Mentor Graphics Community Feed

Copy and pasting of traces does not always work.

community_admin@mentor.com — Tue, 18 Jun 2013 21:43:10 GMT

I have had problems doing copy and pasting of traces a vias in Pads layout for a while now. it will copy single traces or a trace and via but not always a group of traces and vias. it seems to be there is some kind of math rounding problems copying and pasting traces.

I took a DDR3 circuit and duplicated the parts and then tried to copy and paste the traces and vias to an identical circuit. It never copies all the traces and vias.

So I submitted an SR and as usual it went into the postponed, never to be fixed, solution area. Any one else see this all the time with SR's ?

Creating a mipt file: Big Picture Questions

community_admin@mentor.com — Tue, 18 Jun 2013 17:51:28 GMT

I apologize in advance if I this information is already out there, but I have read the xCalibrate Batch User's manual multiple times, and still have some fundamental questions. Background: I am using Calibre 2009 in an academic environment, and am trying to create the PEX file for a fairly simple experimental IC process.

When I think of any basic IC process, I consider there to be two mutually exclusive areas of ACTIVE, and FIELD OXIDE. It appears as though Pex will use "type=diffusion" to determine when a region is ACTIVE, instead of FIELD OXIDE, but how does it know which dielectric in the stack is deleted to create the ACTIVE region?
I assume it removes the detected devices during LVS, and only extracts parasticis from layers that still exist after the intentional devices have been removed, yes?
I have a PIP cap with a thin dielectric that only exists when both polys are on top of each other. Can Ihandle this with a properly configured confromal dielectric, or do I need to specify three custom layer stacks, one with one poly, one with the other, and one with both and the deielectric?

Thanks in Advance,

Paul

Deleting a copper segment.

community_admin@mentor.com — Tue, 09 Aug 2011 11:08:06 GMT

Hi all,

I'm new to padslayout.I need to create a decal using the copper/coppercutout.I want to delete some portions of the copper cutout which is circular in shape by relative position method.

How can i delete a circular copper cutout using a position relative to the reference coordinate.

Please give the suggestions.

Regards,

Anupama

how to differentiate horizontal and vertical swipes

community_admin@mentor.com — Tue, 18 Jun 2013 11:58:47 GMT

Im a new user for this product. i want to know how to differentiate between swipes both horizontal as well as vertical.

i.e If i swipe vertically upwards it must give me a display and if i swipe it verically down it must give another diplay.(same is case in horizontal i.e left and right)

how to differentiate swipes

community_admin@mentor.com — Tue, 18 Jun 2013 11:47:07 GMT

Im a new user for this product. I want to know how to differentiate b/w swipes i.e within the horizontal (left & right) & in vertical(upwards & downwards).

i.e I want to get a display on swiping up and another display on swiping down(same is the case with horizontal).

Generating PDF of Vesys Classic Schematics

community_admin@mentor.com — Mon, 17 Jun 2013 11:10:34 GMT

Hi,

I would like to know is there any plugin or macro to generate the PDF for the schematics drawn in the Vesys Classic of the entire Vehicle.

In general, we have option to create pdf manually to each system and by this way it takes lot of time to generate the pdf of entire vehicle as we have 50-60 schematics.

Please let me know if there is any short way to generate the pdfs in few steps or at one go.

Thanks & Regards,

-Navaneeth

two finger tap as a gesture

community_admin@mentor.com — Tue, 18 Jun 2013 03:53:55 GMT

Hi,

Is there any gesture recognizer for two finger tap in inflexion. If not is there any other algorithm to implement two finger tap as a gesture. Can you please suggest some reference material for implementing two finger tap in inflexion.

Thanks and Regards.

Library conversion issue

community_admin@mentor.com — Tue, 18 Jun 2013 00:05:23 GMT

I was using PADS 5.1V and now I have started using PADS 9.3V. I want to know how to convert my old version library to higher version? Send the reply at the earliest.

Installing powerPCB ver 5.2a, pwrshell failure.

community_admin@mentor.com — Mon, 17 Jun 2013 21:21:27 GMT

Hi,

So I have been reading the forums and working through this problem for a couple of weeks now and I really am at an end. I have a valid licence and teal key (correct key code) for PowerPCB. The program is installed correctly and will run in demo mode with no problems. When I run LMTOOLS, ver 8.2a (came with original software) I can not see the hardware key, but using LMTOOLS ver 11.6.1.0, I can see the hardware key, but PowerPCB still runs in demo mode. So to my question; is there instructions for setting up PowerPCB under windows 7?

Thanks,

Kim

Unable to Merge Bundles

community_admin@mentor.com — Mon, 17 Jun 2013 20:06:41 GMT

Why am I unable to "Delete" or "Merge Bundles" on some Nodes in VeSys Harness Design?

Script to place text as INDEX of the project

community_admin@mentor.com — Mon, 17 Jun 2013 08:52:49 GMT

Hi,

First of all, Does it exist a manual or guide about the commands to use in DxDesigner scripts?

My question is:

Is it possible to build a script that place rows of text as index of the project?

E.g.:

TOPSHEET.........1

SUPPLY..............2

and so on.... where the number is the @PRINTPRDER properties and the name of the is the @NAME properties.

Thanks Very much.

CodeBench Lite - ARM compilerproduce different object file for the same source file !!

community_admin@mentor.com — Wed, 12 Jun 2013 14:17:29 GMT

Using the GCC compiler for ARM (windows) :

arm-none-eabi-gcc.exe (Sourcery CodeBench Lite 2012.09-63) 4.7.2 version

I have got different object file produced every ~5 times i compiled the same source file.

The optimization level 3 is used (aggressive) is used, compiler options used:

-O3 -mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -fshort-wchar -fshort-enums -funsafe-math-optimizations -mvectorize-with-neon-quad

The dump of the different object files shows too many differences in assembly instructions , registers and addresses used.

Is it normal that compiler optimize/compile exactly the same source file differently and produce different object files ?! is it a compiler bug ?
How to avoid this behavior without turning off aggressive optimization ?

ASCII File and Raster Silkscreen images

community_admin@mentor.com — Fri, 14 Jun 2013 12:04:09 GMT

Is there anyway to define a raster/bitmap silkscreen image in PADS ASCII file? I've inserted paintbrush picture object in a PADS designs and then exported it to a ASCII file(selected all items) ......but when I import it into PADS, the bitmap don't show. Any Suggestions? Is there any way to define a single color image pixels by pixels in the ASCII file?

Software download link for 'ProtoView'

community_admin@mentor.com — Mon, 17 Jun 2013 09:40:04 GMT

Hi,

Can anyone please help me with download link for 'Mentor ProtoView Software'?

Regards,

Udaya

Footprint Reporting

community_admin@mentor.com — Mon, 17 Jun 2013 14:05:45 GMT

My project has over 600 slots in an integrator plane.

I’m currently investigating the introduction of (new to Capital 11.1) applying library footprints to the devices that are placed in the slots to manage cavity assignments.

I would like to track how well my plane is being populated as I progress and I would like to use the simplicity of the Connectivity Reporting mechanism in Integrator to help me do this.

I would like to report out information from devices like e.g.

The part number assigned to the device

The footprint Name

And other attribute information

And I would like to report out connector part numbers assigned to virtual connectors via the footprint.

With this new footprint capability you have introduced can you offer a more advanced reporting mechanism to take advantage of the additional attributes that have now become accessible.

Adding stitching via's in a ground plane

community_admin@mentor.com — Mon, 17 Jun 2013 08:54:14 GMT

I'm kind of new to pads and can't find how to add a via inside a ground plane.

I do have some designs that where made in the past that do contain these via's (see attached screendump). Only they were made by my predecessor.

Any suggestions on how to add them?

Best,

Willem

Script to export DXF in PADS.

community_admin@mentor.com — Mon, 17 Jun 2013 05:59:06 GMT

Hoi,

I'm looking for the command(s) on how the build a script to automate the DXF export in PADS 9.3.

Greetings,

Corné Voogt

Layout pan, tilt and zoom by scroll wheel

community_admin@mentor.com — Mon, 17 Jun 2013 10:38:35 GMT

I just started up a new design and found my scroll wheel functions not working in pads layout.

In Logic and router they do function and on an other machine it's no issue, but on my laptop it just quit.

It's probebly a small thing to get it back, but kind of annoying when it's not working.

Best,
Willem

Thermal simulations with emmbedded resistors

community_admin@mentor.com — Mon, 17 Jun 2013 08:22:30 GMT

Hello,

Topic of my Master Thesis is Thermal simulation of buried resistors.

After making couple of project with embedded resistors i have conclusions that it is imposible to do.

HyperLynx show errors about components in inside layers.

Is this possible to simulate this components?

Thanks and Regards,

Slawek

double tap using a timer in inflexion

community_admin@mentor.com — Mon, 17 Jun 2013 05:53:20 GMT

Hi,

I have an icon which should recognize double tap i.e., if we set 500ms as max duration and if there is a second tap on icon within the 500ms after the first tap occurance on the icon, then the layout should switch. Can you suggest me some reference material for including a double tap based on a timer for switching a layout in inflexion ui express.

Thanks and Regards.

anti pad can not display

community_admin@mentor.com — Fri, 14 Jun 2013 09:52:06 GMT

Hi,

I set the antipad in the pad stacks,but can not see the antipad on the inner layer in PCB.(can see the antipad before)How can I see the antipad for well supporting of my design.

using Pad2007 tool and Dell computer.

Thanks and Best Regards.

"Numeric Error During Property Evaluation" In LVS

community_admin@mentor.com — Fri, 14 Jun 2013 06:20:34 GMT

Hi,

I am having issue "Numeric Error During Property Evaluation" when I LVS. The LVS is Correct and Clean. But the Error Appears in My Transcript.

Some Details of the Run,

The Layout I am running, Consists of multiple number of same instance.

The Instance itself DRC and LVS Clean, and there is no Numeric Evaluation Error at instance Level.

The Error starts only when I put more then 2 of them together.

The Error in Transcript is as Follows,

****************************************************************************

ERROR: Numeric error during property evaluation.

Rule file: $..../XYZ.dgo.extract.cal

Device: d(nwp_p) (line XYX of rule file)

Cell: ABC

Instance: 0 x:0 y:4.715

Argument for truncate must be not exceed 2,147,483,647 in absolute Value.

*****************************************************************************

The co-ordinate, (0,4.715) is where my N-Well is. I am not sure how it is related to N-Well location, the co-ordinate moves with N-Well.

Can someone give some sugesstions/ideas for solving it! and explain what is Physically causing the problem.

Thanks in Advance.

Regards,

Aarthy

Tip of the Week: How to list the DOS %PATH% variable in a readable format

community_admin@mentor.com — Sun, 16 Jun 2013 07:03:03 GMT

I have always found the Windows %PATH% variable difficult to read. There are normally multiple lines and the ";" separator is difficult to see.

It turns out I am not alone; yesterday a colleague sent me the following command to report the contents of that variable (or any other) from a DOS window in a simple to read format.

echo %PATH:;=&echo.%

I predict this command will be appearing on a post-it-note near your screen very soon!

Please give me a reason to keep sticking with PADS

community_admin@mentor.com — Wed, 12 Jun 2013 06:09:07 GMT

Ok, I'm a little bit stressed out in here. I'm running basically a one man engineering office. I have PADS LS Suite and use mostly Logic and PADS Layout - only occasionally PADS Router but no DxDesigner at all.

With the new design where I need to apply SDRAM or even DDR, it would help alot to have length control for routing the bus. A signal integrity check would be nice feature as well and for few times I have missed differential routing rules that are not included in PADS Router in LS suite.

These features I can get my upgrading my PADS to ES Suite, but it does cost money. Plus to this, my annual subscription would double. So, I've started to look for other options as well... And one is Altium Designer, that is half the price of ES Suite, but about the same in cost of LS -> ES upgrade. I have evaluated Altium now a little bit and it does look like a nice tool. I probably does have its flaws as well, but features are many and from my point of view most what I would use are quite capable doing what they were designed to do. Absolutely welcome features are things like gerber tools (I can view gerbers I made, I can do panelizing) or generating STEP models from my boards (I have had requests from my clients for this and IDF is NOT an solution unless I want to ask for my clients each time to buy a IDF importer plugin for their MCAD just for importing this one object to their system, that's plain silly).

The schematic capture is also quite nice looking although it will take time to get used to it. I guess DxDesigner comes close to it in features such as reusability and blocking your repeatable parts of your design but there is a learning curve as well thus no matter what route I go I need to familiarize myself with the new tool. Altium also offers lots of ready made library components that can be used to build your own library quicker (saves tons of time for new components, like MCU's). Also trainings are either free (when under subscription) or at least very, very reasonable priced. I can't help but feel that Altium offers more bang for a buck. I'm starting to feeling like I'm a too small user for Mentor Graphics for it to be the supplier for my EDA software.

I don't know, I'm pulling my hair off while I'm trying to make the decision between these two options. Then again I have also a third option: just to try going on with the current tools even if it is not the perfect choice.

Strange behavior from Paste Mask Pads

community_admin@mentor.com — Fri, 24 May 2013 18:08:47 GMT

Imagine a thru hole connector that is going to be placed by automated SMT equipment on a PCB. Since it is going to be placed with automation and reflowed you'd also want solder paste on the PCB (in the holes) while it's being inserted. Thus you would want solder paste openings in your solder paste stencil. To get openings in your stencil, you'd want "something" associated with the opening presumably on the Paste Mask Top (assuming the connector is inserted into the PCB from the top side) layer in the pad stack. The easiest thing for the "something" to be would be a Pad right?

Why will CAM not pick up Paste Mask Pads for thru holes? If there is no drill associated with the pad stack (an SMT pad) a Paste Mask Pad shows up just fine in CAM but if it has a drill associated with the pad stack you MUST Associate Copper on the Paste Mask Layer to get anything to show up.

Why, why, why?? I'd prefer to just be able to handle this via the Pad Stack than have to draw Copper shapes and Associate them.

Thanks for any info!

Chris

DDR3_VTT voltage selection

community_admin@mentor.com — Sat, 15 Jun 2013 00:17:17 GMT

I have a .HYP board file for my design, and I exported a free form schematic of one of my DDR3 address lines. It was terminated to GND thru a 30 ohm resistor, so I changed the ground symbol to DDR3_VTT, but underneath the "DDR3_VTT", it says "0V", and obviously my simulation doesn't work properly with the net terminated to 0V rather than 0.75V. How can I modify that symbol to give the correct termination voltage?

Macro black boxing without extraction

community_admin@mentor.com — Tue, 11 Jun 2013 07:11:05 GMT

Hi,

I have a macro cell placed in the toplevel. The macro level routes are shorting with the top level routes. I need an option to avoid the extraction of that particular macro. LVS BOX is not working as it will extract and not compare as i understand. Since the macro level route is causing a top level VDD/VSS short, my lvs is not clean. Please help.

Thanks.
Arjun

Router_Session.log

community_admin@mentor.com — Fri, 14 Jun 2013 14:15:50 GMT

Has anyone seen this before, and if so, how do I fix? I can't get the Router to fire up.

V9.5.

Thanks,

-Jason

Need an idea how to indicate an automation script is still running

community_admin@mentor.com — Tue, 11 Jun 2013 20:54:15 GMT

I'm writing a script to make modifications to components based on certain part numbers, and I'm getting all the components in one collection, so I am not traversing the hierarchy. This means the Dx window just sits there while the script is running. Is there a good way to display something (i.e. rotating hourglass) showing the user that the script is still running?

Thanks in advance!

How to check the Acute Angle ?

community_admin@mentor.com — Fri, 14 Jun 2013 04:48:58 GMT

Hello ?

Do you know how to check the Acute angle tracks through Valor Vsure in Fab Analysis ?

Thanks and Regards

sabitha