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    <title>CAMBIA Patent Lens Search - (front_page:G11C*)</title>
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    <description>CAMBIA Patent Lens - Patent Search RSS Feed</description>
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    <item>
      <title>Recording medium editing apparatus based on content supply source</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1094466_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Recording medium editing apparatus based on content supply source&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1094466_B1"&gt;EP_1094466_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;00309107.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2000-10-17&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1094466_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>IMPROVED METHOD FOR READING A NON-VOLATILE MEMORY CELL ADJACENT TO AN INACTIVE REGION OF A NON-VOLATILE MEMORY CELL ARRAY</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1590810_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;IMPROVED METHOD FOR READING A NON-VOLATILE MEMORY CELL ADJACENT TO AN INACTIVE REGION OF A NON-VOLATILE MEMORY CELL ARRAY&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1590810_B1"&gt;EP_1590810_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;04700871.9&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2004-01-08&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1590810_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Power-saving reading of magnetic memory devices</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1612801_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Power-saving reading of magnetic memory devices&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1612801_B1"&gt;EP_1612801_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;05014294.2&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2003-05-28&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1612801_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Semiconductor integrated circuit and nonvolatile memory element</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1703520_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Semiconductor integrated circuit and nonvolatile memory element&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1703520_B1"&gt;EP_1703520_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;06011387.5&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2000-01-19&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1703520_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>THREE-DIMENSIONAL NANOSCALE CROSSBARS</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1875476_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;THREE-DIMENSIONAL NANOSCALE CROSSBARS&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1875476_B1"&gt;EP_1875476_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;06751576.7&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2006-04-25&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1875476_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>A non-volatile, electrically-programmable memory with a plurality of storage densities and data transfer speeds</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1892720_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;A non-volatile, electrically-programmable memory with a plurality of storage densities and data transfer speeds&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1892720_B1"&gt;EP_1892720_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;06119479.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2006-08-24&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1892720_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1899975_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;INTEGRATED CIRCUIT WITH SEPARATE SUPPLY VOLTAGE FOR MEMORY THAT IS DIFFERENT FROM LOGIC CIRCUIT SUPPLY VOLTAGE&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1899975_B1"&gt;EP_1899975_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;06774493.8&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2006-06-30&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1899975_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>METHOD FOR PROGRAMMING OF MULTI-STATE NON-VOLATILE MEMORY USING SMART VERIFY</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1946323_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;METHOD FOR PROGRAMMING OF MULTI-STATE NON-VOLATILE MEMORY USING SMART VERIFY&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1946323_B1"&gt;EP_1946323_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;06826985.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2006-10-26&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1946323_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Methods of programming non-volatile memory cells</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2048667_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Methods of programming non-volatile memory cells&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2048667_B1"&gt;EP_2048667_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-27&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08164640.8&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2008-09-18&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 27 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2048667_B1</guid>
      <dc:date>2011-07-27T00:00:00Z</dc:date>
    </item>
    <item>
      <title>SOFTWARE REFRESHED MEMORY DEVICE AND METHOD</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1540657_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;SOFTWARE REFRESHED MEMORY DEVICE AND METHOD&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1540657_B1"&gt;EP_1540657_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-20&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;03749204.8&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2003-08-28&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 20 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1540657_B1</guid>
      <dc:date>2011-07-20T00:00:00Z</dc:date>
    </item>
    <item>
      <title>MEMORY BUS OUTPUT DRIVER OF A MULTI-BANK MEMORY DEVICE AND METHOD THEREFOR</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2082399_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;MEMORY BUS OUTPUT DRIVER OF A MULTI-BANK MEMORY DEVICE AND METHOD THEREFOR&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2082399_B1"&gt;EP_2082399_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-20&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;07863608.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2007-10-29&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 20 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2082399_B1</guid>
      <dc:date>2011-07-20T00:00:00Z</dc:date>
    </item>
    <item>
      <title>BITLINE GOVERNED APPROACH FOR PROGRAM CONTROL OF NON-VOLATILE MEMORY</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1751771_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;BITLINE GOVERNED APPROACH FOR PROGRAM CONTROL OF NON-VOLATILE MEMORY&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1751771_B1"&gt;EP_1751771_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-13&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;05737998.4&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2005-04-20&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 13 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1751771_B1</guid>
      <dc:date>2011-07-13T00:00:00Z</dc:date>
    </item>
    <item>
      <title>BIAS APPLICATION METHOD OF STORAGE AND STORAGE</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1830366_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;BIAS APPLICATION METHOD OF STORAGE AND STORAGE&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1830366_B1"&gt;EP_1830366_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-13&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;04807686.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2004-12-24&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 13 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1830366_B1</guid>
      <dc:date>2011-07-13T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Magnetic tunnel junction device, magnetic memory adopting the same, magnetic memory cell and access method of the same</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1107329_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Magnetic tunnel junction device, magnetic memory adopting the same, magnetic memory cell and access method of the same&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1107329_B1"&gt;EP_1107329_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-06&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;00126994.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2000-12-08&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 06 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1107329_B1</guid>
      <dc:date>2011-07-06T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Read/write protected electrical fuse architecture</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1111618_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Read/write protected electrical fuse architecture&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1111618_B1"&gt;EP_1111618_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-06&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;00311625.8&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2000-12-22&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 06 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1111618_B1</guid>
      <dc:date>2011-07-06T00:00:00Z</dc:date>
    </item>
    <item>
      <title>HARDWARE SECURITY DEVICE FOR MAGNETIC MEMORY CELLS</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1576615_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;HARDWARE SECURITY DEVICE FOR MAGNETIC MEMORY CELLS&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1576615_B1"&gt;EP_1576615_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-06&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;03813278.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2003-12-15&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 06 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1576615_B1</guid>
      <dc:date>2011-07-06T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Nonvolatile memory device with multiple references and corresponding control method</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1750281_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Nonvolatile memory device with multiple references and corresponding control method&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1750281_B1"&gt;EP_1750281_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-06&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;05425564.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2005-07-29&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 06 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1750281_B1</guid>
      <dc:date>2011-07-06T00:00:00Z</dc:date>
    </item>
    <item>
      <title>NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1866932_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;NON-VOLATILE MEMORY AND METHOD WITH COMPENSATION FOR SOURCE LINE BIAS ERRORS&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1866932_B1"&gt;EP_1866932_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-06&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;06748943.5&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2006-03-29&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 06 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1866932_B1</guid>
      <dc:date>2011-07-06T00:00:00Z</dc:date>
    </item>
    <item>
      <title>METHOD FOR NON-REAL TIME REPROGRAMMING OF NON-VOLATILE MEMORY TO ACHIEVE TIGHTER DISTRIBUTION OF THRESHOLD VOLTAGES</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2030205_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;METHOD FOR NON-REAL TIME REPROGRAMMING OF NON-VOLATILE MEMORY TO ACHIEVE TIGHTER DISTRIBUTION OF THRESHOLD VOLTAGES&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2030205_B1"&gt;EP_2030205_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-06&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;07797758.5&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2007-05-25&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 06 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2030205_B1</guid>
      <dc:date>2011-07-06T00:00:00Z</dc:date>
    </item>
    <item>
      <title>A METHOD FOR PROGRAMMING AND ERASING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZE BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2030206_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;A METHOD FOR PROGRAMMING AND ERASING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZE BIT DISTURBANCES AND VOLTAGE WITHSTAND REQUIREMENTS FOR THE MEMORY ARRAY AND SUPPORTING CIRCUITS&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2030206_B1"&gt;EP_2030206_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-07-06&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;07797769.2&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2007-05-25&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 06 Jul 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2030206_B1</guid>
      <dc:date>2011-07-06T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Data storage circuits using a low threshold voltage output enable circuit</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1093128_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Data storage circuits using a low threshold voltage output enable circuit&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1093128_B1"&gt;EP_1093128_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;00303330.5&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2000-04-19&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1093128_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Multiple data rate memory</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1439543_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Multiple data rate memory&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1439543_B1"&gt;EP_1439543_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;04076067.0&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2000-08-03&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1439543_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>A POLYMER MEMORY HAVING A FERROELECTRIC POLYMER MEMORY MATERIAL WITH CELL SIZES THAT ARE ASYMMETRIC</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1661141_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;A POLYMER MEMORY HAVING A FERROELECTRIC POLYMER MEMORY MATERIAL WITH CELL SIZES THAT ARE ASYMMETRIC&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1661141_B1"&gt;EP_1661141_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;04781827.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2004-08-20&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1661141_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>STORAGE DEVICE AND HOST APPARATUS</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1769331_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;STORAGE DEVICE AND HOST APPARATUS&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1769331_B1"&gt;EP_1769331_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;05760161.9&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2005-07-08&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1769331_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>PROGRAM TIME ADJUSTMENT AS FUNCTION OF PROGRAM VOLTAGE FOR IMPROVED PROGRAMMING SPEED</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2005439_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;PROGRAM TIME ADJUSTMENT AS FUNCTION OF PROGRAM VOLTAGE FOR IMPROVED PROGRAMMING SPEED&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2005439_B1"&gt;EP_2005439_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;07758602.2&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2007-03-15&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2005439_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2132750_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2132750_B1"&gt;EP_2132750_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08708985.0&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2008-02-14&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2132750_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Leakage compensation for sample and hold devices</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2166541_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Leakage compensation for sample and hold devices&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2166541_B1"&gt;EP_2166541_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;09170332.2&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2009-09-15&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2166541_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Stacked memory device and method thereof</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2175453_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Stacked memory device and method thereof&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2175453_B1"&gt;EP_2175453_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;09172675.2&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2009-10-09&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2175453_B1</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Method and device for at-speed storage of faults for built-in self-repair (BISR) of embedded-RAMs</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1480228_B9</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Method and device for at-speed storage of faults for built-in self-repair (BISR) of embedded-RAMs&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1480228_B9"&gt;EP_1480228_B9&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-29&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;03291208.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2003-05-22&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 29 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1480228_B9</guid>
      <dc:date>2011-06-29T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Micro-tile memory interface</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2006858_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Micro-tile memory interface&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2006858_B1"&gt;EP_2006858_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-22&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08016184.7&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2006-06-30&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 22 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2006858_B1</guid>
      <dc:date>2011-06-22T00:00:00Z</dc:date>
    </item>
    <item>
      <title>INTEGRATED CIRCUIT WITH MOSFET FUSE ELEMENT</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2250671_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;INTEGRATED CIRCUIT WITH MOSFET FUSE ELEMENT&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2250671_B1"&gt;EP_2250671_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-22&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;09716959.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2009-02-20&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 22 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2250671_B1</guid>
      <dc:date>2011-06-22T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Magnetic random access memory and method of reading data from the same</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1564750_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Magnetic random access memory and method of reading data from the same&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1564750_B1"&gt;EP_1564750_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-15&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;04258119.9&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2004-12-24&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 15 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1564750_B1</guid>
      <dc:date>2011-06-15T00:00:00Z</dc:date>
    </item>
    <item>
      <title>METHOD AND APPARATUS FOR IMPLICIT DRAM PRECHARGE</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1668646_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;METHOD AND APPARATUS FOR IMPLICIT DRAM PRECHARGE&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1668646_B1"&gt;EP_1668646_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-15&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;04789296.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2004-09-29&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 15 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1668646_B1</guid>
      <dc:date>2011-06-15T00:00:00Z</dc:date>
    </item>
    <item>
      <title>AC SENSING FOR A RESISTIVE MEMORY</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1673780_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;AC SENSING FOR A RESISTIVE MEMORY&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1673780_B1"&gt;EP_1673780_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-15&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;04794289.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2004-10-06&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 15 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1673780_B1</guid>
      <dc:date>2011-06-15T00:00:00Z</dc:date>
    </item>
    <item>
      <title>METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1829048_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;METHOD OF PROGRAMMING, READING AND ERASING MEMORY-DIODE IN A MEMORY-DIODE ARRAY&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1829048_B1"&gt;EP_1829048_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-15&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;05855031.0&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2005-12-20&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 15 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1829048_B1</guid>
      <dc:date>2011-06-15T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Semiconductor memory</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1947651_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Semiconductor memory&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1947651_B1"&gt;EP_1947651_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-15&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08153074.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2002-03-28&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 15 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1947651_B1</guid>
      <dc:date>2011-06-15T00:00:00Z</dc:date>
    </item>
    <item>
      <title>AC sensing for a resistive memory</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2026353_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;AC sensing for a resistive memory&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2026353_B1"&gt;EP_2026353_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-15&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08019815.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2004-10-06&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 15 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2026353_B1</guid>
      <dc:date>2011-06-15T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Systems and methods for maintaining data integrity of removable media of an electronic device</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2159798_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Systems and methods for maintaining data integrity of removable media of an electronic device&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2159798_B1"&gt;EP_2159798_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-15&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;09177240.0&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2007-01-23&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 15 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2159798_B1</guid>
      <dc:date>2011-06-15T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Synchronous semiconductor memory device</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1293984_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Synchronous semiconductor memory device&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1293984_B1"&gt;EP_1293984_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-08&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;02020557.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2002-09-17&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 08 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1293984_B1</guid>
      <dc:date>2011-06-08T00:00:00Z</dc:date>
    </item>
    <item>
      <title>SOLID ELECTROLYTE SWITCHING DEVICES, FPGA AND MEMORY DEVICES USING THE SAME, AND METHOD OF MANUFACTURING THE SAME</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1501124_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;SOLID ELECTROLYTE SWITCHING DEVICES, FPGA AND MEMORY DEVICES USING THE SAME, AND METHOD OF MANUFACTURING THE SAME&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1501124_B1"&gt;EP_1501124_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-08&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;03719228.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2003-04-25&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 08 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1501124_B1</guid>
      <dc:date>2011-06-08T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Memory cell for use in an integrated circuit</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1780728_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Memory cell for use in an integrated circuit&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1780728_B1"&gt;EP_1780728_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-08&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;07002959.0&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2002-11-19&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 08 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1780728_B1</guid>
      <dc:date>2011-06-08T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Accelerated P-channel dynamic register</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1887692_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Accelerated P-channel dynamic register&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1887692_B1"&gt;EP_1887692_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-08&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;06254819.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2006-09-15&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 08 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1887692_B1</guid>
      <dc:date>2011-06-08T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Semiconductor memory device</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1970910_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Semiconductor memory device&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1970910_B1"&gt;EP_1970910_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-08&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08152570.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2008-03-11&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 08 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1970910_B1</guid>
      <dc:date>2011-06-08T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Semiconductor memory system for flash memory</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2015311_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Semiconductor memory system for flash memory&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2015311_B1"&gt;EP_2015311_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-08&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08017121.8&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2007-04-18&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 08 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2015311_B1</guid>
      <dc:date>2011-06-08T00:00:00Z</dc:date>
    </item>
    <item>
      <title>PROVIDING ENERGY REDUCTION WHEN STORING DATA IN A MEMORY</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2176865_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;PROVIDING ENERGY REDUCTION WHEN STORING DATA IN A MEMORY&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2176865_B1"&gt;EP_2176865_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-08&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08786937.6&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2008-08-06&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 08 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2176865_B1</guid>
      <dc:date>2011-06-08T00:00:00Z</dc:date>
    </item>
    <item>
      <title>MAGNETIC STORAGE UNIT USING FERROMAGNETIC TUNNEL JUNCTION ELEMENT</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1484766_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;MAGNETIC STORAGE UNIT USING FERROMAGNETIC TUNNEL JUNCTION ELEMENT&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1484766_B1"&gt;EP_1484766_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-01&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;03706934.1&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2003-02-07&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 01 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1484766_B1</guid>
      <dc:date>2011-06-01T00:00:00Z</dc:date>
    </item>
    <item>
      <title>METHOD FOR DETECTING RESISTIVE BRIDGE DEFECTS IN THE GLOBAL DATA BUS OF SEMICONDUCTOR MEMORIES</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1728254_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;METHOD FOR DETECTING RESISTIVE BRIDGE DEFECTS IN THE GLOBAL DATA BUS OF SEMICONDUCTOR MEMORIES&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1728254_B1"&gt;EP_1728254_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-01&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;05708915.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2005-03-03&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 01 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1728254_B1</guid>
      <dc:date>2011-06-01T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Oscillating device, method of adjusting the same and memory</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2015309_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Oscillating device, method of adjusting the same and memory&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2015309_B1"&gt;EP_2015309_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-01&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;08159040.8&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2008-06-25&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 01 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2015309_B1</guid>
      <dc:date>2011-06-01T00:00:00Z</dc:date>
    </item>
    <item>
      <title>NON-VOLATILE MEMORY AND METHOD FOR REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2062265_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;NON-VOLATILE MEMORY AND METHOD FOR REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2062265_B1"&gt;EP_2062265_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-06-01&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;07814597.6&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2007-08-30&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 01 Jun 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_2062265_B1</guid>
      <dc:date>2011-06-01T00:00:00Z</dc:date>
    </item>
    <item>
      <title>Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features</title>
      <link>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1657722_B1</link>
      <description>&lt;table&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Title&lt;/th&gt;&lt;td&gt;Integrated circuit chip having non-volatile on-chip memories for providing programmable functions and features&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;number&lt;/th&gt;      &lt;td&gt;&lt;a href="http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1657722_B1"&gt;EP_1657722_B1&lt;/a&gt;&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Publication&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2011-05-25&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;number&lt;/th&gt;&lt;td&gt;05021147.3&lt;/td&gt;
  &lt;/tr&gt;
  &lt;tr&gt;
    &lt;th align="right" valign="top"&gt;Filing&amp;nbsp;date&lt;/th&gt;&lt;td&gt;2005-09-28&lt;/td&gt;
  &lt;/tr&gt;
&lt;/table&gt;</description>
      <pubDate>Wed, 25 May 2011 00:00:00 GMT</pubDate>
      <guid>http://www.patentlens.net/patentlens/structured.cgi?patnum=EP_1657722_B1</guid>
      <dc:date>2011-05-25T00:00:00Z</dc:date>
    </item>
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