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	<title>FPGA Blog</title>
	
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		<title>Xilinx 7 Series FPGAs, Zynq-7000 SoCs Achieved Full PCI Express Compliance</title>
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		<comments>http://fpgablog.com/posts/xilinx-pci-sig-28nm/#comments</comments>
		<pubDate>Tue, 21 May 2013 12:39:07 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[7 series FPGAs]]></category>
		<category><![CDATA[All Programmable]]></category>
		<category><![CDATA[PCI Express Compliance]]></category>
		<category><![CDATA[PCI-SIG]]></category>
		<category><![CDATA[SoCs]]></category>
		<category><![CDATA[Xilinx]]></category>
		<category><![CDATA[Zynq-7000]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4442</guid>
		<description><![CDATA[Xilinx&#8217;s All Programmable 7 series FPGAs and Zynq-7000 All Programmable SoCs have achieved full PCI Express compliance and are now listed on the PCI-SIG integrator&#8217;s list. With 7 series FPGA and Zynq-7000 All Programmable SoC integrated blocks for PCI Express Gen2 and Gen3, designers can meet high system bandwidth and programmable systems integration requirements needed [...]]]></description>
				<content:encoded><![CDATA[<p>Xilinx&#8217;s All Programmable 7 series FPGAs and Zynq-7000 All Programmable SoCs have achieved full PCI Express compliance and are now listed on the PCI-SIG integrator&#8217;s list. With 7 series FPGA and Zynq-7000 All Programmable SoC integrated blocks for PCI Express Gen2 and Gen3, designers can meet high system bandwidth and programmable systems integration requirements needed in a variety of markets, including communications, storage and server applications.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-pci-sig-28nm/">Xilinx 7 Series FPGAs, Zynq-7000 SoCs Achieved Full PCI Express Compliance</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-pci-sig-28nm/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-pci-sig-28nm/" height="61" width="51" /></a></p>
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		<title>CAST Offers Ultra-low Latency Video Encoding Option for H.264 IP Cores</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/ksyPkNtRIfU/</link>
		<comments>http://fpgablog.com/posts/h264-video-encoder/#comments</comments>
		<pubDate>Thu, 16 May 2013 12:42:08 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[IP Core]]></category>
		<category><![CDATA[CAST]]></category>
		<category><![CDATA[H.264]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[Ultra-Low Latency]]></category>
		<category><![CDATA[Video Encoder]]></category>
		<category><![CDATA[Video Encoding]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4437</guid>
		<description><![CDATA[CAST announced an ultra-low latency video encoding option for their H.264 video encoder IP cores. The new option enables near-real time video transmission for streaming and wireless video applications, especially when coupled with CAST&#8217;s hardware stacks for fast, processor-less video processing. Read more CAST Offers Ultra-low Latency Video Encoding Option for H.264 IP Cores Twitter [...]]]></description>
				<content:encoded><![CDATA[<p>CAST announced an ultra-low latency video encoding option for their H.264 video encoder IP cores. The new option enables near-real time video transmission for streaming and wireless video applications, especially when coupled with CAST&#8217;s hardware stacks for fast, processor-less video processing.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/h264-video-encoder/">CAST Offers Ultra-low Latency Video Encoding Option for H.264 IP Cores</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/h264-video-encoder/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/h264-video-encoder/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2013 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p><div class="feedflare">
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		<title>Altera Releases SDK for OpenCL and Third Party Production Boards</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/bAQDGuxLmOI/</link>
		<comments>http://fpgablog.com/posts/preferred-board-partner-program/#comments</comments>
		<pubDate>Mon, 13 May 2013 12:38:46 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Tool]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[FPGAs]]></category>
		<category><![CDATA[Off-the-Shelf Boards]]></category>
		<category><![CDATA[OpenCL]]></category>
		<category><![CDATA[Preferred Board Partner Program]]></category>
		<category><![CDATA[SDK]]></category>
		<category><![CDATA[Software Programmers]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4433</guid>
		<description><![CDATA[Altera has released a SDK for OpenCL and supported third-party production boards. The SDK for OpenCL enables software programmers to access the high-performance capabilities of programmable logic devices. The Altera SDK for OpenCL is currently available for download. The annual software subscription for the SDK for OpenCL is $995 for a node-locked PC license. Read [...]]]></description>
				<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2013/Altera-SDK-OpenCL.jpg" width="468" height="124" alt="Altera SDK for OpenCL and supported third-party production boards" border="0" /></p>
<p>Altera has released a SDK for OpenCL and supported third-party production boards. The SDK for OpenCL enables software programmers to access the high-performance capabilities of programmable logic devices. The Altera SDK for OpenCL is currently available for download. The annual software subscription for the SDK for OpenCL is $995 for a node-locked PC license.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/preferred-board-partner-program/">Altera Releases SDK for OpenCL and Third Party Production Boards</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/preferred-board-partner-program/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/preferred-board-partner-program/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2013 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p><div class="feedflare">
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		<title>Create Fastest FPGA Designs with Altera Quartus II Software v13.0</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/VNljtu3lVes/</link>
		<comments>http://fpgablog.com/posts/soc-quartus-2/#comments</comments>
		<pubDate>Thu, 09 May 2013 12:43:58 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[FPGA Designs]]></category>
		<category><![CDATA[Quartus II]]></category>
		<category><![CDATA[SOC]]></category>
		<category><![CDATA[Software]]></category>
		<category><![CDATA[Tool]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4426</guid>
		<description><![CDATA[Altera released version 13.0 of their Quartus II software. Quartus II v13 enables designs targeting Stratix V FPGAs to achieve the fastest Fmax of any FPGA in the industry with a two speed-grade advantage over the nearest competitor. Both the Subscription Edition and the free Web Edition of Quartus II software v13.0 are now available [...]]]></description>
				<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2013/Altera-Quartus-II-v13.jpg" width="468" height="153" alt="Altera Quartus II software v13.0" border="0" /></p>
<p>Altera released version 13.0 of their Quartus II software. Quartus II v13 enables designs targeting Stratix V FPGAs to achieve the fastest Fmax of any FPGA in the industry with a two speed-grade advantage over the nearest competitor. Both the Subscription Edition and the free Web Edition of Quartus II software v13.0 are now available for download.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/soc-quartus-2/">Create Fastest FPGA Designs with Altera Quartus II Software v13.0</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/soc-quartus-2/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/soc-quartus-2/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2013 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p><div class="feedflare">
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		<title>Avnet Unveils Xilinx Zynq-7000 All Programmable SoC Mini-Module Plus</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/719ifeVe-vo/</link>
		<comments>http://fpgablog.com/posts/ap-fpga-som/#comments</comments>
		<pubDate>Tue, 07 May 2013 12:43:35 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Tool]]></category>
		<category><![CDATA[All Programmable]]></category>
		<category><![CDATA[Avnet Electronics Marketing]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Mini-Module Plus]]></category>
		<category><![CDATA[SOC]]></category>
		<category><![CDATA[Xilinx]]></category>
		<category><![CDATA[Zynq-7000]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4422</guid>
		<description><![CDATA[Avnet Electronics Marketing announced the Xilinx Zynq-7000 All Programmable (AP) SoC Mini-Module Plus. The new product is a system-on-module (SOM) based on the Xilinx Zynq-7000 AP SoC XC7Z045T device. A complete Xilinx Zynq-7000 AP SoC Mini-Module Plus System including Mini-Module Plus baseboard, Zynq-7000 AP SoC module, and Mini-Module Plus power module is priced at $2,095. [...]]]></description>
				<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2013/Xilinx-Zynq-7000-AP.jpg" width="400" height="287" alt="Xilinx Zynq-7000 AP SoC Mini-Module Plus | Avnet Electronics Marketing" border="0" /></p>
<p>Avnet Electronics Marketing announced the Xilinx Zynq-7000 All Programmable (AP) SoC Mini-Module Plus. The new product is a system-on-module (SOM) based on the Xilinx Zynq-7000 AP SoC XC7Z045T device. A complete Xilinx Zynq-7000 AP SoC Mini-Module Plus System including Mini-Module Plus baseboard, Zynq-7000 AP SoC module, and Mini-Module Plus power module is priced at $2,095.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/ap-fpga-som/">Avnet Unveils Xilinx Zynq-7000 All Programmable SoC Mini-Module Plus</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/ap-fpga-som/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/ap-fpga-som/" height="61" width="51" /></a></p>
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		<item>
		<title>ScanWorks PXI-100 Controller Supports JTAG, PCT, FPGA Controlled Tests, Internal JTAG</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/Qndp8nryNqo/</link>
		<comments>http://fpgablog.com/posts/asset-intertech-fct/#comments</comments>
		<pubDate>Tue, 30 Apr 2013 12:52:57 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Tool]]></category>
		<category><![CDATA[FPGA-controlled Tests]]></category>
		<category><![CDATA[Internal JTAG]]></category>
		<category><![CDATA[PCT]]></category>
		<category><![CDATA[ScanWorks PXI-100 Controller Supports JTAG]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4415</guid>
		<description><![CDATA[ASSET InterTech introduced the PXI-100 controller for the ScanWorks platform for debug, validation and test. The PXI-based controller can apply boundary-scan tests based on the IEEE 1149.1/6 standards (JTAG), processor-controlled tests (PCT), FPGA-controlled tests (FCT) and access instruments embedded in chips via the IEEE P1687 Internal JTAG (IJTAG) standard. The PXI-1000 ScanWorks platform controller is [...]]]></description>
				<content:encoded><![CDATA[<p><img src="http://fpgablog.com/primages/2013/ScanWorks-PXI-1000-controller.jpg" width="400" height="241" alt="ASSET InterTech PXI-100 controller for the ScanWorks platform" border="0"/></p>
<p>ASSET InterTech introduced the PXI-100 controller for the ScanWorks platform for debug, validation and test. The PXI-based controller can apply boundary-scan tests based on the IEEE 1149.1/6 standards (JTAG), processor-controlled tests (PCT), FPGA-controlled tests (FCT) and access instruments embedded in chips via the IEEE P1687 Internal JTAG (IJTAG) standard. The PXI-1000 ScanWorks platform controller is available now. Prices start at $4,995.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/asset-intertech-fct/">ScanWorks PXI-100 Controller Supports JTAG, PCT, FPGA Controlled Tests, Internal JTAG</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/asset-intertech-fct/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/asset-intertech-fct/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2013 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p><div class="feedflare">
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		<title>Lattice Sensor Extender Reference Design Uses Two MachXO2 FPGAs</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/slhdJHhM88Q/</link>
		<comments>http://fpgablog.com/posts/lattice-image-sensor-extender/#comments</comments>
		<pubDate>Thu, 25 Apr 2013 12:52:17 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Reference Design]]></category>
		<category><![CDATA[Image Sensor Extender]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[MachXO2 FPGA]]></category>
		<category><![CDATA[SensorExtender]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4404</guid>
		<description><![CDATA[Lattice Semiconductor recently introduced the SensorExtender reference design. The Sensor Extender is a low-cost solution for remotely locating image sensors up to eight meters away from the image signal processor (ISP) and transmit and receive video signals at resolutions that range up to 720p60 and 1080p30. The reference design is tested with the Aptina MT [...]]]></description>
				<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2013/Lattice-SensorExtender.jpg" width="400" height="246" alt="Lattice Semiconductor SensorExtender reference design" border="0" /></p>
<p>Lattice Semiconductor recently introduced the SensorExtender reference design. The Sensor Extender is a low-cost solution for remotely locating image sensors up to eight meters away from the image signal processor (ISP) and transmit and receive video signals at resolutions that range up to 720p60 and 1080p30. The reference design is tested with the Aptina MT MT9M024 and the Lattice HDR-60 camera development kit&#8217;s base board.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/lattice-image-sensor-extender/">Lattice Sensor Extender Reference Design Uses Two MachXO2 FPGAs</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/lattice-image-sensor-extender/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/lattice-image-sensor-extender/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2013 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p><div class="feedflare">
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		<title>Altera Cyclone V SoC Development Kit Includes ARM DS-5</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/51rqkBAWyjU/</link>
		<comments>http://fpgablog.com/posts/hsmc-board/#comments</comments>
		<pubDate>Tue, 23 Apr 2013 12:47:19 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Tool]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[Altera SoC EDS]]></category>
		<category><![CDATA[ARM Development Studio]]></category>
		<category><![CDATA[ARM DS-5]]></category>
		<category><![CDATA[board]]></category>
		<category><![CDATA[Cyclone V SoC]]></category>
		<category><![CDATA[Development Kit]]></category>
		<category><![CDATA[HSMC]]></category>
		<category><![CDATA[Toolkit]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4408</guid>
		<description><![CDATA[Altera introduced the Cyclone V SoC Development Kit. The tool platform features a broad set of memories, peripherals, interfaces, and a high-speed mezzanine connector (HSMC). The Altera kit helps hardware and software developers to accelerate embedded systems design development. The Altera Cyclone V SoC Development Kit is available for ordering now. Production shipment will begin [...]]]></description>
				<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2013/Cyclone-V-SX-SoC-Development-Board.jpg" width="400" height="254" alt="Altera Cyclone V SX SoC Development Board" border="0" /></p>
<p>Altera introduced the Cyclone V SoC Development Kit. The tool platform features a broad set of memories, peripherals, interfaces, and a high-speed mezzanine connector (HSMC). The Altera kit helps hardware and software developers to accelerate embedded systems design development. The Altera Cyclone V SoC Development Kit is available for ordering now. Production shipment will begin in May 2013. It is priced at $1,595.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/hsmc-board/">Altera Cyclone V SoC Development Kit Includes ARM DS-5</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/hsmc-board/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/hsmc-board/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2013 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p><div class="feedflare">
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		<title>Wasga Compiler Design Suite for FPGA Prototyping Supports Virtex-7 FPGA</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/ZPXRRumuDYo/</link>
		<comments>http://fpgablog.com/posts/xilinx-partitioning-tool/#comments</comments>
		<pubDate>Fri, 19 Apr 2013 12:42:45 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Tool]]></category>
		<category><![CDATA[Flexras Technologies]]></category>
		<category><![CDATA[Multi-FPGA]]></category>
		<category><![CDATA[Partitioning Software]]></category>
		<category><![CDATA[Partitioning Tool]]></category>
		<category><![CDATA[Virtex-7 FPGA]]></category>
		<category><![CDATA[Wasga Compiler]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4400</guid>
		<description><![CDATA[Flexras Technologies introduced version 3.2 of the Wasga Compiler Design Suite for FPGA-based prototyping. The new version of the tool supports the Xilinx Virtex-7 FPGA and includes new features that accelerate SoC rapid prototyping. Wasga Compiler is a timing-driven partitioning tool for SoC rapid prototyping that automatically partitions large designs onto multiple FPGAs while addressing [...]]]></description>
				<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2013/Wasga-Compiler.gif" width="329" height="400" alt="Wasga Compiler Design Suite for FPGA-based prototyping | Flexras Technologies" border="0" /></p>
<p>Flexras Technologies introduced version 3.2 of the Wasga Compiler Design Suite for FPGA-based prototyping. The new version of the tool supports the Xilinx Virtex-7 FPGA and includes new features that accelerate SoC rapid prototyping. Wasga Compiler is a timing-driven partitioning tool for SoC rapid prototyping that automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity, and the clock frequency constraints required for running software applications in near real time. Release 3.2 of the tool is available now.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-partitioning-tool/">Wasga Compiler Design Suite for FPGA Prototyping Supports Virtex-7 FPGA</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-partitioning-tool/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-partitioning-tool/" height="61" width="51" /></a></p>
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		<title>Microsemi EnforcIT Cryptography IP Cores Achieves NIST Certification</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/vAZ3C6Fd06o/</link>
		<comments>http://fpgablog.com/posts/infogard-fpga-asic/#comments</comments>
		<pubDate>Wed, 17 Apr 2013 12:47:56 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[IP Core]]></category>
		<category><![CDATA[ASIC]]></category>
		<category><![CDATA[Designs]]></category>
		<category><![CDATA[DOD]]></category>
		<category><![CDATA[EnforcIT Cryptography]]></category>
		<category><![CDATA[InfoGard Laboratories]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[Microsemi]]></category>
		<category><![CDATA[National Institute of Standards and Technology]]></category>
		<category><![CDATA[NIST Certification]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=4394</guid>
		<description><![CDATA[Microsemi has achieved National Institute of Standards and Technology (NIST) algorithmic certification on their U.S.-developed EnforcIT Cryptography Suite of National Security Agency (NSA) Suite B algorithms. The EnforcIT Cryptography Suite was validated by InfoGard Laboratories, Inc. and certified by the NIST. The certification is expected to be posted to the NIST website later this month. [...]]]></description>
				<content:encoded><![CDATA[<p>Microsemi has achieved National Institute of Standards and Technology (NIST) algorithmic certification on their U.S.-developed EnforcIT Cryptography Suite of National Security Agency (NSA) Suite B algorithms. The EnforcIT Cryptography Suite was validated by InfoGard Laboratories, Inc. and certified by the NIST. The certification is expected to be posted to the NIST website later this month.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/infogard-fpga-asic/">Microsemi EnforcIT Cryptography IP Cores Achieves NIST Certification</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/infogard-fpga-asic/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/infogard-fpga-asic/" height="61" width="51" /></a></p>
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