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	<title>FPGA Blog</title>
	
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		<title>Xilinx Introduces Kintex-7 FPGA Embedded Kit</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/ZXKZhT_xni0/</link>
		<comments>http://fpgablog.com/posts/kc705-xc7k325t-2ffg900ces/#comments</comments>
		<pubDate>Thu, 24 May 2012 16:43:08 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Reference Design]]></category>
		<category><![CDATA[Tool]]></category>
		<category><![CDATA[Embedded Kit]]></category>
		<category><![CDATA[Evaluation Board]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[KC705]]></category>
		<category><![CDATA[Kintex-7]]></category>
		<category><![CDATA[Programmable System]]></category>
		<category><![CDATA[XC7K325T-2FFG900CES]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3886</guid>
		<description><![CDATA[Xilinx introduced the Kintex-7 FPGA Embedded Kit. The Xilinx Kintex-7 Embedded Kit includes the components of the Kintex-7 KC705 Base Evaluation Kit plus all additional soft content that embedded system designers need to quickly design their high-performance embedded systems. This includes the embedded targeted reference design and relevant tools such as ISE Embedded Edition software. [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Kintex-7-FPGA-Embedded-Kit.jpg" width="468" height="234" alt="Xilinx Kintex-7 FPGA Embedded Kit " border="0" /></p>
<p>Xilinx introduced the Kintex-7 FPGA Embedded Kit. The Xilinx Kintex-7 Embedded Kit includes the components of the Kintex-7 KC705 Base Evaluation Kit plus all additional soft content that embedded system designers need to quickly design their high-performance embedded systems. This includes the embedded targeted reference design and relevant tools such as ISE Embedded Edition software. The Kintex-7 FPGA Embedded Kit is priced at $1895.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/kc705-xc7k325t-2ffg900ces/">Xilinx Introduces Kintex-7 FPGA Embedded Kit</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/kc705-xc7k325t-2ffg900ces/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/kc705-xc7k325t-2ffg900ces/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<title>CommAgility Introduces AMC-V6L FPGA Processing Module</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/lHVMpFH899I/</link>
		<comments>http://fpgablog.com/posts/xilinx-advancedmc/#comments</comments>
		<pubDate>Tue, 22 May 2012 18:21:08 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Other]]></category>
		<category><![CDATA[AdvancedMC]]></category>
		<category><![CDATA[AMC-V6L]]></category>
		<category><![CDATA[CommAgility]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[LX240T]]></category>
		<category><![CDATA[LX75T-2]]></category>
		<category><![CDATA[module]]></category>
		<category><![CDATA[Virtex-6]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3882</guid>
		<description><![CDATA[CommAgility introduced the AMC-V6L FPGA processing module. The AMC-V6L AdvancedMC module features the Xilinx Virtex-6 FPGA, 256Mbytes of 16-bit DDR3 SDRAM memory, 128Mbytes of Flash memory, dual Gigabit Ethernet, and two SFP+ sockets. The CommAgility AMC-V6L is sampling now. It is priced at less than $2,000 in 1K+ volume. The AMC-V6L FPGA processing module is [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/CommAgility-AMC-V6L.jpg" width="400" height="241" alt="CommAgility AMC-V6L FPGA processing module" border="0" /></p>
<p>CommAgility introduced the AMC-V6L FPGA processing module. The AMC-V6L AdvancedMC module features the Xilinx Virtex-6 FPGA, 256Mbytes of 16-bit DDR3 SDRAM memory, 128Mbytes of Flash memory, dual Gigabit Ethernet, and two SFP+ sockets. The CommAgility AMC-V6L is sampling now. It is priced at less than $2,000 in 1K+ volume. The AMC-V6L FPGA processing module is ideal for wireless, general-purpose FPGA acceleration and I/O processing applications.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-advancedmc/">CommAgility Introduces AMC-V6L FPGA Processing Module</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-advancedmc/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-advancedmc/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<title>U.S. DLA Qualifies Microsemi RTAX-S/SL FPGA for QML Class V</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/pZSRsrcCXhY/</link>
		<comments>http://fpgablog.com/posts/u-s-dla-qualifies-microsemi-rtax-ssl-fpga-for-qml-class-v/#comments</comments>
		<pubDate>Mon, 21 May 2012 15:47:47 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[FPGAs]]></category>
		<category><![CDATA[Microsemi]]></category>
		<category><![CDATA[MIL-PRF-38535]]></category>
		<category><![CDATA[military]]></category>
		<category><![CDATA[QML Class V]]></category>
		<category><![CDATA[Qualification]]></category>
		<category><![CDATA[Qualified Manufacturers List]]></category>
		<category><![CDATA[radiation-tolerant]]></category>
		<category><![CDATA[RTAX-S/SL]]></category>
		<category><![CDATA[Space]]></category>
		<category><![CDATA[U.S. DLA]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3876</guid>
		<description><![CDATA[Microsemi&#8217;s RTAX-S/SL field programmable gate arrays have received QML Class V qualification. The U.S. Defense Logistics Agency (DLA) qualified the FPGA as Qualified Manufacturers List Class V in accordance with military performance standard MIL-PRF-38535 space-level qualification requirements. QML Class V is the highest standard in the industry for space integrated circuits. Microsemi radiation-tolerant RTAX-S/SL FPGAs [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Microsemi-RTAX-FPGA.jpg" width="416" height="93" alt="Microsemi RTAX-S/SL field programmable gate arrays (FPGA)" border="0" /></p>
<p>Microsemi&#8217;s RTAX-S/SL field programmable gate arrays have received QML Class V qualification. The U.S. Defense Logistics Agency (DLA) qualified the FPGA as Qualified Manufacturers List Class V in accordance with military performance standard MIL-PRF-38535 space-level qualification requirements. QML Class V is the highest standard in the industry for space integrated circuits. Microsemi radiation-tolerant RTAX-S/SL FPGAs are ideal for space-flight systems. They feature high performance, low power, single-chip form factor and live-at-power-up operation.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/u-s-dla-qualifies-microsemi-rtax-ssl-fpga-for-qml-class-v/">U.S. DLA Qualifies Microsemi RTAX-S/SL FPGA for QML Class V</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/u-s-dla-qualifies-microsemi-rtax-ssl-fpga-for-qml-class-v/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/u-s-dla-qualifies-microsemi-rtax-ssl-fpga-for-qml-class-v/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<title>Lattice Released iCE40 Los Angeles mobileFPGA in Volume Production</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/xhmIzpIiewU/</link>
		<comments>http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/#comments</comments>
		<pubDate>Tue, 15 May 2012 17:19:14 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[HX1K]]></category>
		<category><![CDATA[HX4K]]></category>
		<category><![CDATA[HX640]]></category>
		<category><![CDATA[HX8K]]></category>
		<category><![CDATA[iCE40]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[Los Angeles]]></category>
		<category><![CDATA[LP1K]]></category>
		<category><![CDATA[LP4K]]></category>
		<category><![CDATA[LP640]]></category>
		<category><![CDATA[LP8K]]></category>
		<category><![CDATA[mobileFPGA]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3860</guid>
		<description><![CDATA[Eight devices in the Lattice Semiconductor iCE40 Los Angeles mobileFPGA family have been fully qualified and released into volume production. The low power LP640, LP1K, LP4K and LP8K devices, and the higher performance HX640, HX1K, HX4K and HX8K devices have been production released with 17 different device/package combinations. Read more Lattice Released iCE40 Los Angeles [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Lattice-iCE40.jpg" width="391" height="240" alt="Lattice Semiconductor's iCE40 Los Angeles mobileFPGA family" border="0" /></p>
<p>Eight devices in the Lattice Semiconductor iCE40 Los Angeles mobileFPGA family have been fully qualified and released into volume production. The low power LP640, LP1K, LP4K and LP8K devices, and the higher performance HX640, HX1K, HX4K and HX8K devices have been production released with 17 different device/package combinations.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/">Lattice Released iCE40 Los Angeles mobileFPGA in Volume Production</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/lp640-lp1k-lp4k-lp8k-hx640-hx1k-hx4k-hx8k/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<item>
		<title>HuMANDATA Introduces EDA-301 USB-FPGA Board</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/-aXPOahHSJM/</link>
		<comments>http://fpgablog.com/posts/altera-cyclone-fpga-ep4ce15f17c8n/#comments</comments>
		<pubDate>Mon, 14 May 2012 16:58:09 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA-based Product]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[board]]></category>
		<category><![CDATA[Cyclone IV]]></category>
		<category><![CDATA[EDA-301]]></category>
		<category><![CDATA[EP4CE15F17C8N]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[HuMANDATA]]></category>
		<category><![CDATA[PCB]]></category>
		<category><![CDATA[USB-FPGA]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3868</guid>
		<description><![CDATA[HuMANDATA introduced their EDA-301 USB-FPGA board. The EDA-301 features the Altera Cyclone IV E FPGA (EP4CE15F17C8N), 5.0 V external input or USB bus power, and 56 user I/O&#8217;s, which are divided into two I/O banks. The configurable PCB includes on-board oscillators, user switches and LEDs. It measures 53 mm x 54 mm, and can be [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/HuMANDATA-EDA-301-USB-FPGA.jpg" width="300" height="303" alt="HuMANDATA EDA-301 Altera Cyclone IV USB-FPGA board" border="0" /></p>
<p>HuMANDATA introduced their EDA-301 USB-FPGA board. The EDA-301 features the Altera Cyclone IV E FPGA (EP4CE15F17C8N), 5.0 V external input or USB bus power, and 56 user I/O&#8217;s, which are divided into two I/O banks. The configurable PCB includes on-board oscillators, user switches and LEDs. It measures 53 mm x 54 mm, and can be easily swapped for a different FPGA/CPLD board.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/altera-cyclone-fpga-ep4ce15f17c8n/">HuMANDATA Introduces EDA-301 USB-FPGA Board</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/altera-cyclone-fpga-ep4ce15f17c8n/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/altera-cyclone-fpga-ep4ce15f17c8n/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<item>
		<title>PLDA Unveils QuickTCP 10G TCP/IP Stack IP Core for Altera, Xilinx FPGA</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/dutnpC1gVmE/</link>
		<comments>http://fpgablog.com/posts/plda-quicktcp-ip/#comments</comments>
		<pubDate>Wed, 09 May 2012 16:12:20 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[IP Core]]></category>
		<category><![CDATA[10G]]></category>
		<category><![CDATA[altera]]></category>
		<category><![CDATA[AMBA AXI4]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[PLDA]]></category>
		<category><![CDATA[QuickTCP]]></category>
		<category><![CDATA[TCP/IP Stack]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3851</guid>
		<description><![CDATA[PLDA recently introduced their QuickTCP IP, which is a 10Gb TCP/IP Hardware stack IP core. It features an AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. PLDA QuickTCP is a 100% RTL designed IP. It is compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/PLDA-QuickTCP-IP.gif" width="468" height="254" alt="" border="0" /></p>
<p>PLDA recently introduced their QuickTCP IP, which is a 10Gb TCP/IP Hardware stack IP core. It features an AMBA AXI4 user interface that enables instant integration into either Altera-based or Xilinx-based FPGA designs. PLDA QuickTCP is a 100% RTL designed IP. It is compliant with the IEEE802.3 specification and supporting the ARP, IPv4, ICMP, and TCP protocols. The PLDA QuickTCP IP solution is available now from PLDA.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/plda-quicktcp-ip/">PLDA Unveils QuickTCP 10G TCP/IP Stack IP Core for Altera, Xilinx FPGA</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/plda-quicktcp-ip/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/plda-quicktcp-ip/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<item>
		<title>X-fest 2012 Technical Seminars Heading to Dallas, Minneapolis, Toronto, Vancouver</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/bPOVi7aXS-w/</link>
		<comments>http://fpgablog.com/posts/x-fest-2012/#comments</comments>
		<pubDate>Tue, 08 May 2012 15:20:52 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Event]]></category>
		<category><![CDATA[Avnet Electronics Marketing]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[North America]]></category>
		<category><![CDATA[Technical Seminars]]></category>
		<category><![CDATA[X-fest]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3843</guid>
		<description><![CDATA[Avnet Electronics Marketing is currently holding their X-fest technical seminar series in North America. X-fest 2012 features twelve technical courses based on Xilinx&#8217;s new Artix-7, Kintex-7 and Virtex-7 FPGAs, and Zynq-7000 Extensible Processing Platform (EPP) family. There are four remaining cities on the North American schedule: Dallas, Minneapolis, Toronto, and Vancouver. Read more X-fest 2012 [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/X-fest-2012.gif" width="468" height="137" alt="X-fest 2012 ~ Avnet Electronics Marketing" border="0" /></p>
<p>Avnet Electronics Marketing is currently holding their <a href="http://fpgablog.com/posts/avnet-xilinx-xfest-2012/">X-fest</a> technical seminar series in North America. X-fest 2012 features twelve technical courses based on Xilinx&#8217;s new Artix-7, Kintex-7 and Virtex-7 FPGAs, and Zynq-7000 Extensible Processing Platform (EPP) family. There are four remaining cities on the North American schedule: Dallas, Minneapolis, Toronto, and Vancouver.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/x-fest-2012/">X-fest 2012 Technical Seminars Heading to Dallas, Minneapolis, Toronto, Vancouver</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/x-fest-2012/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/x-fest-2012/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<title>Lattice Introduces New Power Management Architecture, Releases Two App Notes</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/9-Gjuqoag8A/</link>
		<comments>http://fpgablog.com/posts/star-topology-power-management/#comments</comments>
		<pubDate>Mon, 07 May 2012 16:19:36 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[App Notes]]></category>
		<category><![CDATA[Architecture]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[Platform Manager]]></category>
		<category><![CDATA[Power Management]]></category>
		<category><![CDATA[Power Supply]]></category>
		<category><![CDATA[star topology]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3854</guid>
		<description><![CDATA[Lattice Semiconductor introduced a new power management architecture. The new in-system upgradable, star topology power management architecture can be used across a wide range of circuit boards requiring over 12 power supply rails. In addition, Lattice also released two new application notes for their Platform Manager devices that will enable engineers to quickly adopt the [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Lattice-Power-Management.gif" width="468" height="201" alt="Platform Manager Provides Centralized Sequencing and Monitoring of up to 36 Power Supplies" border="0" /></p>
<p>Lattice Semiconductor introduced a new power management architecture. The new in-system upgradable, star topology power management architecture can be used across a wide range of circuit boards requiring over 12 power supply rails. In addition, Lattice also released two new application notes for their Platform Manager devices that will enable engineers to quickly adopt the new architecture.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/star-topology-power-management/">Lattice Introduces New Power Management Architecture, Releases Two App Notes</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/star-topology-power-management/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/star-topology-power-management/" height="61" width="51" /></a></p>
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		<title>Lattice Semiconductor Packs MachXO2 PLD into 32 QFN Package</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/MHpxG4kjJmk/</link>
		<comments>http://fpgablog.com/posts/machxo2-256-qfn/#comments</comments>
		<pubDate>Tue, 01 May 2012 15:52:23 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[FPGA]]></category>
		<category><![CDATA[32 QFN]]></category>
		<category><![CDATA[Lattice Semiconductor]]></category>
		<category><![CDATA[MachXO2]]></category>
		<category><![CDATA[PLD]]></category>
		<category><![CDATA[Programmable Logic Devices]]></category>
		<category><![CDATA[Quad Flatpack No-leads]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3838</guid>
		<description><![CDATA[Lattice Semiconductor&#8217;s MachXO2 family of programmable logic devices (PLD) is available in a new 32 QFN (Quad Flatpack No-leads) package. Engineering samples of the MachXO2-256 in the 32 QFN package are available now. Production-qualified versions will be available in the third quarter of this year. MachXO2 PLDs with 256 LUTs are priced at $0.55 in [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Lattice-MachXO2.jpg" width="250" height="250" alt="Lattice Semiconductor MachXO2 Programmable Logic Devices" border="0" /></p>
<p>Lattice Semiconductor&#8217;s MachXO2 family of programmable logic devices (PLD) is available in a new 32 QFN (Quad Flatpack No-leads) package. Engineering samples of the MachXO2-256 in the 32 QFN package are available now. Production-qualified versions will be available in the third quarter of this year. MachXO2 PLDs with 256 LUTs are priced at $0.55 in volumes of 250K units. The programmable devices are supported in Lattice Diamond design software version 1.4.2.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/machxo2-256-qfn/">Lattice Semiconductor Packs MachXO2 PLD into 32 QFN Package</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/machxo2-256-qfn/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/machxo2-256-qfn/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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		<title>Maxim 1-Wire Security Reference Design Protects Spartan-6 FPGA-Based Designs</title>
		<link>http://feedproxy.google.com/~r/fpgablog/~3/_WBvLphXYFs/</link>
		<comments>http://fpgablog.com/posts/xilinx-ds28e01-100/#comments</comments>
		<pubDate>Mon, 30 Apr 2012 15:36:15 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Reference Design]]></category>
		<category><![CDATA[1-Wire]]></category>
		<category><![CDATA[Control]]></category>
		<category><![CDATA[Designs]]></category>
		<category><![CDATA[DS28E01-100]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[FPGA IP]]></category>
		<category><![CDATA[Licensing]]></category>
		<category><![CDATA[Maxim Integrated Products]]></category>
		<category><![CDATA[memory device]]></category>
		<category><![CDATA[safeguards]]></category>
		<category><![CDATA[Secure]]></category>
		<category><![CDATA[Security]]></category>
		<category><![CDATA[Spartan-6]]></category>
		<category><![CDATA[Xilinx]]></category>

		<guid isPermaLink="false">http://fpgablog.com/?p=3833</guid>
		<description><![CDATA[Maxim Integrated Products introduced a reference design that will protect Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The reference design features security software (from Maxim or Xilinx) and the Maxim DS28E01-100 1-Wire secure memory device. Engineers can easily add a level of design security to products with the Maxim DS28E01-100 1-Wire secure memory device. In the [...]]]></description>
			<content:encoded><![CDATA[<p align="center"><img src="http://fpgablog.com/primages/2012/Maxim-DS28E01-100-FPGA.gif" width="468" height="207" alt="Maxim 1-Wire security reference design" border="0" /></p>
<p>Maxim Integrated Products introduced a reference design that will protect Xilinx Spartan-6 field-programmable gate arrays (FPGAs). The reference design features security software (from Maxim or Xilinx) and the Maxim DS28E01-100 1-Wire secure memory device. Engineers can easily add a level of design security to products with the Maxim DS28E01-100 1-Wire secure memory device. In the future, the reference design will support Artix-7, Kintex-7, Virtex-7 and the Zynq-7000 FPGA devices.</p>
<p><p>Read more <a href="http://fpgablog.com/posts/xilinx-ds28e01-100/">Maxim 1-Wire Security Reference Design Protects Spartan-6 FPGA-Based Designs</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://fpgablog.com/posts/xilinx-ds28e01-100/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://fpgablog.com/posts/xilinx-ds28e01-100/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/fpgablog">Twitter @fpgablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : FPGA Blog is a trademark of Online Destiny Ltd</p>
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