EDA Blog

Tanner Analog FastSPICE Features Berkeley Design Automation AFS

Ken Cheung — Fri, 25 May 2012 15:57:48 +0000

Tanner EDA introduced Tanner Analog FastSPICE (T-AFS), which adds Berkeley Design Automation Analog FastSPICE Platform to Tanner EDA’s full-flow HiPer Silicon design suite. With the availability of Analog FastSPICE as an add-on to Tanner EDA’s analog and mixed-signal design tools, RF designers can realize the benefits of Tanner EDA’s full-flow analog design suite. Analog FastSPICE enables verification of very complex analog/ RF circuits with nanometer SPICE-accurate results.

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Carbon Design Systems and Cadence Design Systems Team on Performance Analysis Kit

Ken Cheung — Thu, 24 May 2012 04:01:44 +0000

Carbon Design Systems and Cadence Design Systems announced the availability of a Carbon Performance Analysis Kit. The CPAK accelerates the intellectual property (IP) benchmark process. The Carbon/Cadence CPAK is available now from Carbon’s IP Exchange web portal. Ported CoreMark benchmarking software is available from coremark.org.

Corelis Introduces ScanExpress Boundary-Scan Tool Suite v7.7

Ken Cheung — Wed, 23 May 2012 15:46:31 +0000

Corelis launched version 7.7 of their ScanExpress Boundary-Scan Tool Suite. The latest version of the tool suite features improved constraints handling, support for multi-core devices, and new JTAG Embedded Test support for additional Freescale and Texas Instruments processors. ScanExpress Boundary-Scan Tool Suite, version 7.7 is available now to customers with a valid maintenance contract.

Texas Instruments Introduces ULP Advisor Software Code Analysis Tool

Ken Cheung — Tue, 22 May 2012 17:30:48 +0000

Texas Instruments introduced the ULP (Ultra-Low Power) Advisor software code analysis tool. The TI ULP Advisor tool provides a static code analyzer that flags software code and offers ultra-low-power tips and tricks to help developers understand where to improve code, line by line. This results in milliamps and nanoamps saved in designs for ultimate low-power performance. ULP Advisor software is available now. It is included in the latest install of Code Composer Studio IDE version 5.2.

HiPer Simulation A/MS Features Tools from Tanner EDA, Aldec

Ken Cheung — Mon, 21 May 2012 15:36:13 +0000

Tanner EDA and Aldec teamed together on HiPer Simulation A/MS, which is an integrated co-simulation solution for analog and mixed-signal (A/MS) design. HiPer Simulation A/MS includes Tanner EDA’s T-Spice analog design capture and simulation tool, and Aldec’s Riviera-PRO mixed language digital simulator. The integrated solution helps both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform. HiPer Simulation A/MS is available on both Windows and Linux.

EVE Introduces e-zTest 10GbE Validation Platform for ZeBu

Ken Cheung — Thu, 17 May 2012 16:33:41 +0000

EVE introduced e-zTest 10GbE, which is a 10-Gigabit Ethernet validation platform for their ZeBu (Zero Bugs) family of system-on-chip (SoC) hardware-assisted verification platforms. The e-zTest 10GbE software is a transaction-based environment for high-speed validation of 10GbE functions in network routers, switches and controllers, and SoC application specific integrated circuits (ASICs) containing 10GbE ports.

Carbon Design Systems Launches Performance Analysis Kits

Ken Cheung — Wed, 16 May 2012 16:31:51 +0000

Carbon Design Systems is accelerating the analysis, optimization and verification of system-on-chip (SoC) performance with their new Carbon Performance Analysis Kits (CPAK). The CPAK family for ARM Cortex processors includes reference hardware and software designs along with analysis and debug software for the Cortex-A9, Cortex-A15 and Cortex-A7 cores, and the ARM big.LITTLE subsystem. The CPAK Family for ARM Cortex A-Series Processors will be available in bare metal and Linux configurations in this quarter. Android configurations will be available in the second half of this year.

Cadence Adds In-Circuit Acceleration to System Development Suite, Expands VIP Catalog

Ken Cheung — Tue, 15 May 2012 17:11:15 +0000

Cadence Design Systems made two announcements today. First, the company developed new in-circuit acceleration based on the Incisive and Palladium XP platforms for their System Development Suite. Cadence’s second announcement involved extensions to the Verification IP Catalog for acceleration and emulation that enable engineers to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.

STMicroelectronics Introduces STM3220G-JAVA Starter Kit

Ken Cheung — Mon, 14 May 2012 16:12:30 +0000

STMicroelectronics introduced the STM3220G-JAVA Starter Kit. The STM3220G-JAVA kit is a complete platform for evaluating the development of embedded applications in Java for the STM32 F2 series microcontrollers. The new Java tool includes an evaluation version of IS2T’s MicroEJ Software Development Kit (SDK) and the STM32F2 series microcontroller evaluation board providing everything engineers need to start their projects. The STM3220G-JAVA Starter Kit is available now. It is priced at $349.

Sigrity Launches XcitePI IO Interconnect Model Extraction

Ken Cheung — Mon, 14 May 2012 06:59:31 +0000

Sigrity launched their XcitePI IO Interconnect Model Extraction and Assessment software. The tool provides accurate system-level analysis of high-speed channels and buses by generating precise chip IO power/ground and signal interconnect models. XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms. Prices start at $108,000 for a 3-year license. The new tool is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement.