EDA Blog

Cadence Design Systems Seeks Papers for MemCon 2013

Ken Cheung — Fri, 24 May 2013 12:49:04 +0000

Cadence Design Systems has issued a call for papers to be presented at MemCon 2013. Cadence is seeking presentations and papers on topics that illustrate users’ knowledge and expertise in memory design and architecture. The deadline for paper abstract submission is May 30, 2013. The MemCon conference showcases the thought leaders driving advances in memory technology. The event will take place August 6, 2013 at the Santa Clara Convention Center.

Twitter @edablog : : Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek : : Dad Blog
© 2013 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd

Texas Instruments Unveils OMAP5432 Processor-based Evaluation Module

Ken Cheung — Wed, 22 May 2013 12:46:04 +0000

Texas Instruments introduced the OMAP5432 processor-based evaluation module. The TI OMAP5432 EVM is a cost-effective tool to prototype software, evaluate applications and benchmark designs. It is available now for $329. The OMAP5432 EVM is ideal for human machine interface (HMI), portable data terminals (PDT), digital signage and medical monitoring end equipment.

Cadence Tempus Timing Signoff Solution Speeds Timing Closure

Ken Cheung — Tue, 21 May 2013 12:50:34 +0000

Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.

Synopsys IC Compiler 2013.03 Speeds Design Closure

Ken Cheung — Fri, 17 May 2013 12:43:49 +0000

Synopsys recently released a new version of their IC Compiler software. Release 2013.03 features innovations to speed design as well as enables the latest process nodes. IC Compiler 2013.03 includes advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.

Mentor Graphics Introduces Capital Harness TVM Tool

Ken Cheung — Wed, 15 May 2013 12:52:37 +0000

Mentor Graphics recently introduced their Capital Harness TVM tool. The software automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models. Capital Harness TVM helps harness manufacturers win business profitably, and is also a platform for other activities such as value engineering and process optimization.

Data Translation Introduces QuickDAQ 2013 for Data Acquisition

Ken Cheung — Mon, 13 May 2013 12:54:33 +0000

Data Translation introduced QuickDAQ 2013. The new software application supports all of Data Translation data acquisition modules. QuickDAQ 2013 has been designed to accommodate a wide variety of sensor types and various throughput speeds for our many OEM’s and end-users. Engineers can use one application software package for many measurement needs with no software changes. QuickDAQ 2013 is available for free. FFT Analysis and Advanced FFT Analysis add-ons are offered to build onto the capabilities of the base package.

Cadence Design Systems Debuts Incisive Enterprise Simulator v13.1

Ken Cheung — Wed, 08 May 2013 12:51:00 +0000

Cadence Design Systems released version 13.1 of the Incisive Enterprise Simulator. The latest release of the software tool improves low-power verification productivity of complex SoCs by 30%. Cadence Incisive Enterprise Simulator v13.1 features new capabilities that ease the challenge of verifying all of today’s power-aware designs.

Free Boundary Scan Workshop at Manufacturing Technology Centre

Ken Cheung — Tue, 07 May 2013 12:58:48 +0000

XJTAG will hold a free boundary scan training workshop at the UK’s Manufacturing Technology Centre (MTC). The workshop will provide an introduction to boundary scan and to show how the debug, test and programming process can be used throughout the product life cycle. The XJTAG workshop will take place Wednesday, June 12, 2013 in Coventry.

Download ADLINK AD-Logger and DAQBench for Free

Ken Cheung — Fri, 03 May 2013 12:43:58 +0000

Thanks to ADLINK Technology, engineers can download AD-Logger and DAQBench for free. AD-Logger is a ready-to-run data capture application. DAQBench provides ActiveX controls used for creating professional instrumentation applications using ActiveX development environments. AD-Logger and DAQBench are compatible with ADLINK’s full range of data acquisition modules and digitizers. Both tools are compatible with 32-bit Windows XP/7/8.

Synopsys Debuts Virtualizer Development Kit for Freescale Qorivva Microcontroller

Ken Cheung — Thu, 02 May 2013 12:46:59 +0000

Synopsys introduced the Virtualizer Development Kit (VDK) for Freescale Semiconductor’s Qorivva microcontroller family. The Synopsys VDK accelerates the development of automotive control applications in powertrain/hybrid, chassis/safety and body electronic control units (ECUs). Synopsys’ automotive VDKs help OEMs and tier-one suppliers to enhance their embedded software development processes by starting earlier, improving productivity and enabling more and better testing in support of safety standards such as ISO 26262. The VDK for Freescale Qorivva MCUs is available now.