Verification(Verification of System and Software) Blogs

USB4 Interoperability with Thunderbolt™︎ 3 (TBT3) Systems

Anshul Shah — Mon, 26 Sep 2022 14:43:00 GMT

One of the key goals for USB4 is to retain compatibility with the existing ecosystem of USB3.2, USB 2.0 and Thunderbolt products, and the resulting connection scales to the best mutual capability of the devices being connected. USB4 is designed to work with older versions of USB and Thunderbolt . USB4 Fabric support high throughput interconnects of 10 Gbps (for Gen 2) and 20 Gbps (for Gen 3) and supports Thunderbolt 3-compatible rates of 10.3125 Gbps (for Gen 2) and 20.625 Gbps (for Gen 3). It becomes very important to verify the Thunderbolt backward compatibility with the designs. Though the support of USB4 Interoperability with Thunderbolt 3 (TBT3) is optional in USB4 host or USB4 peripheral device and required USB4 Hub and USB4 Based Dock but it is very essential to work in the existing ecosystem.

Few Main features of USB4 Interoperability with Thunderbolt 3 (TBT3) Systems

Support for Bi-Directional Pins & Retimers: TBT3 Active Cables can contain two bidirectional Re-timers which have the capability to send AT Responses on its RX channel. Router connected directly to such Retimer needs to support A Router that is connected directly to a bidirectional Re-timer shall support reception of Transactions on both TX and RX channels.

Bounce Mechanism: This feature is used by Router to access the Register Space of a Cable Re-timer that can only be accessed by its Link Partner.
Asymmetric Negotiation: The Router which connects with Cable Retimers needs to follow Asymmetric TxFFE in Phase 5 of Lane Initialization.
USB4 Link Transitions: In TBT3 mode, the configuration of two independent Single Lane Links can be used non-transient state or Single Lane Link just using the Lane1 Adapter.

Cadence has a mature USB4 Verification IP solution that can help in the verification of USB4 designs with TBT3. Cadence has taken an active part in the Cairo group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members. If you plan to have a USB4-compatible design, you can reduce the risk of adopting new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team, for more details.

Moving Beyond EDA: The Intelligent System Design Strategy

Vinod Khera — Thu, 22 Sep 2022 09:20:00 GMT

The rising customer expectations, intermingling fields and high performance needs can be satisfied with the system based design. An intelligent Systems Design strategy can offer a quicker route to an optimum design and helps to increase designers' productivity and analyzes efficiency by providing the ability to explore the entire design space. Cadence Intelligent System Strategy enables a system design revolution and reduces project schedules with optimized continuous integration.(read more)

TSN-PTP: A Real-Time Network Clock Synchronizing Protocol

Vedansh Seth — Mon, 12 Sep 2022 06:45:00 GMT

In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication process smooth, then the local clocks of these nodes must be synchronized.

The problem with this synchronization is that we have the clock running in the Manager as well. If we send the value of the Manager clock to the Peripheral, the synchronization doesn’t happen as we have a propagation delay of the messages, along with the propagation delay of the electronic circuits of Manager and the Peripheral.

The cherry on the cake is that these electronic circuit propagation delays are not random and remain constant, so we can add a time offset to it to match the clock. To tackle this challenge, IEEE has come up with a protocol named “Precision Timing Protocol.”

Operation of PTP:

To synchronize the clocks, a Sync message is sent by the Manager to the Peripheral, which then timestamps the receiving time of the same. Following this, a ‘Follow up’ message is issued by the Manager stating the timestamp at which the Sync message was sent.

The Peripheral then finds the difference between the two values and adds this to its current time. After this, the time difference between the Manager and the Peripheral narrows down to only the propagation delay of the messages.

To overcome this, the Peripheral issues a ‘Delay Request’ to the Manager, and the Manager, in turn, issues a ‘Delay Response.’ Both these messages have the timestamp of when they were issued. The time at which they are received is then noted. Since two messages are sent, one from the Peripheral and the other from the Manager, there are two propagation delays. Then half of this value is our propagation delay.

The Peripheral then adds this propagation delay to its clock, and hence the clock gets synchronized.

Advantages of PTP:

It provides accurate time stamping.
It is a well-known clock synchronization protocol.
It provides intensified security inside the premises.
It provides the possibility of setting coordinated actions and synchronized communication.

There are various versions of PTP that have been developed over time, namely PTPv1, PTPv2, PTPv2_1, and the latest PTP-AS.

Cadence Verification IP for Ethernet is available to support the newer version of PTP, allowing simulation of the device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time. 

Flash Toggle NAND 4.0 in a Nutshell

GauravJ — Wed, 31 Aug 2022 14:45:00 GMT

NAND Flash memory is now a widely accepted non-volatile memory in many application areas for data storage such as digital cameras, USB drive, SSD and smartphones. One form of NAND flash memory, Toggle NAND, was introduced to transmit high-speed data asynchronously thus consuming less power and increasing the density of the NAND flash device.

The initial Toggle NAND versions had memory arranged in terms of SLC (Single Level Cell) or MLC (Multi Level Cell) mode that was considered as a 2D scalar stack and their frequency of operation was also less. The ever-growing demand of high memory capacity and high throughput required further research in the areas like the shrinking size of cell, performance to fill-in these gaps.

Some of these new requirements were incorporated, leading to newer versions of Toggle NAND, namely 3.0 and 4.0, with a re-arrangement of the internal memory developing a 3D layer of memory. With such structures, higher capacity of the memory was possible, but performance was the primary challenge as the latency of the write/read of memory quadrupled with the same frequency.

The key to improving the performance and run the device at very high speed in low power mode was to enhance the frequency of operation for faster read/writes to the memory and reduce the voltage levels.

But with every technology advancement comes some other problems, the next being the data sampling at that high frequency that can cause setup/hold time issues. To overcome these concerns, different types of trainings on the signal interface were made mandatory that shall assist in proper sampling of the data. Few other features for improving the integrity of the signals were added.

The current set of commands were applicable to access the SLC and MLC memory modes but with the 3D layering, these commands were lacking access to the entire set of TLC (Triple Level Cell) and QLC (Quad Level Cell) memory modes. Thus, more commands were required to make sure that the 3D layering was fully written/read.

Main features of Toggle NAND 4.0 :

High Density of Memory
High Frequency of operation, greater than 800 MHz
Data Trainings

Cadence Verification IP for Flash Toggle NAND 4.0 is available to support the newer version of Flash Toggle NAND 4.0, allowing to simulate the memory device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time.

Gaurav

Achieve 80% Less Late-Stage RTL Changes and Early RTL Bug Detection

Vinod Khera — Tue, 16 Aug 2022 05:00:00 GMT

It has become challenging to ensure that the designs are complete, correct, and adhere to necessary coding rules before handing them off for RTL verification and implementation. RTL Designer Signoff Solution from Cadence helps the user identify RTL bugs at a very early development stage, saving a lot of effort and cost for the design and verification team. Our reputed customers have confirmed that using RTL signoff for their design IP helped save up to 4 weeks and reduce the late-stage RTL changes by up to 80%.(read more)

JEDEC UFS 4.0 for Highest Flash Performance

Yeshavanth BN — Thu, 11 Aug 2022 12:30:00 GMT

Speed increase requirements keep on flowing by in all the domains surrounding us. The same applies to memory storage too. Earlier mobile devices used eMMC based flash storage, which was a significantly slower technology. With increased SoC processing speed, pairing it with slow eMMC storage was becoming a bottleneck. That is when modern storage technology Universal Flash Storage (UFS) started to gain popularity.

UFS is a simple and high-performance mass storage device with a serial interface. It is primarily used in mobile systems between host processing and mass storage memory devices. Another important reason for the usage of UFS in mobile systems like smartphones and tablets is minimum power consumption.

To achieve the highest performance and most power-efficient data transport, JEDEC UFS works in collaboration with industry-leading specifications from the MIPI® Alliance to form its Interconnect Layer. MIPI UniPro is used as a transport layer, and MIPI MPHY is used as a physical layer with the serial DpDn interface.

UFS 4.0 specification is the latest specification from JEDEC, which leverages UniPro 2.0 and MPHY 5.0 specification standards to achieve the following major improvements:

Enables up to 4200 Mbps read/write traffic with MPHY 5.0, allowing 23.29 Gbps data rate.
High Speed Link Startup, along with Out of Order Data Transfer and BARRIER Command, were introduced to improve system latencies.
Data security is enhanced with Advanced RPMB. Advance RPMB also uses the EHS field of the header, which reduces the number of commands required compared to normal RPMB, increasing the bandwidth.
Enhanced Device Error History was introduced to ease system integration.
File Based Optimization (FBO) was introduced for performance enhancement.

Along with many major enhancements, UFS 4.0 also maintains backward compatibility with UFS 3.0 and UFS 3.1.

JEDEC has just announced the UFS 4.0 specification release, quoting Cadence support as a constant contributor in the JEDEC UFS Task Group, actively participating in these specifications development.

With the availability of the Cadence Verification IP for JEDEC UFS 4.0, MIPI MPHY 5.0 and MIPI UniPro 2.0, early adopters can start working with the provisional specification immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. 

More information on Cadence VIP is available at the Cadence VIP Website.

Yeshavanth B N

Coalesce Xcelium Apps to Maximize Performance by 10X and Catch More Bugs

Anika Sunda — Tue, 02 Aug 2022 04:30:00 GMT

Xcelium Simulator has been in the industry for years and is the leading high-performance simulation platform. As designs are getting more and more complex and verification is taking longer than ever, the need of the hour is plug-and-play apps that ar...(read more)

Stay Ahead of Competition with Real-Time Cross-Team Collaborations

Vinod Khera — Tue, 26 Jul 2022 05:21:00 GMT

To stay ahead in competition in chip design real-time collaborations ensure traceability, speedy innovations at reduced the cost.(read more)

Xcelium PowerPlayBack App and Dynamic Power Analysis

Vinod Khera — Mon, 18 Jul 2022 10:00:00 GMT

Learn how Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms for glitch-accurate power estimation of multi-billion gate SoC designs.(read more)

Jasper C2RTL App for Datapath Verification

Vinod Khera — Wed, 13 Jul 2022 02:31:00 GMT

Ensuring that the RTL designs correctly implement the C++ algorithmic intent in every circumstance is difficult to achieve with conventional verification. Learn more how Jasper C2RTL App helps to perform equivalence checking with 100x performance improvement(read more)

Cadence in Collaboration with Arm Ensures the Software Just Works

Vinod Khera — Tue, 12 Jul 2022 01:02:00 GMT

The increase in compute and data-intensive applications and the need for lower power consumption have resulted in a rapidly growing number of Arm-based devices in various market segments; this requires fast time to market (TTM) and support for off-t...(read more)

Automotive Revolution with Ethernet Base-T1

Krunalkumar — Thu, 07 Jul 2022 14:11:00 GMT

The automotive industry revolutionized the definition of a vehicle in terms of safety, comfort, enhanced autonomy, and internet connectivity. With this trend, the automotive industry rapidly adopted automotive Ethernet such as 10Base-T1, 100Base-T1, and in some cases, 1000Base-T1.

Faster Speed (than CAN-FD), Scalability, embedded security protocols (like MacSec), cost and energy efficiency, and simple yet redundant network made Ethernet an obvious choice over CAN(FD) and FlexRay. 

Ethernet 10Base-T1

10BASE-T1S is defined under IEEE with 802.3cg. The S in 10BASE-T1S stands for a short distance. 10BASE-T1S uses a multidrop topology, where each node connects to a single cable. Multidrop topology eliminates the need for switches and, as a result, fewer cables/less cost. The primary goal of 10BASE-T1S is a deterministic transmission on a collision-free multidrop network. 10BASE-T1S cables use a pair of twisted wires. As per IEEE, at least eight nodes can connect to each, but more connections are feasible.   

The Physical Layer Collision Avoidance [PLCA] protocol ensures that it uses the entire 10 Mbps bandwidth. In 10BaseTs, Reconciliation Sublayer provides optional Physical Layer Collision Avoidance (PLCA) capabilities among participating stations. Using PLCA-enabled Physical Layers in CSMA/CD half-duplex shared-medium networks can provide enhanced bandwidth and improved access latency under heavily loaded traffic conditions. The working principle of PLCA is that transmit opportunities on a mixing segment are granted in sequence based on a node ID unique to the local collision domain (set by the management entity). 10BASE-T1S also supports an arbitration scheme that guarantees consistent node access to the media within a predefined time.

The 10BASE-T1S PHY is intended to cover the low-speed/low-cost applications in the industrial and automotive environment. A large number of pins (16) required by the MII interface is one of the significant cost factors that must be addressed to fulfill this objective. The 10BASE-T1S "Transceiver" solution is suited for embedded systems where the digital portion of the PHY is fully integrated, e.g., into an MCU or an Ethernet switch core, leaving only the analog portion (the transceiver) into a separate IC.

Ethernet 100Base-T1/1000Base-T1

100Base-T1 and 1000Base-T1 can be used for audio/video information. With Higher bandwidth capacity, 100Base-T1/ 1000Base-T1 paired with AVB (Audio video bridging) can be used for car infotainment systems. 100Base-T1/1000Base-T1 paired with time-sensitive networking [TSN] protocol can be used to fulfill the automotive industry's mission-critical, time-sensitive, and deterministic latency needs.

PTP Over MacSec

With today's automotive network, all the Electronic Control Units connected require timing accuracy and network synchronization, Precision Time Protocol (PTP), defined in IEEE 1588, provides synchronized clocks throughout a network.  While maintaining the timing accuracy for mission-critical applications, protecting the vehicle network from vulnerable threats is mandatory, and PTP over MacSec provides the consolidated solution.

With the availability of the Cadence Verification IP for 10/100/1000BaseT1 and TSN, adopters can start working with these specifications immediately, ensuring compliance with the standard and achieving the fastest path to IP and SoC verification closure. The 10/100/1000GBaseT1 and TSN provide a full-stack solution, including support to the PHY, MAC, and TSN layers with a comprehensive coverage model and protocol checkers. Ethernet BaseT1 and TSN VIP covers all features required for complete coverage verification closure. More details are available in the Ethernet Verification IP portfolio.

Krunal

Data Integrity for JEDEC DRAM Memories

Shyam Sharma — Wed, 06 Jul 2022 16:58:00 GMT

With the DRAM fabrication advancing from 1x to 1y to 1z and further to 1a, 1b and 1c nodes along with the DRAM device speeds going up to 8533 for Lpddr5/8800 for DDR5, Data integrity is becoming a really important issue that the OEMs and other users have to consider as part of the system that relies on the correctness of data being stored in the DRAMs for system to work as designed.

It’s a complicated problem that requires multiple ways to deal with it.

Traditionally one of the main approaches to deal with data errors is to rely on the ECC. ECC requires additional memory storage in which the ECC codes will calculated and stored at the time of memory write to DRAM. These codes will be read back along with the memory data during to the reads and checked against the data to make sure that there are no errors. Typical ECC schemes use Hamming code that provide for single bit error correction and double bit error detection per burst. Also, while several of previous generation of DRAM required Host to keep aside system memory for ECC storage latest DRAMs like Lpddr5 and DDR5 support on die ECC as part of the normal DRAM function that can be enabled using mode registers. DDR5 further requires Host to run through an ECC Error Check and Scrub (ECS) cycle on an average every tECSint time (Average Periodic ECS Interval) to prevent data errors.

Not meeting the DRAM Refresh requirement is a major reason that can lead to loss of data. This could be challenging as the PVT variation can cause the refresh requirement to change over time. Putting the DRAM in Self Refresh mode can help off-loading Refresh tracking responsibilities to DRAM but may prevent Host to do other scheduling optimizations and should be carefully considered.

Some of the other things that can affect the DRAM data are

Row hammer where same or adjacent rows are activated again and again leading to loss or changing of data contents in the rows that has not being addressed. Latest DRAMs like Lpddr5/Ddr5 support Refresh Management (including DRFM and ARFM) that allows the Host to compensate for these problems by issuing dedicated RFM commands helping DRAMs deals with potential Data loss issues arising out of Row hammer attacks.
Device temperature is another important factor that the Host needs to be aware of and if the application requires DRAM to operate at elevated temperature. The user needs to check with DRAM Vendor on the temperature range that DRAM can still operate. Data integrity at thresholds greater than certain temperature is not assured regardless of refresh rate unless DRAM is manufactured to withstand that.
Loss of power to DRAM will cause DRAM to lose all its contents. If this is a real concern for the system designer, they should consider using NVDIMM-N devices which has an onchip controller and a power source which is just enough to allow the DRAM contents to be copied into a backup non-volatile memory before power is lost. When the power is stored back, the stored memory contents in the non-volatile memory will be written back to the DRAM and system can continue to operate as it was before the power loss event occurred.

For transmissions and manufacturing errors DRAMs support additional features like CRC, DFE, Pre-Emphasis and PPR which will be covered in the next blog.

Cadence MMAV VIPs for DDR5/DDR5 DIMM and LPDDR5 are compressive VIP solutions and supports all of the above-listed Data integrity features including support for ECC error injection and SBE correction/DBE detection to assist with the verification challenges dealing with data integrity issues.

More information on Cadence DDR5/LPDDR5 VIP is available at Cadence VIP Memory Models Website.

Shyam

5X “Time Warp” in Your Next Verification Cycle Using Xcelium Machine Learning

Anika Sunda — Wed, 22 Jun 2022 05:19:00 GMT

Artificial intelligence (AI) is everywhere. Machine learning (ML) and its associated inference abilities promise to revolutionize everything from driving your car to making your breakfast. Verification is never truly complete; it is over when you run...(read more)

Quest for Bugs – The Constrained-Random Predicament

Anika Sunda — Tue, 14 Jun 2022 14:54:00 GMT

Optimize Regression Suite, Accelerate Coverage Closure, and Increase hit count of rare bins using Xcelium Machine Learning. It is easy to use and has no learning curve for existing Xcelium customers. Xcelium Machine Learning Technology helps you discover hidden bugs when used early in your design verification cycle.(read more)