Cadence IC Packaging and SiP Design Blogs

Help Shape Future Releases of APD and SiP – Provide Your Feedback on Early Adopter Features!

Jeff Gallagher — Mon, 20 May 2013 21:48:00 GMT

With every new release of the Cadence IC Package design software, many new features requested by designers are added. In other cases, interesting concepts that R&D engineers think up also make it into this list, so that real designers can try them...(read more)

Turn GDSII Data into Intelligent Die Components with 16.6 Cadence APD/SiP Tools

Jeff Gallagher — Fri, 03 May 2013 16:34:00 GMT

As we all know, there are many file formats in which an IC package designer will receive a die from the IC designer. Ideally, it will be in a format such as die text or a co-design die abstract, as these files contain both logical and physical information...(read more)

Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP

Jeff Gallagher — Thu, 11 Apr 2013 16:03:00 GMT

The level of ease and efficiency you experience in selecting the items needed for modifying in your substrate can mean the difference between a great design experience and an exercise in frustration and futility. With the 16.6 release, Cadence IC Packaging...(read more)

Reduce Flip-Chip Design Time with Cadence Advanced Package Router (APR) for 16.6 APD and SiP Layout

Jeff Gallagher — Thu, 21 Mar 2013 14:38:00 GMT

Perhaps the most time-consuming aspect to designing the package substrate for a large, high pin count flip-chip comes in the form of package routing. Escaping from underneath the flip-chip die itself, routing through multiple substrate layers, and finally...(read more)

Remove Die Stack Layers from NC Drill Outputs using Cadence 16.6 SiP and APD IC Packaging Tools

Jeff Gallagher — Fri, 01 Mar 2013 16:08:00 GMT

As we continue with our series on improvements to the manufacturing and documentation outputs in the Cadence 16.6 IC Packaging layout tools, our focus this week is on NC Drill outputs. For as long as NC Drill data has been a part of the IC Packaging tools...(read more)

Ease Your IC Packaging Documentation and Manufacturing Exports for Stacked Dies in 16.6 SiP

Jeff Gallagher — Wed, 06 Feb 2013 21:43:00 GMT

Following our last posting concerning intelligent documentation text, this week we look at the a new ability in 16.6 for managing the die outlines in a manner which allows simplified generation of documentation and manufacturing outputs. In a complex...(read more)

Make Your IC Packaging Documentation Labels Smarter with 16.6 SiP and APD

Jeff Gallagher — Thu, 17 Jan 2013 16:31:00 GMT

Documentation is key when completing any IC package substrate design. Without it, any number of problems can arise - from incorrect bond mapping between die pads and bond fingers to die being stacked in the wrong order. Ensuring that your documentation...(read more)

Be Among the First IC Packagers to Experience the New GDS-II Stream Interface in 16.6

Jeff Gallagher — Thu, 20 Dec 2012 21:06:00 GMT

For most IC package designers, the GDSII format is a part of daily life. You may receive stream data from your IC designers or partners which you must convert into die components for placement on a package substrate, or perhaps you export stream data...(read more)

Leverage System Planning to Maximize Performance of Silicon Interposer

TeamAllegro — Thu, 06 Dec 2012 17:23:00 GMT

Recently, an article was published in Chip Scale Review by Cadence product manager Kevin Rinebold talking about maximizing the value of silicon interposer technology using system planning (see page 30). Today’s semiconductor technologies help meet...(read more)

Minimize Your Mouse Clicks in IC Packaging with New Customizable Wire Bond Application Mode in 16.6

Jeff Gallagher — Tue, 04 Dec 2012 14:00:00 GMT

Whether it is reducing mouse clicks, minimizing access to menus, eliminating the need to modify the find filter, or providing direct access to change options panel settings without leaving the canvas, anything that can be done to improve the efficiency...(read more)