Cadence PCB Design Blogs

Cadence's Acquisition of Hexagon D&E: A Game-Changer for Multiphysics Innovation

Stephen Smith — Mon, 02 Mar 2026 21:30:00 GMT

Having spent six rewarding years at Hexagon Design and Engineering (D&E), followed by the last three years in leadership at Cadence, I have watched both organizations push the boundaries of what is possible in design and engineering. This week's announcement that Cadence has acquired Hexagon's D&E business isn't just a corporate milestone for me personally—it represents a massive leap forward for the entire engineering community.

As products become smarter, smaller, and more complex, the traditional silos between electronic and mechanical design are no longer sustainable. By bringing Hexagon's world-class simulation and analysis portfolio into the Cadence ecosystem, we are providing our customers with a unified pathway to innovation that was previously fragmented.

Bridging the Gap: The Convergence of ECAD and MCAD

For years, the industry has struggled with the "wall" between electronic computer-aided design (ECAD) and mechanical computer-aided design (MCAD). Engineers often found themselves translating data across disparate platforms, leading to versioning errors, delayed timelines, and missed optimization opportunities.

The integration of Hexagon's D&E expertise with Cadence's computational software leadership effectively dissolves this barrier. We are now uniquely positioned to offer a seamless, collaborative workflow. This convergence allows for true electromechanical co-design, where thermal, structural, and electromagnetic constraints are addressed simultaneously rather than sequentially. For our customers, this means faster time to market and the ability to iterate with a level of precision that was previously out of reach.

A Comprehensive Portfolio for the Entire Design Spectrum

The most immediate advantage to our customers is the sheer breadth of the combined portfolio. We are no longer just providing tools; we are providing a complete, end-to-end design and analysis environment. By integrating Hexagon's market-leading structural, acoustic, and manufacturing analysis tools with Cadence's gold-standard electronic design and multiphysics platform, we now cover the entire spectrum:

From Silicon to Systems: We can now analyze how a microscopic chip architecture impacts the structural integrity and thermal performance of a massive industrial system.
Predictive Accuracy: With Hexagon's heritage in high-fidelity simulation and Cadence's strength in algorithmic physics, our customers can now build "digital twins" with unprecedented accuracy, reducing the need for costly physical prototypes.
Optimization at Scale: Whether in aerospace, automotive, or consumer electronics, our combined technologies enable holistic optimization—balancing weight, power consumption, durability, and signal integrity across a single ecosystem.

Driving Value for Our Customers

The ultimate winner in this acquisition is the customer. This union is built on a shared philosophy: empowering engineers to solve the world's most complex challenges.

Our customers will benefit from a unified support structure, a more aggressive R&D roadmap, and a simplified vendor landscape. More importantly, they gain access to a visionary technology stack that is ready for the era of AI-driven design. We are providing the tools to ensure that the next generation of products is not only functional but optimized for a sustainable and hyper-connected world.

A Personal Note on the Journey Ahead

Having walked the halls of both Hexagon and Cadence, I know the talent, passion, and brilliance that exist within both teams. Bringing these two cultures together creates an innovation powerhouse. I am incredibly proud to be part of this journey and look forward to helping our customers leverage this expanded portfolio to turn their most ambitious ideas into reality—the gap between "what is imagined" and "what is engineered" just got significantly smaller.

Learn more about Cadence's acquisition of Hexagon's Design and Engineering Business.

Ascent: Migrate DE-HDL & OrCAD X Capture to Allegro X PCB System Capture

AsadMakandar — Thu, 26 Feb 2026 13:38:00 GMT

The electronics design world is moving fast, and teams are starting to feel the limits of their existing schematic workflows with Allegro X Design Entry HDL (DE-HDL) or OrCAD X Capture. As design complexity increases and product cycles shrink, engine...(read more)

A Journey Through 2025: PCB and Package Design Learning in Motion

ulrike — Thu, 12 Feb 2026 04:21:00 GMT

2025 was a year of innovation and learning for PCB and Package Design, with 17 new blogs, expanded training programs, digital badges, accelerated learning options, and smarter tools like the GenAI-powered ASK assistant—empowering engineers to design faster, smarter, and with confidence.(read more)

Clarity Solver’s Automated Channel Extraction (ACE) to Be Featured at DesignCon

MSATeam — Wed, 04 Feb 2026 04:48:00 GMT

Visit us at DesignCon 2026, February 24-26, at booth 827, to discover Clarity 3D Solver's automated channel extraction (ACE) technology, a transformative tool designed to eliminate manual bottlenecks to simulating massive multi-channel systems. You will see how the ACE feature provides a scalable, automated path to high-fidelity 3D electromagnetic (EM) analysis, ensuring your designs meet performance targets faster than ever before.

In addition, meet our experts, customers, and partners to learn more about our electronic system design solutions in booth demos, sponsored sessions, and our Cadence networking event.

Demos in Booth 827

Scalable 3D electromagnetic (EM) modeling solutions for interposer/package/PCB
Interposer/package/PCB signal, power, and thermal integrity analysis
How to use real-world measurement data as a foundation for validating EM simulations
End-to-end design flows for advanced multi-chiplet 3D package design
DDR5 @ 12.8Gbps MRDIMM Gen2 for AI in the data center
224G long-reach SerDes for AI data center systems

Cadence Networking Event

Continue your conversations over food and drinks with peers and 12+ Cadence experts at our networking event.

Date: Thursday, February 26

Time: 4:00 pm - 6:00 pm

Location: Great America Ballroom K

See the complete schedule and register now.

Ascent: Training Insights: Version Control in Allegro X PCB System Capture

Priyadarshini N D — Thu, 29 Jan 2026 09:09:00 GMT

In today’s fast-paced PCB design environment, managing design changes efficiently is critical. Imagine working on a complex schematic with many collaborators, generating multiple versions. How do you ensure that every change is tracked, and old...(read more)

Celebrating 2025, an Inspiring Year, with the Cadence Community!

Renu Vibha — Fri, 23 Jan 2026 20:00:00 GMT

2025 was a year of collaboration, learning, and innovation. Together, we achieved incredible milestones that strengthened our vibrant Cadence Community. Here's a look back at the highlights that made this year truly special: Early in the Year: W...(read more)

Accelerating Chiplet Integration in Heterogeneous IC Package Designs

MSATeam — Thu, 15 Jan 2026 04:49:00 GMT

Today’s multi-chip and chiplet solutions are leading the way for the “More than Moore” vision, with companies leveraging packaging technologies to create value and differentiation from their competitors. Silicon via (TSV), wafer-level packaging (WLP), and 3D stacking technologies are providing a tremendous number of packaging options for all form factors. The figure below provides a common example of 3D die/wafer stacking vs. the traditional 2D system on a chip (SoC).

As semiconductor packaging technologies such as chip-on-wafer-on-substrate with redistribution layer (CoWoS-R) and CoWoS local silicon interconnect (CoWoS-L) increase in complexity due to the rapid growth in the number of signals and high-bandwidth memory (HBM) memory integration, high-speed interface areas are a key focus for design and analysis. This complexity challenges traditional design and analysis workflows, as importing large designs into analysis tools and managing redesigns can exceed project time constraints, making it difficult to meet deadlines.

In response to these challenges, Cadence has developed a novel methodology that enables early and iterative optimization of IC package designs. This approach eliminates the need to wait for complete designs or spend excessive time preparing simulations. By integrating in-design analysis and optimization with Cadence’s scalable multiphysics analysis engines, IC package engineers can accelerate design cycles and efficiently improve complex package design efficiently.

Accelerating Chiplet Integration in Heterogeneous IC Package Designs, an on-demand webinar presented by Cadence’s Mark Gerber, Brad Griffin, and Gary Lytle, covers early-stage design optimization that eliminates the need to wait for full design completion. This is done by reducing simulation preparation time through a methodology of rapidly iterating and enhancing designs to align with project management expectations and leveraging scalable multiphysics analysis engines for comprehensive package design evaluation and signoff.

Advanced Packaging Key Challenges and Cadence Solutions

Cadence offers a variety of solutions to address the design challenges of new IC package structures:

In summary, as packaging design has become more complicated, Allegro X Advanced Package Designer Platform continues to lead the IC packaging design community. Cadence design technology has evolved quickly to support 3D planning, silicon bridges, in-design analysis, automated substrate routing, and physical verification (LVS).

Design and Analysis Flow

Constraint-driven design streamlines development and reduces costs, strategic floor planning shortens cycles and lowers expenses, and automated routing speeds workflows and cuts manual work. In-design analysis enables early electrical/thermal issue detection and accelerates signoff and selective design cutting saves engineering time and enables parallel problem-solving.

An example of this flow, covered in the webinar, is a 16Gbps Universal Chiplet Interconnect Express (UCIe) interface with ground trace shielding. The analysis team was tasked with finding the optimal constraints to guide routing, and the routing team needed to implement the routing patterns to meet the constraints. A methodology is reviewed where stringent spacing and shielding is required for longer connections and tighter spacing with less shielding can be used for shorter connections.

The UCIe compliance kit in Sigrity X SystemSI provided guidance on which routing configurations could be used to meet the UCIe electrical requirements. The UCIe interface compliance kit within the Sigrity X topology workbench is shown below.

The bottleneck for advanced package design is routing. Cadence’s advanced substrate router technology (shown below) provides an optimized automated routing flow for 3D-IC design to streamline substrate layout generation. It optimizes the routing of high-density die-to-die and die-to-substrate connections and provides multi-core performance benefits. This technology supports diverse requirements for any angle routing, auto shielding, bus breakout routing, high-density bump escape planning, differential pair routing, and fillet/teardrop insertion for yield improvement.

IC Package Analysis and Signoff

The following figure shows how Sigrity X and Clarity 3D Solver work together to provide advanced IC package signal integrity analysis and signoff.

Three platforms comprise the complete flow: Allegro X Advanced Package Designer Platform, Sigrity X, and Clarity 3D Solver. Together, they allow exploration, in-design analysis, and signoff, including spec-driven compliance reports.

A case study within the webinar demonstrates and provides results for a full 3D extraction of an interposer with Clarity, as well as Sigrity X SystemSI simulation results with the interposer model.

Conclusion

Times have changed and manual-driven design workflows used with yesterday’s IC package designs lack the efficiency required to address electrical, thermal, and mechanical challenges of modern 3D package design. Cadence offers a modern flow that meets the latest design requirements, enabling multi-chip(let) solutions that are leading the way for a “More than Moore” vision. Chip companies are leveraging TSV, WLP, and 3D stacking packaging technologies to create value and differentiation and provide a tremendous number of packaging options for all form factors.

This blog summarizes the Accelerating Chiplet Integration in Heterogeneous IC Package Designs webinar, which presents some of the revolutionary solutions Cadence offers that enable IC companies to create the leading-edge products of the future (see below table). Click here to learn more and view this valuable webinar on demand.

You can learn more about Allegro X Advanced Package Designer Platform here, Sigrity X here, and Clarity 3D Solver here. You can also learn more about Cadence chiplet design solutions by downloading our eBook, “Helping You Realize Your Chiplet Ambitions.”

Integrity 3D-IC Course Updated for Version 25.1

Vince Kim — Tue, 16 Dec 2025 01:00:00 GMT

Unlocking Advanced 3D-IC Design: The Updated Integrity 3D-IC Course The semiconductor industry is rapidly evolving, and so are the tools and methodologies that enable cutting-edge designs. To keep pace with these advancements, the Integrity 3D-IC cou...(read more)

System Analysis Knowledge Bytes: Two New Courses to Refine Your PI Skills

Vince Kim — Mon, 15 Dec 2025 23:00:00 GMT

The System Analysis Knowledge Bytes blog series explores the capabilities and potential of the System Analysis tools offered by Cadence. In addition to providing insight into the useful features and enhancements in this area, this series aims to broa...(read more)

System Analysis Knowledge Bytes: NEW COURSE - PDN and Voltage Ripple Analysis

Vince Kim — Mon, 15 Dec 2025 20:00:00 GMT

Revolutionizing Design: Cadence Community Forums Empowering AI-Driven Innovation

Renu Vibha — Wed, 10 Dec 2025 06:41:00 GMT

As AI-driven design gains momentum, Cadence is leading the way, leveraging agentic AI to transform how engineers innovate, solve complex challenges, and build next-generation systems. Community forums have evolved far beyond simple Q&A space...(read more)

IC Packagers: Optimizing Connectivity Between Die Escape Routing and BGA Balls

JFLepere — Mon, 08 Dec 2025 09:53:00 GMT

Package designers need to add escape routes to a die to facilitate further package routing: these routes provide essential pathways for signals to exit the die and reach other parts of the package or PCB. Without well-planned escape routing, signal t...(read more)

How to Use AI to Optimize Your Power Delivery Network

MSATeam — Thu, 04 Dec 2025 01:30:00 GMT

Modern power delivery network (PDN) design poses numerous challenges. Traditionally, designers rely on target impedance analysis—a widely used and effective starting point for ensuring power integrity (PI). While its simplicity and historical success make it appealing, in today's high-speed, high-density systems, its limitations are becoming more apparent with faster transistor switching and increased current demands.

Jared James, product engineer architect at Cadence, presented at EDI CON Online 2025 a new methodology using a target objective that considers both cost and performance. Cadence Optimality Intelligent System Explorer, along with Sigrity X SystemPI, is leveraged to determine the ideal combination of decoupling capacitor (decap) values and empty locations to achieve acceptable PDN performance at the lowest possible cost.

Traditional Target Impedance Analysis

The typical target impedance flow follows these steps:

Define power requirements by determining the core voltage and maximum transient current for each power rail and define acceptable voltage ripple (usually 3-5%)
Calculate target impedance:
Simulate PDN impedance using software tools to simulate the impedance of the PDN across frequency and plot impedance vs. frequency
Compare to the target impedance by overlying the target impedance line on the impedance plot
Optimize the decoupling network by adjusting capacitor values, quantities and placements, adding low-ESL capacitors for high-frequency noise, and using bulk capacitors for low-frequency transients
Re-simulate and iterate
Validate with time-domain simulations and compare with voltage ripple specifications

This flow has several limitations, including oversimplification of dynamic behavior, frequency range ambiguity, capacitor anti-resonance, and cost and space tradeoffs that can trigger performance vs. practicality issues. The focus of this paper is to improve the validation in Step 7.

The Cadence Sigrity X SystemPI/Optimality Explorer Methodology

The new Cadence methodology leverages Sigrity X SystemPI, a model-based topology environment that has been adapted for impedance analysis (AC), IR drop analysis (DC), and time-domain power ripple and transient behavior. System PI integrates models from the chip, interposer, package, and PCB, while extraction tools like Voltus IC power integrity solution and Clarity 3D Solver help build these models.

SystemPI works with the Optimality engine, which utilizes a novel reinforcement learning technology that significantly reduces the number of individual simulations needed, especially for high dimensional complex SI/PI and RF synthesis applications. The primary advantage of Optimality is efficiency; it achieves optimized solutions by evaluating objective functions sparingly, allowing users to obtain accurate optimized PI results faster.

In this flow, a SystemPI testbench has been built with various design parameters, including decap models and the number of decaps at each position. Once the simulation setup is complete, Optimality explores the full design space by running targeted simulations. It analyzes each result, updates design variables based on a defined objective function and constraints and iteratively refines the model. This process enables Optimality to adjust decap values and constraints efficiently, ultimately producing an optimized design ready for signoff.

The primary advantage of Optimality is its efficiency in that it evaluates objective functions just enough to find accurate, optimized results quickly, which significantly reduces the number of required simulations, This is especially valuable in high-dimensional, complex design spaces.

Test Case Demonstration

The EDI CON talk presents a test case highlights how SystemPI and Optimality work together to streamline PDN design. As a demonstration of the Optimality engine in the SystemPI flow, a test case was created to optimize the decap values of multiple decap positions using time-domain simulations. The objective function is to minimize the initial undershoot and the number of needed decaps simultaneously. The below image shows the test case setup.

Given a list of possible decap values, find the decap values that provides the lowest undershoot from a die current step of 1A. Simulation results showed a reduced number of needed decaps while exceeding the undershoot spec of 5% (50mV).

The plot below illustrates the simulation results. Each downward step represents a new simulation that produced a lower objective value than the previous best. While only the updated points are shown, intermediate simulations can be displayed if needed. The first ~57 simulations were run randomly to build a diverse sample space, which is known as the exploration phase. Around simulation 58, the algorithm began balancing exploration with exploitation, refining its search based on prior results. From that point, Optimality iteratively ran simulations, updated the model, and adjusted design parameters until either the maximum of 200 simulations was reached, or an optimal solution was found. In this case, the process concluded before reaching 140 simulations.

The next figure compares two scenarios: the red curve represents the worst-case condition with all decap positions left empty, while the green curve shows the optimized result.As you can see, the optimized design significantly reduces power ripple compared to the baseline. While our primary measurement focused on initial undershoot, the tool can easily be configured to target other metrics—such as minimizing ripple beyond the initial transient—depending on design goals.

Conclusion

The optimized result exceeded the 50mV undershoot spec while reducing the number of decaps by four. At simulation index 96, the power ripple was just under 18mV, with four blank decap positions, demonstrating both performance and cost savings. Achieving this result with fewer than 200 simulations out of over two trillion possible combinations highlights the efficiency and effectiveness of the Optimality engine.

To learn more about this revolutionary new methodology, access the EDI CON 2025 on-demand webinar. Visit our product pages to learn more about Optimality Intelligent System Explorer, Sigrity X SystemPI, Voltus IC Power Integrity Solution, and Clarity 3D Solver.

Determining Effects on PDN Target Impedance Using Sigrity X

MSATeam — Tue, 02 Dec 2025 22:00:00 GMT

Ensuring a functional power distribution network (PDN) for chips, packages, and PCBs is a challenge for system design engineers facing increasingly difficult design targets and varying design and hardware delivery dates. A CadenceLIVE 2025 presentation is now available on demand that examines work done as part of Project Kuiper, Amazon's low Earth orbit satellite broadband network with a mission to deliver fast, reliable internet to customers and communities around the world.

Written by Ethan Koether, senior signal and power integrity engineer for Project Kuiper, along with industry experts Kristoffer Skytte, John Phillips, and Shirin Farrahi of Cadence, Abe Hartman of Oracle, Mario Rotigni, retired, and Istvan Novak of Samtec, the paper explores the spatial, frequency, and loading effects of a system on PDN target impedance requirements.

Project Goals

The presentation presents the project goals and examines two power delivery strategies: single point-of-load PDNs and PDNs feeding multiple parallel loads.

Compare single point-of-load PDNs and PDNs feeding multiple parallel loads
Correlate bandwidth changes from the DC source pads to IC pads on the PCB
Present guidelines to avoid over-designing PDNs
Understand considerations for complex, multi-load power delivery designs
Update PDN target impedance methodology to be a function of frequency and spatial position

The required bandwidth (BW) of the PDN response depends on the supply network location. The project correlates Cadence's Sigrity X PowerSI simulations with vector network analyzer (VNA) measurements to determine bandwidth changes with major PDN components from the DC source pads to IC pads on the PCB.

The paper highlights that impedance requirements differ across the system due to spatial filtering effects.

Power integrity experts must decide whether to combine power rails or provide separate power for each device. Using two high-power processor-based server systems, the project measures and simulates power rail impedance at various PDN points. The findings offer guidelines to avoid over-designing PDNs and to understand considerations for complex multi-load power deliveries.

Conclusion

The presentation concludes that good simulation/measurement correlation was achieved for two high-power DUTs.

It highlights the spatial filtering effects of the passive PDN and their physical roots and shows that the low-frequency RC cutoff due to net capacitance and plane resistance was in the ~10kHz range. The target impedance methodology described in the presentation can be adapted and optimized for individual applications as the different noise sources and filters in a complex system PDN are considered.

You can now view Project Kuiper's CadenceLIVE presentation on demand.

Empowering Innovation in Abu Dhabi - CadenceCONNECT Middle East

Stephen Smith — Tue, 02 Dec 2025 21:30:00 GMT

Cadence recently had the honor of hosting CadenceCONNECT: Middle East Tech Days at the prestigious Khalifa University in Abu Dhabi. This event was a testament to our commitment to fostering innovation and collaboration in one of the world's most ...(read more)

Cadence PCB Design Blogs

Cadence's Acquisition of Hexagon D&E: A Game-Changer for Multiphysics Innovation

Bridging the Gap: The Convergence of ECAD and MCAD

A Comprehensive Portfolio for the Entire Design Spectrum

Driving Value for Our Customers

A Personal Note on the Journey Ahead

Ascent: Migrate DE-HDL & OrCAD X Capture to Allegro X PCB System Capture

A Journey Through 2025: PCB and Package Design Learning in Motion

Clarity Solver’s Automated Channel Extraction (ACE) to Be Featured at DesignCon

Demos in Booth 827

Sponsored Sessions

Cadence Networking Event

Ascent: Training Insights: Version Control in Allegro X PCB System Capture

Celebrating 2025, an Inspiring Year, with the Cadence Community!

Accelerating Chiplet Integration in Heterogeneous IC Package Designs

Advanced Packaging Key Challenges and Cadence Solutions

Design and Analysis Flow

IC Package Analysis and Signoff

Conclusion

Integrity 3D-IC Course Updated for Version 25.1

System Analysis Knowledge Bytes: Two New Courses to Refine Your PI Skills

System Analysis Knowledge Bytes: NEW COURSE - PDN and Voltage Ripple Analysis

Revolutionizing Design: Cadence Community Forums Empowering AI-Driven Innovation

IC Packagers: Optimizing Connectivity Between Die Escape Routing and BGA Balls

How to Use AI to Optimize Your Power Delivery Network

Traditional Target Impedance Analysis

The Cadence Sigrity X SystemPI/Optimality Explorer Methodology

Test Case Demonstration

Conclusion

Determining Effects on PDN Target Impedance Using Sigrity X

Project Goals

Conclusion

Empowering Innovation in Abu Dhabi - CadenceCONNECT Middle East