Cadence PCB Design Blogs

What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!

Jerry GenPart — Mon, 20 May 2013 19:02:00 GMT

Just a very "quick read" on a new option for Quickplace this week.

The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components are placed not to overlap each other. As a result, the application may fail to place components if space is not available. A new control option in the 16.6 release,"Overlap components by," has been introduced to improve completion percentages. You can control the amount of overlap - the default value is seeded at 50%.

Read on for more details …

Invoke Place – Quickplace
Enable the option "Overlap components by," which is located near the end of the form:

Set ‘Edge’ = ‘Top’
Click ‘Place’ then review the results:

Feel free to provide feedback on this new capability.

Jerry “GenPart” Grzenia

What's Good About AMS Data Precision Options? They’re in the 16.6 Release!

Jerry GenPart — Mon, 13 May 2013 16:14:00 GMT

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage loses its resolution, displaying staircase waveforms. With 64-bit precision, for the same signal, a perfect ramp waveform is displayed.

Here’s a simulation output with the 32-bit data precision set (notice the staircase style of output):

Now, change the Probe Data option to 64-bit:

Here’s the resulting waveform (notice the smooth results):

I look forward to your feedback!

Jerry "GenPart" Grzenia

What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements!

Jerry GenPart — Mon, 06 May 2013 17:14:00 GMT

Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS (Capture) product has a few new enhancements for Saving designs.

Read on for more details ...

Save

In the Hierarchy viewer, you’ll now see pages and library components which have been modified by the designer marked with an asterisk (“*”). These are schematics and pages that require saving prior to existing Capture:

Save As

This enables a user-controlled save of associated files along with the project at a new specified location while maintaining the original references.

Available options:

Copy DSN to Project Folder
Rename DSN to match Project
Copy all referred files present within the project folder
Copy all referred files present outside of the project folder

Saved associated files include referred projects, designs, libraries, simulation profiles, output files, etc.

Select Project (Design Resources) and RMB click on Save As:

Change the destination directory and project name:

Please share your experiences using these new features.

Jerry "GenPart" Grzenia

Customer Support Recommended - Instance and Occurrence Modes of Design Annotation using OrCAD Capture

Naveen — Thu, 02 May 2013 13:51:00 GMT

Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct and optimized.

Annotation is the automated process of assigning reference designators in Allegro Design Entry CIS, also known as OrCAD Capture. The following AppNote clarifies the fundamentals of the Instance and occurrence modes of annotation in a Capture based design. It explains various aspects of annotation and simplifies the concept behind Instance and Occurrence modes.

What are Instance and Occurrence Modes?

These two modes essentially determine how a design is annotated. The Annotate dialog, as shown in Fig.2, provides the option to annotate a design in Instance or Occurrence modes. The recommended mode of annotation is determined based on the conditions specified in the following table:

Table.1 - Recommended annotation modes

Fig.2 - Annotate Dialog Box

Property Editor

The property editor for any part in a Capture design has a white column and one or more yellow columns. The white column is the instance column and yellow columns are occurrence columns.

Flat and Simple Hierarchical Design

With the above explanation, we can deduce that no part contains duplicate occurrence in a flat or simple hierarchical design. The property editor contains one white and one yellow column for every part and both contain the same value for all the properties. By default, the yellow column is hidden for an INSTANCE mode design. You can click the plus sign to expand the yellow column.

Fig. 3 - Property Editor of a Part in a Flat/Simple-Hierarchical Design

For Complex Designs

The property editor includes a yellow column for each occurrence of a part. If a design contains 3 duplicate hierarchical blocks, for all the parts within that hierarchical block, the property editor will contain one white and three yellow columns.

The Part Reference of parts in yellow columns (at the Occurrence level) must be unique after correct annotation of the design.

Fig.4 - Property Editor of a Part in a Complex Hierarchical Design

In Fig.4, observe that capacitors have four occurrences in the design. C1 has four occurrences, C1, C5, C9 and C13.

Annotation

Annotation is the automated process of assigning reference designators to all the parts placed in the design. Under ideal conditions, annotation must be done as shown in Table1.
However, you can select the desired radio button in Fig.2 for any type of design. So, let's understand what exactly happens when the INSTANCE or OCCURRENCE radio buttons are selected.

Instance Mode

When a design is annotated in the Instance mode, the part reference is assigned/modified in the white column, representing the instance mode, of the property editor.
As a flat or simple hierarchical design is expected to have the same values in the white and yellow columns, this is the preferred mode of annotation for a flat or simple hierarchical design.

Occurrence Mode

When a design is annotated in the Occurrence mode:

Mostly, the part reference is assigned/modified in the yellow column representing the Occurrence mode of the property editor.
At times, the Occurrence value for a property may be picked from the Instance column. Such columns appear striped. In Fig 4a, L1 is striped because it is being picked from instance columns while L3 is not striped because it has been assigned at the occurrence level. (See Fig 5)

Fig 5 - Occurrence mode annotation

Note: As a part will have more than one occurrence in a complex hierarchical design, it is essential that all these occurrences have a unique reference designator in the design. For this, the yellow columns for the parts must have unique reference designator. Therefore, for a complex hierarchical design, the preferred mode of annotation is Occurrence. This ensures that each occurrence gets a unique reference designator.

Controlled Annotation

You can also perform controlled annotation in a multi-page design or a design which contains hierarchical blocks. You can specify the range of reference designator under a hierarchical block or a page. To do this, use the Refdes control required option in the Annotate dialog. Selecting this option gives an additional control to specify range for reference designators as per the hierarchical block or schematic pages.

Fig 6 - options for controlled annotation

For hierarchical designs, you can define a range for each hierarchical block. For flat designs, you can define a range for schematic pages.

Exception in Design Annotation Modes

Sometimes it can be seen that for a flat or simple hierarchical design, the preferred annotation mode is Occurrence. This is the case when any property value has been manually modified in the yellow column (occurrence level). Even adding a space in a property value at the occurrence level will make the preferred mode change from occurrence to instance. In such cases, the preferred mode can be changed using the Accessories > Transfer Occ. Prop. to Instance > Push Occ. Prop into Instance command. Sometimes it can be seen that for a flat or simple hierarchical design, the preferred annotation mode is Occurrence. This is the case when any property value has been manually modified in the yellow column (occurrence level). Even adding a space in a property value at the occurrence level will make the preferred mode change from occurrence to instance. In such cases, the preferred mode can be changed using the Accessories > Transfer Occ. Prop. to Instance > Push Occ. Prop into Instance command.

This will transfer all the yellow column property values (occurrence level properties) to white column (Instance), making both the same and switching the design back to the Instance mode.

Refer the following AppNote for the detailed understanding of these modes in the Capture - Allegro PCB Editor flow.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com/).

Naveen Konchada
Cadence Customer Support

What's Good About ADW’s Design Migration? 16.6 has many new enhancements!

Jerry GenPart — Mon, 29 Apr 2013 18:24:00 GMT

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables:

–   Netassembler
–   Archiver
–   Purge
–   Packager

It was also less robust with dependencies on external programs, and the error resolution was not always clear.

With the 16.6 release, design migration is more efficient and less error prone. Below is a quick summary of what’s new in ADW 16.6 Design Migration.

Read on for more details …

New 16.6 Design Migration Features and Settings
Command line operation
“Designmigration –help” for full list of options and use

PART_NUMBER synchronization from the Library Flow
<PCBDW_LIB>/distributions/env/libimport_parts.ini file

Directive based migration
The project .cpm file directives can be preserved during migration
<ADW_CONF_ROOT>/<ATDM_COMPANY>/<ATDM_SITE>/cdssetup/pcbdw/MigrateDirective.txt

Running Design Migration

Please share your experience using the ADW Design Migration process.

Jerry "GenPart" Grzenia

What's Good About FSP’s Design Compare? Check Out 16.6!

Jerry GenPart — Thu, 18 Apr 2013 14:59:00 GMT

The 16.6 Allegro FPGA System Planner (FSP) product has an extremely helpful Design Compare capability.

With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP Design Compare form compares two FSP designs and is similar, but not identical, to the one used in Allegro PCB Editor.

The Design Compare form

Design Compare is a stand-alone form – it does not require the master, or any other design, to be open in FSP.
Click on the Design Compare icon or use the File > Design Compare pull-down:

In the Design Compare form, select the PCB copy on the right and the master design on the left (the order does not make a difference, but it’s easier to track differences if the master design is on the left).

Click the Compare button.

The “Show Only Diff” button helps to focus in on the differences. This is a “sticky” button – click to turn it on, click to turn it off.

The green arrows between the two sides and the yellow arrows at the top perform identical functions.

“Merge All To Left” and “Merge All To Right” will sync the designs in one step:

The FSP version of Design Compare is a little different than the one used in Allegro PCB editor. For one, there is no cross-probing in FSP like there is in Allegro. Also, in Allegro, the sections (connectivity, placement/ref des, etc.) are shown as tabs because the differences are displayed as a flattened list, for the entire design. In FSP, the items are displayed hierarchically and are selected from a drop-down:

Placement differences between the PCB copy and the FSP master are shown textually and graphically:

Merge the changes

You can merge all of the PCB changes into the FSP master. Click the “Merge All To Left” button:

You may encounter situations where an attempt to merge one signal(s) forces the merge of other signals:

This could happen if there is a cyclic dependency in the net connectivity. For example, if net n1 has to be moved to pin B26 and B26 is currently connected to net n2, then n1 and n2 are dependent nets. In other words, they both have to be moved together.

Please share your experiences using the FSP Design Compare capability.

Jerry “GenPart” Grzenia

What's Good About DEHDL’s Constraints Comparison? The Secret's in the 16.6 Release!

Jerry GenPart — Tue, 16 Apr 2013 13:40:00 GMT

The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare two databases for constraint differences. The databases that can be compared are of the following types:
• Schematics (.cpm)
• Layout design (.brd, .sip, .mcm)
• Constraints Manager Database (.dcf, .tcf)

The Constraint Comparison Utility can be used for comparing two different revisions/versions of the schematic or board databases. This utility can also be used for comparing the schematic database with the board database. A report is generated as a result of the comparison and lets you see all the changes which have been made to the design database since it was last synced up. This report helps you ensure that none of the constraints are conflicting and thus might overwrite on sync up.

The utility can be integrated in any of your design flows where you feel that you need to see the constraints differences in two databases before proceeding further in the design.
The utility can be invoked from the command line using command cmDiffUtility. This command launches the Cadence Constraints Differencing Utility dialog box, as shown below, where you can specify the two databases which need to be compared for constraints differences:

The button (browse) can be used to select the database. Once you click this button, the file selection dialog box appears. This dialog box displays the files based on the file type filter. By default the filter is set to “Constraints Files (*.dcf, *.tcf)”.

You can select any of the following options to change the filter setting and select appropriate databases:

Once both the databases are selected, the “Compare Files” button is enabled. Click this button to start the database comparison. The results of comparison between the two databases are reported in a Firefox window:

The report is displayed as a single screen, with two frames – left frame containing the object tree and the right frame containing the details of the selected tree item.

The complete report contains hyperlinks and helps in navigating through any of the objects within the various tools – Design Entry HDL, Allegro PCB Editor, Constraint Manger. When you click a category in the tree in the left frame, the details containing lists of all the objects of that category are opened in the right frame. These details contain the object name and brief description of the changes observed.

All the object names are also hyperlinked. You can click any of the objects to view more details. The object names are also visible in the tree view in the left frame, and the detailed view can also be opened by selecting the object name there. Since the different object categories are listed in the tree view, you will notice that you can navigate to the same difference from multiple places.

Please share your experiences using this new feature.

Jerry “GenPart” Grzenia

What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself in 16.6!

Jerry GenPart — Tue, 09 Apr 2013 15:47:00 GMT

Beginning with the Allegro PCB Editor 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer types. Currently, a GCSF supports four types of layers: TOP, INTERNAL (internal signal), PLANE, and BOTTOM.

Importing a GCSF will not update the design’s cross-section, but will update the design’s constraint information (electrical, physical, and spacing) based upon the current import modes (overwrite, merge, and replace).

When a GCSF is imported into a board, constraints from that techfile will be mapped as follows -
1.    TOP - TOP (topmost etch layer)
2.    INTERNAL - signal layers between TOP and BOTTOM
3.    PLANE - all plane layers
4.    BOTTOM - BOTTOM (bottommost etch layer)

Generating a GCSF

1. Open an existing board or create a new one and edit constraints.
2. In Constraint Manager, use File > Export > (Technology file or Constraints file):

3. Select the “Generic” radio button in the “Export cross-section” section.

The “Generic” radio button is enabled only if the “Physical & spacing constraints” box is checked.
The “Configure” button is enabled only when the “Generic” radio button is selected.
The “None” radio button is enabled only if “Physical & spacing constraints” box is not checked – otherwise cross-section data is necessary.

4. Click the “Configure” button if you want to select the layers you would like to use as TOP, BOTTOM, INTERNAL, and PLANE (layer mapping):

This step is optional. If generic cross-section is not configured, the default mapping will be used.
User selections are remembered only for the current dialog form – when you invoke the export dialog again, the default mapping will be used.

Default mapping:

TOP: first etch layer

INTERNAL: first signal layer after TOP

PLANE: first plane layer

BOTTOM: last etch layer

To exclude a generic layer from the techfile, select <IGNORE>:

In the situation shown in the screenshot above, the resulting generic techfile will have only three generic layers – TOP, PLANE, and BOTTOM.

Importing GCSF

Open Constraint Manager and select File > Import > (Technology file or Constraints file).
Select the GCSF that you have exported from a different database and choose an Import Mode (overwrite, merge, or replace).

If in the imported GCSF some of the generic layers are ignored, then layers matching the ignored layer will not be changed. This is what the report will look like:

Note: When a GCSF is imported, the cross-section of the original board stays intact (i.e. the number of layers, their names, and characteristics remain as before importing; only the Csets are imported).

The GCSF techfile units will behave the same way as any other techfile units. A suggested approach would be to have the same units used in both the original and the target board.

I look forward to your feedback!

Jerry “GenPart” Grzenia

What's Good About RF PCB and Autoplace? 16.6 Has Many New Enhancements!

Jerry GenPart — Wed, 03 Apr 2013 15:04:00 GMT

The 16.6 Allegro RF PCB application has many new enhancements.

I’ll cover a few over the next several weeks. Here are some major autoplace related enhancements:

Grouping in Design Entry HDL (DEHDL)
Allegro PCB Editor Enhancements

Read on for more details …

Autoplace is a very important step for RF layout after the schematic is transferred to PCB layout. The system will automatically create groups based on connectivity during the autoplace process. This will result in many groups in autoplace and it’s difficult to find the proper groups to do autoplace. Designers like to define groups in the schematic based on functions such as LNA, pre-amplifier and so on and then select the proper groups to start autoplace.

In 16.6, we’ve added some new commands in DEHDL to support grouping, such as add group, disband group, display group and so on. In this case, designers can easily control the groups for autoplace. The detailed commands are:

Add Group will attach a property (RFGROUP) to the selected components.
Add Split will attach a property (RFSPLIT) to the wires selected. If a wire is attached with this property, then the logic group will be broken at here (one big logic group will be split into two logic groups).
Disband will remove the RFGROUP property from each RF component for the specific group.
Exclude will remove the property for selected objects (RFGROUP for RF components or RFSPLIT for wires).
Display Group will highlight/report the RF components within a specific group.
Display Split will highlight all wires with the RFSPLIT property.

All these commands are only available in the DEHDL pre-selection mode.

When you transfer the schematic to layout and launch autoplace, you will see the groups are classified differently, the group names added in schematic are reflected in the autoplace form:

You can use the Group filter to easily find/locate some specific groups to do autoplace.

RF Grouping in the Front End (DEHDL)

To use the grouping functionality in the schematic, you need to select Tools->Options and check the “Enable Pre-select Mode.” You will see the RF PCB menu as follows:

If you check “Enable Windows Mode” as well, then Import IFF… item will not be available under the RF-PCB menu. You can find it from File->Import->Import IFF…->RF-PCB.

Add Group

You need to first select some RF components (or non-RF components) and then click RF-PCB->RF Group->Add Group. The following dialog will pop up:

You can enter a new group name or select an existing group from the drop-down list. If the existing group includes elements outside the current page, you need to select Module radio option. You can only select the components in current page to add to a group.

Add Split

Select a wire or multiple wires and then click RF-PCB->RF Group->Add Split. The RFSPLIT property will be attached to the wires selected. You can’t select wires crossing pages to add split. That means you can only select the wires in the current page for this command.

For example, in the schematic, two wires are attached with the RFSPLIT property as following:

There will be three logic groups in the layout for autoplace even though they are actually connected together logically:

Disband

Click RF-PCB->RF Group->Disband. The following dialog will appear:

All available groups will be listed in the drop-down list. Select a group and select the proper scope and then Apply to disband the group. The RFGROUP property will be removed from each component of the group.

Exclude

Select one or more components with the RFGROUP property attached or one or more wires with the RFSPLIT attached and then click RF-PCB->RF Group->Exclude. The property will be removed for the selected objects. This command also works for the current page objects only.

Display Group

Click RF-PCB->RF Group->Display Group. The following dialog will appear:

You can display one group from the drop-down list or all groups by selecting All from the drop-down list. To display a group including elements in other pages, you can select Module radio option. Click Apply or OK. All components within the selected groups will be listed in the command line if the module option is selected, and the components of the selected groups will be highlighted in the current page.

Display Split

Click RF-PCB->RF Group->Display Split. The following dialog will appear:

OK to highlight the wires with the RFSPLIT property in the current page. To get the description of each wire with the RFSPLIT property within the current page, select Page option. To get the description of each wire with the RFSPLIT property in the whole design, select Module option.

Enhancements in Back End (Allegro PCB Editor)

In layout, launch RF-PCB->Autoplace. The dialog will appear:

All components will be classified into different logic groups. Each logic group will have a name with the prefix “_rfGroup”. If you have already defined a group in schematic (for example ABC), then this name will be the name for a real physical group in layout. This name will be attached following the logic name within brackets such as _rfGroup1(ABC).

Some other enhancements for autoplace are:
•   Add a new check box “Ignore FIXED property”
•   A new mark “A” for the groups just completed autoplace
•   A filter to find/locate a group
•   Ratsnests display during autoplace
•   Moving clearances
•   Performance enhancements

If you check the “Ignore FIXED property” option, then a fixed component can be moved as well during the autoplace.
There are two kinds of marks for the groups. A group with a “P” mark means this group is already placed into canvas before the autoplace command launched. A group with an “A” mark (green color) means this group completed the autoplace in the current session. A group without any marks means this group is still unplaced and you may need to do autoplace for it.
The autoplace is enhanced to show the ratsnests while the dynamic path is attached to your mouse during the autoplace process. This makes it is easy for you to place the group to the proper location:

Another enhancement is to support the clearance moving as well for the autoplace--for example, after completing the autoplace for a logical group and then adding the clearances for the components within the group. If you redo the autoplace and move to a different location to place the group, the clearances will be moved as well. Before that, the clearances will not go with the RF components:

Please share your experiences using these new capabilities.

Jerry “GenPart” Grzenia

What's Good About PCB SI and Vias? 16.6 Has Many New Enhancements!

Jerry GenPart — Mon, 25 Mar 2013 16:55:00 GMT

In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models.

Read on for more details …

Adding Vias

Adding a via is easier and faster than before. You no longer have to go through the Via Model Generator to create a model nor are you required to search the list of existing models that fit the need. The difference is that you are now adding a via rather than a via model. The via may not be pre-solved to a specific model.

The current way of adding a via in SigXp is still supported and unchanged. You can still add a via model on the canvas.

In order to add these “dynamic” vias in SigXp, a layerstack will have to be present in the topology. In a new topology this can be accomplished by using the Manage LayerStacks function to create or import a layerstack. When a topology is extracted from Allegro, the layerstack of that board is automatically imported in the topology.

A new via is added with two nodes (two connection points) on the canvas. When newly added, the two nodes are not tied to any specific layer as they will take on the properties of the connected node, so the label of those nodes will be Layer1 and Layer2:

If a trace is connected and is on a particular layer then the via node is assumed to be on that layer and will take its properties. In the case of a "floating trace" (a trace not on a layer stack layer), the via node will take its properties and still say LayerX (unchanged). Since we do not know what layer that is, we will assume the top or bottom most layer of the via structure:

The prior release (16.5) via toolbar button is a two-part button which lists all available via models on the right hand side pulldown:

Clicking on the left side of the button (the one with the via image) brings up the Add Element Browser. In 16.6, the left part of the Add Via button will add the new “dynamic” via with only two nodes. The pulldown remains unchanged to list the pre-solved via models.

Reuse of Via Models

You will want to reuse already solved via models in SigXp. To do that, the same technique used today is available. You can either select the right button of the Add Via toolbar button, which will list all existing via models available sorted by types, or RMB > Add Element can still be used to choose the desired via model.

When these via models are added to the canvas, the model is “locked” to the via and cannot be changed - this is the via model that will be used to simulate.

Via Parameters

The new (dynamic) via has the following parameters which are listed in the standard parameters spreadsheet. These parameters can be modified:

model   The via model associated with the via. A via which has no model yet will have UNMODELED as a model. Once solved, the name of the model will be used.
viaOutputFormat   The format with which the model was solved. If no model exists yet, the format is blank.
viaPadstack   The name of an available padstack. This parameter is a pulldown which lists the available padstack files on disk and in the library.
viaTopLayer   The top most layer of the via drill.
viaBottomLayer   The bottom most layer of the via drill.

For coupled vias the parameters will be a little different. It will show the via name with which it is coupled as well as the distance between them. Aside from that, it will look just like a single via.

Padstack Consumption

SigXp can now consume and optionally modify the same padstacks as Allegro PCB Editor. You can to import *.pad files and keep them as file if they are different than the library.

You can access the Via Padstack Manager through the menus using Setup > Manage Via Padstacks, or by right clicking in the SigXp canvas and selecting Manage Via Padstacks. Editing or creating a new padstack will use the same padstack editor available in Allegro. The padstack can be saved as an external file. If shapes are associated with the padstack, they will be stored in the same location. All information in the padstack relevant to the via is used to generate the model:

Via Modeling

When a new “dynamic” via is added to the topology, no model is associated with it. Only when you perform a simulation or manually solve the via will the field solver be called. In batch mode, the field solver uses the standard via modeling preferences that are currently found in PCB SI. These settings are available in SigXp and can be accessed through the menus using Analyze > Via Setup Preferences or by right clicking in the SigXp canvas and selecting Via Setup Preferences:

The via subckt section is built using the padstack information, the layerstack and the connected traces, as is done in Allegro PCB SI. The via model is stored in the working IML file.

Coupling Vias

With this feature, you can couple 2 single vias to form one single model. You can select 2 vias in the SigXp canvas and select Couple from the right mouse button menu:

When the Couple function is used, you will be required to specify a spacing between the vias:

This spacing is added to the parameters in the spreadsheet:

When you select a coupled via, all vias in the set will be selected:

You can decouple the vias by selecting Decouple from the right mouse button when one of the vias is selected:

Please share your experiences using these 16.6 features.

Jerry "GenPart" Grzenia