Cadence Mixed-Signal Design Blogs

Managing Inherited Connections with CPF in Virtuoso

AndreasLenz — Wed, 23 May 2012 17:10:00 GMT

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso.

Why use CPF?

The Common Power Format (CPF) describes the design power intent for the whole flow, including digital implementation in Encounter, custom/analog implementation in Virtuoso Schematic Editor, and further into simulation. In Virtuoso Schematic XL, CPF creates the inherited connections for you in an automated way. You may want to reuse the same CPF that was used for your digital block implementation in Encounter.

What might CPF contain?
- Power domains with their shutoff conditions if applicable
- Power and ground nets
- Technology for low power: isolation cells, level-shifters (need to be registered as special cell in Virtuoso)
- Isolation, shifting and retention policy
- Power modes and analysis views
- Library sets
- Global connection

What does CPF not contain?

CPF is not a command file. It doesn't contain power domain coordinates, power routing details, number of power switches, or implementation details.

How can I handle the inherited connections ?

Within the Virtuoso IC 6.1.5 release it is possible to describe your low power intent through a CPF file. This posting describes the method according to the use model described above. Further information, including supported CPF commands, is available in the Virtuoso Schematic XL User Guide.

What are the requirements?

A consistent power intent for the analog and digital parts of your design is required. You could have explicit power pins and implicit net sets and net expressions defined in parallel. CPF will update or create the net sets and expressions.

All of the power and ground nets (PG nets) in your design should have the signal type Power or Ground. The default signal type is Signal. This might be the case if you take a closer look at your standard cell library. Power and Ground nets are very often defined as type signal. Another requirement is that your standard cell power connection must be described as an inherited connection. Before you start, make sure that the CPF created is verified for correctness using the Cadence Conformal Low Power product.

And as mentioned before, you need Schematics XL to make use of CPF.

Step by Step introduction

Setup Schematics XL

After Verilog import Open Check - Rules Setup - Inherited Connections and enable the CPF nets error switch.

To verify the signal types choose Options - Check and enable "set Signal Type from Net and Type Registration."

Applying the right signal type

As mentioned above, we need to make sure to set the right signal type. Descend in the hierarchy by double clicking on a symbol until the standard cells occur. Are your PG nets defined as inherited connections, but the signal type is Signal? If so you need to change it. Because your standard cell library usually is set to read only, we need to change the cells in your design using the register API to provide a complete list of all your PG nets (don't miss the std cell PG nets):

ciRegisterNet("power" list("VDD" "vdd" "VDD!" "VDDA" "VDDD" ....)

ciRegisterNet("ground" list("VSS" "vss" "VSS!" "GND" "gnd" ....)

Now check if the PG Signal type gets applied correctly:

ciGetNetNames("power") ciGetNetNames("ground")

Finally we use the Check - Hierarchy command to propagate the changes to the schematic. Don't enable save schematics since you may don't have write access to the Library

Shortcut: schHiCheckHier()

Import the CPF file

Open "File - Import Power Intend" or type schHiAddCPFNetSets() in the CIW command line to open the CPF import form. Library, Cell and View Name are already filled in. The View Name List may be changed by adopting by editing "Options - Check - Views to check.

Specify your CPF File name

Use ‘Register Special Low Power cells' for Isolation cells , Level shifter cells, Power switches, ...Use ‘Remove existing Power Intend' if you are not sure which power is defined and you want to rebuild the power connection. The alternative is to use "Edit - Power Intend - Remove netSet properties." The progress is logged in CIW and CDS.log files.

Again, the last step is to propagate the power intent through the hierarchies and we use "Check - Hierarchy."

Verify the power intent

After importing and applying the CPF file you may want to verify the created power intent. To verify the created power domains, rules, mappings ... Enable "Window - Assistant - Power Intend Export" for a review.

To verify the created inherited connections on a specific instance open "Edit- Net Expressions - Available properties" and select a block or instance.

If you want to verify the evaluated names from net expressions open "Edit- Net Expressions - Evaluated Names." In case you want to review which instances are connected to a PG net, use the Search assistant to search for a net and check the User properties.

Kind Regards,

Andreas Lenz

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

paragb — Wed, 16 May 2012 15:00:00 GMT

The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react to a Pcell, but Pcell code should not react to, interact with, or be dependent on an environment. Although it is possible to create Pcells dependent on something in your current or local environment, and/or using unsupported or un-recommended functions, Pcell code is likely to fail when you try to translate it for a different environment.

Functions that are not supported for use within SKILL pcells usually belong to specific applications (tools); they are unknown to other environments, to other tools, and to data translators. For example, if you create a Pcell in the Virtuoso environment and include place-and-route functions, the Pcell will fail in the layout environment. Also, application-specific functions that are not supported for customer use can disappear or change, without notice.

Why you should create a Pcell? Creating Pcells for the ECO sometimes helps when we are not sure what size of cell we will have to use for fixing timing violations. Then, just changing a parameter in the Pcell may do the trick. Generally, you can identify them by their prefixes. However, you can also use all of the basic SKILL language functions. In the following example, we will demonstrate how you can insert the buffer during hold time fix (as part of the ECO) flow using Pcell:

1. At the Linux prompt set the following environment variables:

setenv CDS_ENABLE_EXP_PCELL true

setenv CDS_EXP_PCELL_DIR ./.expressPcells

2. Invoke Virtuoso and open the design. Note that for Virtuoso versions before IC6.1.4.500.1, VLS-XL or VLS-GXL is required to save the express PCell cache. In IC6.1.4.500.1 and later versions, all Virtuoso products support this.

3. Select Tools->Express Pcell Manager. Fill out all the details and Enable Caching of the Pcells check box with Auto Save option. Press Save Copy to save the Pcell Layout Cache. This step is necessary to enable inter-operation of the data between Encounter and Virtuoso.

4. Open the design using

Library Manager -> <Library name> <Cell name> <view name>

5. Zoom and select the flip-flop (FF1), in front of which the Pcell has to be inserted.

6. To placed the Pcell go to create -> Instance -> Library:pcell cell:pcell view:layout and placed the instance (I1) to a specific location (x1, y1) in between the flip-flop (FF1) and previous Instance (I2).

7. To do the connectivity

Select I2 instance->connectivity->net->propagate-> A: I2 Y: net1

Select I1 instance->connectivity->net->propagate-> A: net1 Y: net2

Select FF1 Instance->connectivity->net->propagate->D: net2

8. Press Save copy to save the design to OA and exit Virtuoso.

9. To do ECO routing in the Encounter Digital Implementation System (EDIS), make sure the same environment variables of step 1 is set before invoking the tool.

10. Before restoring the OA design database, update the config file with the Pcell library as below:

set rda_Input(ui_timelib,max) ./lib/max/spcbuf_wc.lib"

set rda_Input(ui_timelib,min) ./lib/min/spcbuf_bc.lib"

11. Within EDI, follow these steps to restore the OA design.

restoreOaDesign <Library name> <cell name> <view name>

The design, including the Pcells, should now be read in properly. If the Pcells still do not appear correctly, remove the ./.expressPcells directory and repeat steps 1-4 above. This will make sure new Pcell abstracts are created.

Note: In IC6.1.4 onwards, the cache saved is in a different format than what is saved by IC6.1.3. IC614 can read the Express PCell Cache created by IC6.1.3 and IC6.1.4, but IC6.1.3 cannot read the Express PCell Cache created by IC6.1.4. If you have made a cache using IC6.1.4 then make sure the LD_LIBRARY_PATH environment variable points to <IC6.1.4>/tools/lib while using EDIS. For example:

setenv LD_LIBRARY_PATH <IC6.1.4>/tools/lib

If the cache was made by IC6.1.3 then the LD_LIBRARY_PATH variable can be set to the tools/lib directory under your IC6.1.3 installation.

12. Finally, take the following steps to do the hold time fixing and save the design into OA database:

ecoRoute

timeDesign -postRoute -hold

saveOaDesign <Library name> <cell name> <view name1>

Parag Bhatnagar

What is Digitally Assisted Analog Design?

QiWang — Mon, 30 Apr 2012 23:47:00 GMT

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels.

Unfortunately, compared with the advancement of digital designs over the past decade, the state of art analog design is significantly lagging behind. For example, the throughput of microprocessors doubles every 1.5 years while it takes three times longer to achieve the same advancement for analog designs. Another big roadblock for analog designs is the power consumption. According to Boris Murmann, professor at Stanford University, the equivalent digital gate count in terms of power consumption for a 10-bit ADC at 0.13 um is about 100K, and this number grows almost exponentially for larger ADC and modern advanced nodes.

A new circuit design technique, digitally assisted analog (DAA), delivers a promising solution to address the performance and power challenges to further expand the scope of analog designs to meet today's application requirements. Let's use a simple ADC to explain the concept of DAA:

Figure 1 shows a conventional ADC and Figure 2 shows a DAA style ADC. In Figure 2 a conventional, high performance, power consuming ADC is replaced by a very simple, low-power ADC, followed by a digital post-processor to apply corrections to the output to achieve the same accuracy as the conventional ADC. Compared to the conventional ADC, the DAA ADC has a significant benefit in terms of power and area.

In addition, DAA style designs are easier to port to advanced nodes since majority of the computation task will be performed by the digital post-processor which typically demonstrates an even larger advantage in power, performance and area (PPA) at advanced nodes. With the increasingly wide usage of embedded processors, such as the ARM Cortex-M series, designers can achieve additional benefits in terms of productivity and flexibility thanks to the great software capability of such processors.

The above example just illustrates one specific approach for DAA circuits. In general, in DAA circuits, the assisting digital logic is used to monitor analog performance through the different stages of the operation and to adjust parameters of the analog circuits (such as bias, resistance, capacitance) through calibration loops to meet overall design objectives.

We have seen significant advancements of DAA designs in recent years from the design community, and its proliferation signifies a new era of mixed-signal design. By replacing more and more analog circuitry with digital counterparts to achieve the ever more aggressive PPA targets, we foresee an explosion of new mixed-signal design starts. As a result, the industry is demanding a true mixed-signal design methodology for design, verification and implementation to meet the requirements of such design styles. In the follow-up blogs, we will talk more about how the Cadence mixed-signal solution is best positioned to meet such new mixed-sign design challenges and how you can learn more by joining us at DAC.

Qi Wang

CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Verification

AElzeftawi — Mon, 09 Apr 2012 13:00:00 GMT

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification, characterized by performance and accuracy tradeoffs -- thus making AMS verification the biggest challenge facing verification engineers today.

Lack of consistent handoff between analog and digital design boundaries and the inexistence of mature verification methodologies for mixed signal verification have been common reasons for chip re-spins. As AMS verification matures, so do the methodologies that support AMS verification which now include low-power, behavioral modeling abstraction, assertions, and metric driven verification methodologies.

I had the pleasure of meeting lots of customers during CDNLive! Silicon Valley 2012 and learned firsthand about their verification challenges and the approaches they're taking to address such challenges. Ken Luo from LSI Corporation delivered a presentation about real number model (RNM) development and application in mixed-signal SoC verification. Luo iterated that exploding operating modes, functionality demands for digital control, and calibration to mitigate against process variations are typical trends in modern SoC designs.

As such, analog simulation performance and convergence are bottlenecks for full chip verification. Luo discussed the benefits of adopting RNM, which include the continuous value and discrete time nature of real numbers that allow for pure digital solver simulation and high speed performance. Also, Luo highlighted other features like multiple drivers and resolution function support for RNM, discipline association, and ease of connecting real to electrical nets using R2E/E2R connect modules.

Luo also shared some guidelines for RNM modeling regarding signal flow modeling (voltage vs. current), sampling approaches (uniform vs. non-uniform sampling) which are required to balance performance and accuracy, and modeling data processing algebraic equations vs. nonlinear table models. One of the key takeaways of the presentation is to "model what you need and not what you can" to reflect the specified functionality and avoid unnecessary high order effects. Another takeaway is to align the model development plan with the design development plan, maintain consistent interfaces for model/design, and to use version control to keep the model/design in sync.

Also, Luo discussed that models should be classified according to the block characteristics and verification requirements. Communication I/Os that toggle frequently and have low accuracy requirements can be modeled using Verilog, while high accuracy and frequently toggling nodes like clocks, oscillators, and high bandwidth amplifiers or high accuracy, less frequently toggling nodes like reference voltage/current and, low speed high resolution ADC/DAC, should be modeled using Verilog-AMS/Wreal.

Luo introduced an LSI application, which is a hard disk drive (HDD) PreAmplifier that performs small signal amplification (during READ operation) and voltage waveform shaping (during WRITE operation) interfaces to the HDD R/W heads. The PreAmp has been historically an analog ASIC, but today it has became a complex mixed-signal SoC due to > 4.0 Gbps high data rate requirements, multiple operation modes, programmability of bias/threshold control and calibration. The increased feature complexity poses a challenge to AMS verification due to extremely long simulation times, D/A interface coverage and lack of coverage measurement.

The LSI verification team used Cadence verification planning (vPlan) to collect and define model feature requirements and align verification milestones. Also, the team developed analog mixed-signal Universal Verification Components (UVC) and checkers for analog signals for amplitude, frequency, common mode voltage and sampling frequency. The team observed significant improvements (~600x) using the RNM models over SPICE simulations, which suffered convergence issues and didn't provide adequate coverage. The RNM models achieved 95% accuracy, enabled full coverage, and achieved first silicon success with zero functional bugs.

AMS verification engineers need access to a strong design environment that bridges the productivity gap between analog and digital verification flows. The Virtuoso environment empowered by AMS Designer verification technology is well equipped to resolve the inconsistent handoff between analog and digital design boundaries. RNM makes it possible to apply advanced digital verification methodologies to mixed-signal SoCs and enhance traditional AMS verification.

If you need further information on the presentation, please do not hesitate to contact me at ahmedelz@cadence.com

Ahmed Elzeftawi

DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups

PrabalB — Fri, 30 Mar 2012 20:50:00 GMT

On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference to extend SystemVerilog to support a real data type in coverpoint objects in order to facilitate mixed-signal verification for functional coverage. The paper, titled “Bringing Continuous Domain into SystemVerilog Covergroups,” reflected a year-long effort between Cadence R&D and Scott Little of Freescale (Scott moved to Intel just before we submitted our work to DVCon) that culminated in a prototype of SystemVerilog real coverage in action. We wanted to share this development with the digital verification community that usually represents the majority of DVCon crowd.

After providing a brief refresher on functional coverage basics, the paper went on to ask: “How do analog effects get captured in functional coverage while performing system level verification?” Since analog effects are described in form of floating point numbers, it becomes apparent that to meet the needs of mixed-signal in functional coverage, the language needs to support a floating point (aka real) data type. Since SystemVerilog is widely used in verification, we developed our proposal around the P1800-2009 standard of SystemVerilog.

The paper then went into the detailed mechanics of real typed SystemVerilog coverpoint objects. It highlighted an important extension to the language, specifically an instance-specific covergroup option called range_precision, to divide a range of vector bins into sub-ranges. It also explained how the existing features of SystemVerilog covergroup can be modified or extended with the introduction of real data type. Finally, the paper explored some of the challenges that are still open in the areas of floating point arithmetic and issues related to overflow and underflow. It drew a conclusion stating that our next step would be to complete an analysis of the Functional Coverage Section of the P1800 SystemVerilog Language Reference Manual (P1800-2012) and then work with the SV-EC sub-committee members for standardization of our proposal.

The audience was primarily filled with users from the digital verification community, and therefore there was a lot of curiosity in hearing a presentation coming from someone more oriented to the analog and mixed-signal world. An engineer from Dialog Semiconductor expressed strong interest in our work and stated that she found immediate use of this approach in her group’s verification initiatives. There was a concern raised by one member of the audience who wondered whether we’re trying to make the language more complex. We explained that the we were only proposing extensions that fill the gap between the existing integral type support to the desired level of real data type support.

There were some very good suggestions provided as part of audience feedback, such as consideration of logarithmic ranges and also support for the real data type for transition bins.Overall it was a very enriching experience for me and my colleagues to share our work with a community of folks who are certainly showing signs of interest to extend standard verification techniques to the wonderful world of analog. If you need further information on the presentation, please do not hesitate to contact me at prabal@cadence.com.

Prabal Bhattacharya

Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

QiWang — Wed, 07 Mar 2012 21:29:00 GMT

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area stands out is mixed-signal design. There are more than 10 presentations with specific focuses on mixed-signal design challenges, and how Cadence tools and flows were used to solve those challenges. Here is a list of related papers in different categories with a list of keywords to highlight the technical contents:

Mixed-signal verification

Real Number Model (RNM) Model Development and Application in Mixed-Signal SOC Verification by LSI on Tuesday
- Real number modeling/wReal, mixed-signal SoC simulation, metric driven verification
AMS Simulation of full duplex USB interface using strength modeled Connect Modules by Texas Instruments on Tuesday
- Mixed-signal SoC simulation, strength modeling, custom connect modules
SPEF/DSPF Parasitic Stitching in Post-Layout Analog and Mixed-Signal Simulation by Cadence on Wednesday
- AMS simulation, parasitic extraction, Spice/Fast-spice
An Efficient Phase-Locked Loop Noise Simulation Using APS & ViVA by Nvidia on Wednesday
- PLL simulation, Jitter/noise analysis, Virtuoso® Power System (VPS)
Verilog-AMS Verification of ADC Soft IP cores by Missing Link Electronics on Wednesday
- AMS simulation, Verilog-AMS, Spice
High Performance, Interoperable Real Number Models for Mixed-Signal Verification by Silicon Labs on Wednesday
- Real number modeling/wReal, mixed-signal SoC simulation, metric driven verification, Virtuoso ADE

Mixed-signal implementation

IC 61 and EDI 10.1 Inter-Operability Flow, Features and Benefits by Maxim Integrated Products on Tuesday
- Open Access/OA, unified analog/digital database, analog/digital interoperability, Encounter® Power System (EPS)
Case Study of Complex High-Speed Mixed-Signal Chip Integration at 40nm by Intersil on Tuesday
- Analog/digital interoperability, digital-on-top methodology
Substrate Noise Analysis and Wide Metal Extraction for Power MOS embedded LSIs by Renesas on Wednesday
- Substrate noise analysis (SNA), wide-metal extraction, QRC

Ecosystem and technology partners

GLOBALFOUNDRIES 28nm Analog & Mixed Signal Production Ready Flow by Global Foundries on Tuesday
- AMS reference flow, 28nm, advanced nodes
AMS Reference Flows for Advanced TSMC CMOS Processes by TSMC on Wednesday
- AMS reference flow, 28nm, advanced nodes, silicon stress, yield
From 6 Days to 6 Minutes: Accelerating Mixed-Signal Design Verification by Orora Design Technologies on Wednesday
- Advanced node, PVT and process variations, mixed-signal SoC simulation, AMS IP integration

What's Hot/What's Cool

A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP by Rambus on Tuesday
- Power gating, low power mixed-signal designs, CPF, Conformal® Low Power (CLP)
Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification by Cadence on Wednesday
- Power aware AMS simulation, CPF, power smart connect modules, CPF generation from Virtuoso Schematic Editor (VSE)

Of course, do not miss the keynote speeches given by executives from ARM, TSMC and Cadence. Go to CDNLive! SV 2012 for more information. See you there next week!

Qi Wang

Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

QiWang — Tue, 28 Feb 2012 14:22:00 GMT

The China Annual Creativity in Electronics (ACE) Awards was established to recognize individuals, companies and technologies that have made profound impacts in the overall China electronics industry each year. Joining with the industry prestigious names like ARM and TI, Cadence Virtuoso AMS Designer won the 2012 Best EDA product award. Five candidates were nominated for this award including Cadence. The award was presented to Cadence at the 17^th IIC China Conference in Shenzhen on Feb. 23, 2012.

AMS Designer is a mixed-signal simulation tool for the design and verification of analog, RF, memory, and mixed-signal SoCs. It is recognized as the most mature mixed-signal simulation tool by the fast-growing electronic designer community around the world. However, that is not the main reason for winning this award. As stated by the mission of this award, AMS Designer was selected as the winner for its recent innovations in areas like wreal (real number) modeling, simulation support for SoC mixed-signal verification, and power aware simulation for mixed-signal designs with power management features. AMS Designer has demonstrated productivity gains and additional verification capabilities in product design.

Congratulations to the Cadence China Team and the AMS Designer team!

Qi Wang

Behavioral Model Validation with amsDmv

xiuya — Thu, 01 Dec 2011 02:00:00 GMT

amsDmv (Analog Mixed Signal Design and Model Validation) is an application integrated in the Cadence Virtuoso GUI flow and it can also be invoked from command line with some feature limitations. amsDmv can be used to compare the simulation restults and design interface (pins) from the DUT with those from the reference design. Therefore users can use amsDmv to validate behavioral models with original transistor level models, and to make sure the new model behavior matches the original design. The following problems can be resolved by using amsDmv:

Behavioral models are created and initially validated by the designer against the original transistor level design

The design and the model continues to evolve and change

Designers don’t have time to continually validate models

Issues such as pin list mismatches or behavioral variations can occur

Using the original (out of sync) model could result in errors or worse, incorrect model behavior hiding design flaws

Continual model validation is mandatory during the design creation and model validation process, but this can take time and expertise

amsDmv is mainly targeted at analog/mixed-signal models. To solve the problems described above, the tool must meet some basic requirements. Such as:

1) The validation process must be easy to set up. It should require a minimal threshold for designers to use it, reuse existing testbenches and simulation setups, and be accessible from known working environments such as Virtuoso.

2) The validation process must be fully automated.

amsDmv meets the above requirements and therefore is useful to designers in validation process. amsDmv is not a replacement for accurate modeling or a detailed manual model validation process. It complements the modeling and model validation process by adding a sanity check in regression mode. This sanity check will notify the user if there are potential problems with the model (or the reference).

This integrated model validation solution supports:

Validation of analog and digital waveform signals saved from simulations

Validation of measured values: Gain, power, delay, noise, etc.

Validation of pin/module interfaces of the design and model

It supports a GUI based setup and an exported command line regression run to fulfil these requirements. The run output provides straightforward pass/fail output, reports, and extended debugging capabilities (waveform zoom, etc.).

Manual waveform comparison/debugging in the analog domain often leads to complex and incomplete answers. While this provides useful information for a discussion, it is not useful for a regression based methodology. Therefore, amsDmv provides a very clear pass or fail answer within the validation process. If in doubt, it might be useful to use conservative settings – resulting in tighter tolerances. This will give the analog designer the opportunity to double check questionable validation results.

The amsDmv tool flow looks like the following:

It is the user’s responsibility to provide the design, the model, a testbench and a simulation setup – such as an ADE state. In most cases this information should already be available.

amsDmv will perform the simulation for the reference and compare setup. This results in two sets of waveforms and measured results data. All of this data will be processed in the validation engine using user defined tolerances. The final result is a pass/fail output and additional data for debugging, such as reports and log files.

The interface check is not based on simulation data but works directly on the provided design (DUT) and model data.

As you might have noticed, the validation process for waveforms and measured results is independent of the simulation and the input data. This enables amsDmv to operate completely independent of the modeling language being used. You can use Verilog-AMS, VHDL AMS, SystemC, or any other language in addition to wreal models. It also provides you the flexibility to not only carry out design versus model (bottom-up) checking but also model vs. design (top-down), model versus model, design versus design, simulator version A versus simulator version B checking.

amsDmv provides an easy to use model validation environment with a GUI based setup and a command line script export for regression run. The output is straightforward pass/fail information. In addition a lot of detailed information is provided in the GUI and in the report files on the command line to help the user debug potential problems.

The validations include analog and digital waveform signals, measured results, and pin/module design/model interface checks.

amsDmv was released in the IC614 stream, however, it can be used together with IC 5.1.41 (set up special env variables and pointing to amsDmv installation in IC614) and on the command line (some features may not be available, see our detailed documentation and tutorials).

amsDmv can be started from the Virtuoso CIW window, as shown below.

The following is amsDmv GUI, where users can set up DUT and reference design simulations, measurements, start simulations, compare waveforms,measurement results and pin definitions, also can see final report (pass/fail).

In the shown waveform tab, user can specify relative/absolute tolerance,debug failing areas, using ViVA or SimVision. v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} p\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} v\:textbox {display:none;} By default SimVision is used for waveform viewing when any digital waveform signals are loaded. Wavescan/Viva are the default when only analog waveform signals are found. .The preferred waveform viewer can be selected in the Preferences dialog.

There are some advanced features available in recent release, including preload filter for large waveform database, signal alias for defining equivalent signal names, signal selection tab to narrow down the listed/compared signals, A2D/D2A conversion for comparing the equivalent signals from different domains. Those are new features we developed based on customer feedback and these new features further improved the usability of amsDmv.

Xiuya Li

Fred Discovers 1000x-10000x Speedup Using wreal Models

Paul Foster — Wed, 02 Nov 2011 01:00:00 GMT

This is the second installment in an ongoing series of blog posts that includes an email conversation between Fred and Harry, two fictional mixed-signal engineers, about analog behiavoral modeling. You can read the first installment by clicking here. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).

Hi Harry,

As I said, this was really the fun stuff. We are coming into the region of 1000x, 10000x or more speedup over SPICE -- that is what I was looking for. Before I tell you about the detail, it is for sure that this speedup does not come free (you know that I never trust someone who tells me that stuff comes free). We have to leave behind some of the analog behavior details, but that is fine.

OK, back to the beginning: Wreal is doing the magic. As you know, Verilog-D is not capable of using real valued ports. This is what wreal gives you. Wreal is a "wire real" or "real wire" if you want. The fun part is that even though it is a Verilog-AMS LRM construct it only needs the digital kernel for evaluation.

Thus, we are at the digital performance level and the coding style is pretty digital-like, for example:

module vco(vin, clk);
input vin;
wreal vin;
output clk;
reg clk;
real freq,clk_delay;
always @(vin) begin
freq = center_freq + vco_gain*vin;
clk_delay = 1.0/(2*freq);
end
always #(clk_delay) clk = ~clk;
endmodule

It's that simple, you just connect the "vin" to your real net and you have a
nice oscillator.

I asked the Cadence guy why this is coming up now and why people haven't used this before since wreal has been in the Verilog-AMS standard forever.
Interesting answer, he said it is two-fold. One point is that there is more demand for really high speed mixed signal models from the digital teams (they have realized they can't ignore analog anymore -- like us), and secondly, Cadence has implemented some enhancements over the standard that were essential to write good models.

I will get you the details soon.

Stay tuned, Fred

How Fred Discovered Mixed-Signal Behavioral Modeling

Paul Foster — Tue, 01 Nov 2011 03:00:00 GMT

Introduction

This is the first of a series of blogs where we will add pieces to the story over time. This is an email conversation between Fred and Harry, two fictional mixed-signal designers, where Fred is adopting various modeling techniques to realize faster simulations while maintaining acceptable levels of accuracy. (NOTE: This blog post was written by Walter Hartong and uploaded by Paul Foster).

How Fred came to mixed signal behavioral modeling

Hi Harry,
Oh man, tape-out is in five days, and the SPICE level simulation is only at 2.34ns. With today's computers simulator performance is simply too slow, darn Moore's law.
CU Fred

Hi Harry,
I called Cadence and they suggested APS (Virtuoso Accelerated Parallel Simulator). Wow, that made a difference. I can now burn a whole 16-core machine. It should be okay for this project, but we will need something faster moving forward.
Bye, Fred

Hi Harry,
Cadence said to look into modeling and DMS (Digital Mixed-signal) for the next project and finish this one with APS. It seems like a good idea for now.
Wish me luck that I do not find any serious issues over the next few days.
Cheers, Fred

Hi Harry,
We did it. After some long nights, we finished verification just in time before the tape-out. Fancy a beer tonight?
Let's hope the chip works. We did our best but who knows if this was good enough.
See you tonight, Fred

Hi Harry,
We are now on the next project. We need to do things differently this time. We really need to improve the verification coverage and speed up functional verification. There is no way that we can do this the same way as we have done before.

Talked with Cadence again and there will be a seminar tomorrow.
I will keep you posted, Fred

Hi Harry,
Cadence did a presentation on behavioral modeling. Here is my conclusion:
There are various behavioral languages out there and it is critical to pick the right one for our problem. We ruled out all the VHDL flavors, as nobody here knows VHDL.

There is Verilog-A which is a pure analog subset of Verilog-AMS. This is mainly used for detailed analog models for performance type of verification. The language is quite simple but as noted by the Cadence guy, the devil is in the details, and it is not trivial to write a good behavioral model that provides the performance gains I need and also retains the right level of accuracy.

The advantage of the Verilog-A subset is that we can definitely reuse the models in pure analog simulations, like APS, as well as in our mixed signal environment. I will probably go ahead and suggest this language to our analog team, but for me this looks to low level. As said before, I need it really fast!!!

Then there is Verilog-AMS. As the name says, this is a superset of Verilog-A and Verilog-D. This language gives people a huge amount of flexibility. You can create all sorts of interactions between the analog and digital domains, and the simulator figures out in the background which solver to use. Man, this can get quite hairy. There were a few tricky examples in the labs.

One other takeaway point was "model what you need and not what you can." It took me a while to understand this but then the guy gave a few examples of folks creating highly accurate models that would model very tiny details of the analog behavior, while the purpose was only to verify the connectivity. Thus, all the modeling effort and the simulation performance were completely wasted.

Tomorrow should be interesting; we are talking about wreal modeling and Verilog-AMS.

Have a good day,

Fred.