Low Power Blog

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

Adam Sherilog — Tue, 07 May 2013 19:41:00 GMT

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release. Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release.

When we talk about low-power verification its easy to equate it with simulation. For certain, simulation is the heart of a low-power verification solution. Simulation enables engineers to run their design in the context of power intent. The challenge is that a simulation-only approach is inadequate. For example, if engineers could achieve SoC quality by verifying the individual function of each power control module (PCM), then simulation could be enough. For a single power domain, simulation can be enough.

However, when the SoC has multiple power domains -- and we have seen SoCs with hundreds of them -- engineers have to check the PCMs and all of the arcs between the power modes. These SoCs often synchronize some of the domain switching to reduce overall complexity, creating the potential for signal skew errors on the control signals for the connected domains. Managing these complexities requires verification methodologies including advanced debug, verification planning, assertion-based verification, Universal Verification Methodology - Low Power (UVM-LP), and more (see Figure 1).

Figure 1: Comprehensive Low-Power Verification

But even advanced verification methodologies on top of simulation aren't enough. For example, the state machine that defines the legal and illegal power mode transitions is often written in software. The speed and capacity of the Palladium emulation platform is ideal to verify in this context, and it is integrated with simulation sharing debug, UVM acceleration, and static checks for low-power. And, it reports verification progress into a holistic plan for the SoC. Another example is the ability to compare the design in the implementation flow with the design running in simulation to make sure that what we verify is what we intend to build.

Taken together, verification across multiple engines provides the comprehensive low-power verification needed for today's advanced node SoCs. That's the heart of this low-power verification announcement.

Another point you may have noticed is the extension of the Common Power Format (CPF) based power-aware support in the Incisive Enterprise Simulator to IEEE 1801. We chose to bring IEEE 1801 to simulation first because users like you sometimes need to mix vendors for regression flows. Over time, Cadence will extend the low-power capabilities throughout its product suite to IEEE 1801.

If you are using CPF today, you already have the best low-power solution. The evidence is clear: the upcoming IEEE 1801-2013 update includes many of the CPF features contributed to 1801/UPF to enable methodology convergence. Since you already have those features in the CPF flow, any migration before you have a mature IEEE 1801-2013 tool flow would reduce the functionality you have today.

If you are using Unified Power Format (UPF) 1.0 today, you want to start planning your move toward the IEEE 1801-2013 standard. A good first step would be to move to the IEEE 1801-2009 standard. It fills holes in the earlier UPF 1.0 definition. While it does lack key features in -2013, it is an improvement that will make the migration to -2013 easier. The Incisive 13.1 release will run both UPF 1.0 and IEEE 1801-2009 power intent today.

Over the next few weeks you'll see more technical blogs about the low-power capabilities coming in the Incisive 13.1 release. You can also join us on June 19 for a webinar that will introduce those capabilities using the reference design supplied with the Incisive Enterprise Simulator release.

=Adam "The Jouler" Sherer

(Yes, "Sherilog" is still here. :-) )

Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?

Pete Hardee — Tue, 12 Feb 2013 16:00:00 GMT

I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here. In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired by Horst Diewald, chief architect of MSP430^TM microcontrollers at Texas Instruments, the group's line-up is an impressive "who's who" of the microcontroller space, including Analog Devices, ARM, Atmel, Cypress, Energy Micro, Freescale, Fujitsu, Microchip, Renesas, Silicon Labs, STMicro, and TI.

As the press release explains, unlike usual processor benchmark suites which focus on performance, the ULP benchmark will focus on measuring the energy consumed by microcontrollers running various computational workloads over an extended time period. The benchmarking methodology will allow the microcontrollers to enter into their idle or sleep modes during the majority of time when they are not executing code, thereby simulating a real-world environment where products must support battery life measured in months, years, and even decades.

Processor performance benchmarks seem to be as widely criticized as EPA fuel consumption figures for cars - and the criticism is somewhat related. There is a suspicion that manufacturers can tune the performance for better test results, rather than better real-world performance. On the face of it, the task to produce meaningful ultra low power benchmarks seems even more fraught with difficulties. For a start, there is a vast range of possible energy profiles - different ways that computing is spread over time - and a plethora of low power design techniques available to optimize the system for the set of profiles that particular embedded system is likely to experience. Furthermore, you could argue that, compared with performance in a computer system, energy consumption in an ultra low power embedded system has less to do with the controller itself and more to do with other parts of the system like the memories and mixed-signal real-world interfaces.

EEMBC cites that common methods to gauge energy efficiency are lacking in growth applications such as portable medical devices, security systems, building automation, smart metering, and also applications using energy harvesting devices. At Cadence, we are seeing huge growth in these areas which, along with intelligence being introduced into all kinds of previously "dumb" appliances, is becoming known as the "Internet of Things." Despite the difficulties, with which the parties involved are all deeply familiar, I applaud this initiative. While it may be difficult to get to apples-to-apples comparisons for energy consumption in these applications, most of the time today we don't even know where the grocery store is. If the EEMBC effort at least gets us to the produce department, we're going to be better off.

Pete Hardee

New Rapid Adoption Kit (RAK) Enables Productive Mixed-Signal, Low Power Structural Verification

SumeetAggarwal — Mon, 10 Dec 2012 16:32:00 GMT

All engineers can enhance their mixed-signal low-power structural verification productivity by learning while doing with a PIEA RAK (Power Intent Export Assistant Rapid Adoption Kit). They can verify the mixed-signal chip by a generating macromodel for their analog block automatically, and run it through Conformal Low Power (CLP) to perform a low power structural check.

The power structure integrity of a mixed-signal, low-power block is verified via Conformal Low Power integrated into the Virtuoso Schematic Editor Power Intent Export Assistant (VSE-PIEA). Here is the flow.

Applying the flow iteratively from lower to higher levels can verify the power structure.

Cadence customers can learn more in a Rapid Adoption Kit (RAK) titled IC 6.1.5 Virtuoso Schematic Editor XL PIEA, Conformal Low Power: Mixed-Signal Low Power Structural Verification.

To read the overview presentation, click on following link: PIEA Overview
To download this PIEA RAK click on following link: PIEA RAK Download

The RAK includes Rapid Adoption Kit with demo design (instructions are provided on how to setup the user environment). It Introduces the Power Intent Export Assistant (PIEA) feature that has been implemented in the Virtuoso IC615 release. The power intent extracted is then verified by calling Conformal Low Power (CLP) inside the Virtuoso environment.

Last Update: 11/15/2012.
Validated with IC 6.1.5 and CLP 11.1

The RAK uses a sample test case to go through PIEA + CLP flow as follows:

Setup for PIEA
Perform power intent extraction
CPF Import: It is recommended to Import macro CPF, as oppose to designing CPF for sub-blocks. If you choose to import design CPF files please make sure the design CPF file has power domain information for all the top level boundary ports
Generate macro CPF and design CPF
Perform low power verification by running CLP

It is also recommended to go through older RAKs as prerequisites.

Conformal Low Power, RTL Compiler and Incisive: Low Power Verification for Beginners
Conformal Low Power: CPF Macro Models
Conformal Low Power and RTL Compiler: Low Power Verification for Advanced Users

To access all these RAKs, visit our RAK Home Page to access Synthesis, Test and Verification flow

Note: To access above docs, use your Cadence credentials to logon to the Cadence Online Support (COS) web site. Cadence Online Support website http://support.cadence.com/ is your 24/7 partner for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you can receive new solutions, Application Notes (Technical Papers), Videos, Manuals, and more.

You can send us your feedback by adding a comment below or using the feedback box on Cadence Online Support.

Sumeet Aggarwal

Low-Power Technology Summit Proceedings Now Available

Pete Hardee — Thu, 06 Dec 2012 00:09:00 GMT

On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit Proceedings archive, which just went live.

We've put both video and PDF versions of the presentations there. Obviously the PDFs give you the quickest access to the material, but you'd be missing a lot to just grab those. Seeing and hearing the presenter in action is important, especially when one of the keynotes, entitled "The power wall - are we scaling it or is it just getting higher?", is delivered by a noted expert like Professor Jan Rabaey of the University of California at Berkeley. The videos also have the Q&A sessions at the end of each presentation -- there were lots of good questions, and good interaction. You do need a "Cadence Community" login to access those, so there will be a quick one-time registration for the login if you don't already have it.

Prof. Jan Rabaey presents at the Low Power Technology Summit

As well as the keynote from Professor Rabaey (which Richard Goering also covered in a blog here), there were also presentations from Sathya Subramanian of ARM on Low-Power Design with ARM® Physical IP and POP^TM IP, and technical updates from the Cadence team.

My personal highlight from the day was the presentation by Anis Jarrar of Freescale. Anis talked about all the measures they took to meet the aggressive power specifications on the Kinetis family of chips. Kinetis has been highly successful for Freescale, and they really are using all the tricks in the book (and then a few that aren't) to minimize power on these designs. You can also find more about Kinetis here. As well as the usual techniques (clock-gating, multi-Vt, Multi-Supply Voltage, Power Shut-off) they were also an early user of multi-bit register mapping in RTL Compiler. Further, they found a novel way to apply body bias that avoided the need for that inefficient, tricky way to generate a negative bias supply -- the charge pump. The audience was very happy to learn more about Anis's experiences, and the Q&A session for this one was lively and informative.

Finally, the presenters were joined by representatives of Broadcom and Berkeley Wireless Research Center for a panel session moderated by Richard Goering. Panelists provided a great low-power design-related discussion. You can also read Richard's blog on that, for a summary.

Enjoy!

Pete Hardee

Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS

Pete Hardee — Thu, 29 Nov 2012 16:30:00 GMT

The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises.

First, some of the expected stuff. We'd noticed in the last major surveys done almost two years ago (see the Perspective on Power blog from December 2010) that advanced low-power design techniques were starting to be applied outside of mobile (battery-operated) devices, and this trend has increased. 49% of the attendees surveyed worked on non-mobile end-applications. As in 2010, very nearly 100% were already using basic low-power techniques like clock gating and multi-Vt optimization. But the people using advanced techniques "currently" increased from 60% to 70% (see figure below).

As before, we define advanced low power techniques as the ones that apply to power domains - splitting the design into separately-powered areas where the voltage can be shut off to reduce leakage (Power Shut-Off - PSO, aka State Retention Power Gating - SRPG) or supplied with different voltage levels (permanently in the case of Multi-Supply Voltage - MSV, or dynamically in the case of Dynamic Voltage and Frequency Scaling - DVFS).

As in 2010, PSO was the most popular of the advanced techniques, followed by MSV, then DVFS. What was less expected was that, in contrast to 2010 where the "future" use of advanced techniques increased all of them proportionately, in the 2012 results, the designers surveyed were expecting to use a lot more DVFS in their next designs, pushing it into second place in front of MSV.

So why might DVFS become more popular than MSV? Both use different supply voltages for domains that have different performance needs. The difference is that DVFS allows the voltage level, or more usually a combination of voltage and clock speed, to be selected on the fly based on current performance demand. It is therefore a more complex technique to implement and verify, meaning that the designer has to achieve sign-off for power domain to which it applies at multiple modes and corners.

Also, opportunities to apply MSV may have already been fully exploited and designers are looking for more. Recently, design tools such as the Cadence Encounter RTL-to-GDSII flow support design closure for multi-mode multi-corner (MMMC) simulations, which is an important enabler for an increase in the use of DVFS on the next generation of designs.

Pete Hardee

Packed House Expected for Cadence Low-Power Technology Summit

Pete Hardee — Tue, 16 Oct 2012 17:28:00 GMT

It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full agenda covering multiple aspects of low-power design.

No longer the sole preserve of designers needing to extend battery life, low-power design has become ubiquitous in many different applications from mobile devices to datacenters. We have recently seen a bifurcation in the needs of our customers --- on the one hand, for power optimization in high-performance digital design, and on the other hand, ultra-low-power design techniques in a myriad of smaller, lower performance but none-the-less challenging mixed-signal devices. There will be technology updates from Cadence focusing in each of these areas. We also expect the audience to be given plenty to think about from our keynote speaker, Professor Jan Rabaey, of U.C. Berkeley. I just wanted to highlight a few of my favorites that I'm really looking forward to from the agenda.

Keynote speech by Professor Jan Rabaey - see Richard Goering's blog from a couple of weeks ago for more information on Professor Rabaey
Sathya Subramanian of ARM will talk about low-power support in ARM's physical libraries, memories, and also optimization of processor implementation with POP^TM IP and ARM-Cadence collaboration on design flows
Anis Jarrar of Freescale will talk about low-power design experiences on the latest Kinetis series of ARM Cortex®M-powered mixed-signal chips
Panel discussion moderated by Richard Goering with interesting diverse and experienced panelists:
- Sathya Subramanian of ARM
- Qi Wang of Cadence
- Anis Jarrar of Freescale
- Sushma Honnavara-Prasad of Broadcom
- Gary Kelson of the Berkeley Wireless Research Center

For more details on the agenda, times and logistics, please see the Cadence event page.

See you on Thursday!

Pete Hardee

Your First Low-power Verification Project - Webinar

Adam Sherilog — Thu, 11 Oct 2012 17:00:00 GMT

So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls, isolation, and retention. As a verification engineer, you know that any test could trigger a power change either intentionally or in error. How do you build your environment to verify this first low-power project?

Mickey Rodriguez, Cadence low-power verification product engineer has answers for you. In a webinar on Tuesday October 16 at 9:00 am PDT, Mickey will lead a technical discussion entitled "5 Steps to Your First Power Shutoff (PSO) Verification". The discussion will cover these key topics and utilize the low-power reference implementation in the Incisive Verification Kit provided within with the Incisive Enterprise Simulator:

Explaining PSO concepts including isolation and retention
Checking the power format file for errors using low-power rules in Incisive HAL
Understanding and debugging corruption in Verilog
Identifying typical PSO bugs using SimVsion low-power debug
Leveraging assertions to increase quality and generate low-power verification coverage

So if you are a digital IP designer intersted in knowing how your PSO circuit will be verified, a verification engineer responsible for that verification, or a project manager trying to balance project risk and tighten power-budget requirements, this webinar is for you!

You can sign-up for the webinar here: http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home

=Adam "The Jouler" Sherer, Incisive Product Marketing Director

Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

Pete Hardee — Mon, 17 Sep 2012 13:00:00 GMT

CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far from San Jose, USA; Munich, Germany; and Hsinchu, Taiwan. If you click on those proceedings links, you get to a multitude of different tracks and, for those interested in everything low-power, it can be quite challenging to find all the relevant presentations. So I've saved you the trouble of hunting through by gathering them all here - 12 so far from Cadence customers plus 3 useful presentations from Cadence's own technologists.

Note: you will need to log in with your cadence.com user account to access the papers. If you don't have one, create a Cadence.com User Account now.

A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP
Norman Chan, Rambus
Conformal Low Power - Complex Low Power Design Verification
Sorin Dobre, Qualcomm
CPF in AMS Simulation and Macro IP
Qingyu Lin, Cadence
Low Power Implementation on Freescale Kinetis Family
Anis Jarrar, Freescale Semiconductor
Techtorial: Low Power Failures--What not to Plan
John Decker, Cadence
Low-power Verification using UVM SystemVerilog
John Decker, Cadence
Automation of Switch Insertion and Power Network Generation in 28nm PSO Designs
Shane Stelmach et al, Texas Instruments
Multi Voltage Domain, Multi VT Low power physical implementation with Cadence tool suite
Harald Hopperdietzel & Uwe Ratzmann, Texas Instruments
Power Calculation From Early Estimation to Silicon Correlation
Johannes Bruecker, Renesas Electronics
Implementation of a Flexible, Low Power and High Performance 4G Baseband Processor
Peter Debacker et al, imec
Hierarchical CPF Usage in ST-HED Low Power Flow
Sylvie Pierunek, STMicroelectronics
Early, Functional Unit-Based, Power Estimation for Wireless Baseband Processors
Peter Debacker et al, imec
Challenging Verification for Complex Low-Power Design without Always-Power-On Domain
Zhaohui Hu, ST-Ericsson
Effective GPU platform verification and power estimation solutions with Palladium
Kaowen Liu, MediaTek
Design Closure in 28nm Low-Power Design with EDI
Jurcy Huang, Socle
Huge thanks to all who contributed these presentations!

Pete Hardee

RAK: Conformal Low Power Advanced Features for Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling

SumeetAggarwal — Fri, 10 Aug 2012 15:07:00 GMT

Why do you define macro models? Luke Lang, Engineering Director at Cadence, says that "Just because you have a hard macro doesn't mean you need to define a macro model: A single-domain hard macro without any low power component should be black-boxed. A macro model is not necessary."

Luke further elaborates: "Custom IP blocks and analog macros often contain low-power features. A pure black box makes verification and implementation almost impossible. So, you need macro modeling as it provides the necessary power information to enable verification and implementation." The diagram below depicts Common Power Format (CPF) macro models.

Examples:

Embedded RAM with always-on memory core but with power shutoff (PSO) interfaces.
Analog macro that turns off a portion of the circuit.
Embedded processor that operates with dynamic voltage and frequency scaling (DVFS).

Cadence customers can learn more in a Rapid Adoption Kit (RAK) titled Conformal Low Power and RTL Compiler: Low Power Verification for Advanced Users. The kit includes overviews, tutorials with demo design (instructions are provided on how to set up uthe ser environment) and provides introductions for the advanced features of Conformal Low Power -- including Power Intent Comparison, Hierarchical Integration and CPF Macro Modeling.

Validated with CLP 11.1 and RC 11.1.
Last Update: 07/18/2012.
Skill Level: Intermediate

You can also find a low power (LP) Mixed Verification presentation that talks about:

Overview of LP structural verification
Application of LP structural verification to mixed-signal designs
Generation of CPF macro model

While providing an overview on hierarchical flow and integration, the Cadence Low Power team also shares some confidential tips and techniques on Macro Cell Modelling. There are several "learning-by-doing" labs to cover these advanced features of the Conformal Low Power verification solution. They will surely make you productive and proficient with Cadence tools and technologies.

To download this Advanced CLP RAK, click here. To access all RAKs, visit our RAK Home Page

Note: To access above docs, click a link and use your Cadence credentials to logon to the Cadence Online Support (COS) web site.

Cadence Online Support website http://support.cadence.com/ is your 24/7 partner for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you've likely to notice new solutions, Application Notes (Technical Papers), Videos, Manuals, etc.

You can send us your feedback by adding a comment below or using the feedback box on Cadence Online Support.

Happy Learning!

Sumeet Aggarwal

Mixed Signals from European Low-Power Designers

Pete Hardee — Wed, 25 Jul 2012 21:47:00 GMT

Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it a good time to visit - while it was nice in Germany the Northern European summer has been a disappointment so far, although the two days I spent in Scotland were, I'm told, the first two rain-free days since April.

It was a good time because our customers were keen to get a mid-year update, especially since so few make the trip over to DAC nowadays. And we had plenty of interesting stuff to share. But the value for me is not really the communication of our latest stuff to our customers; it's more listening to what their changing needs are. More than I'd ever experienced before, the needs stem from the confluence of low-power and mixed-signal design challenges.

While much of the semiconductor industry globally seems preoccupied with digital design in advanced nodes like 28nm, and starting to think about 20nm and beyond, you can practically count the companies in Europe involved with such designs on the fingers of one hand. However, if I try to count the companies involved with mixed-signal designs, combined with the need to meet stringent power specifications, I fast run out of digits.

The European chip design scene is all about mixed-signal and low-power in a wide range of mobile, automotive, industrial and medical applications. While designs tend to be implemented in less advanced process nodes - in companies I visited many new designs are moving to the 65nm node and designs at 90nm, 130nm and even 180nm are still commonplace - the designs are every bit as challenging. The challenges are just different. In the pure digital world, unless you've been living under a rock for the past couple of decades, you probably know that CMOS process technology has been able to follow Moore's Law - the approximate doubling of transistor count every two years. Try doing that with RF devices, passives, power management components, MEMS, or in short, all of those components you need to interface with the (analog) real world. Fabs specializing in mixed-signal technologies have recently coined the phrase "More than Moore" to describe this challenge.

Power-wise, these mixed-signal designs are no less challenging. Medical devices and smart card applications in particular have pushed back the state-of-the-art in ultra-low-power design. Power specifications in the automotive world have become tighter and tighter as the rapidly-growing electronics content adds up to significant power demand, and power densities are strictly controlled to avoid temperature-related reliability issues in an already pretty hostile environment.

Depending on the application, and given the process nodes in use, most emphasis so far has been on reduction of dynamic power. Aggressive techniques including multi-supply voltages, and dynamic voltage and frequency scaling are commonplace. But with the move to 65nm and beyond, and especially if the application involves extended idle periods, controlling leakage is becoming more important and power gating is starting to be more widely deployed. While the complexity of power architectures may not seem to be as great as the latest mobile multimedia platform, nonetheless it's introducing multiple power domains and multiple power modes on top of the existing complexities of mixed signal design.

This is critical, especially since verification complexity increases exponentially with complexity of the power architecture, and mixed-signal verification is already considerably more challenging than digital verification. Why? Continuous waveforms simulate slower than discrete, and techniques from the digital world like formal verification and hardware acceleration are almost impossible to apply, if the conventional mixed-signal verification methodology continues.

So, many customers were interested in recent developments at Cadence that bring our mixed-signal and low-power solutions closer together. This inlcudes capabilities like power-aware mixed signal simulation with real number modeling (i.e. wreal). Here, signals crossing the analog and digital domains are not just modeled abstractly for speed, but electrical-to-logical and logical-to-electrical conversion is power-aware, meaning all the logic states and their equivalent voltages are derived automatically from the Common Power Format (CPF) file. Also important is the ability to generate CPF from the analog circuitry in the Virtuoso schematic view, which makes a block that would be functionally a "black box" in digital formal verification tools like Conformal Low Power, look like a "white box" from the power intent point of view, enabling rigorous chip-level functional and structural checks of the integrated design's power intent. Mixed-signal and low-power design challenges seem daunting enough individually, but we're really starting to see what happens when they coincide. And hopefully, we're doing something useful about it.

Pete Hardee