Low Power Blog

Low-Power Design? Brian Bailey Gets It

Pete Hardee — Wed, 02 May 2012 20:23:00 GMT

Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he put it: "I doubt if the EDA Designline, or in fact any Designline in the history of EE Times has ever had anything close to the concentration of design articles, opinions, book excerpts that I will be putting up this month - and all of them will be on the subject of power." And I agree.

Contributions have come predominantly from EDA, and from pretty much all the players with any kind of power analysis, verification or optimization offering. There's good stuff from a lot of different companies, but since this is a Cadence blog, I make no apologies for highlighting the Cadence content here.

In his opinion piece What Comes After Power Formats, Qi Wang elaborates on future developments we may see after the current focus on design automation for today's advanced low-power techniques. He touches on system level and software, novel clock tree methods, mixed-signal designs especially digitally-assisted analog, future process technologies, and 3D-IC.
Next up, Buda Leung and I wrote a detailed case study of power analysis in Building predictability into your low-power design flow. We looked at the power savings achieved with multi-supply voltage domains, power shut-off, and multi-voltage threshold techniques, showing that RTL power estimation gets you early feedback on the benefit of these techniques, and could get pretty good correlation to sign-off analysis provided you use realistic activity vectors. We deservedly credited Paul Weil, John Decker and Mickey Rodriguez for the design work they did that made the article possible.
Another major design article came from Luke Lang, who contributed Hierarchical methods for power intent specification. This article takes a comprehensive look at power intent specification for hierarchical designs, giving an in-depth "how to" on both top-down and bottom-up techniques, and pointing out that real-world design of any complexity is invariably a combination of both. Somewhere in the EDA Designline series, you can find an article on hierarchy management in UPF. Compare the two, and see which one makes more sense to you for real design. Maybe you will see why we're putting a lot of effort into driving methodology convergence with IEEE 1801 with broad industry backing, which is more fully explained in another EE Times article, co-written by ARM, Cadence, Qualcomm and TI, called Power Intent Formats: Light at the End of the Tunnel?
In Brian's editorial Power 107: Power Delivery Networks, Brad Griffin is quoted extolling the benefits of full chip-package-board PDN modeling solutions.
Finally, in Brian's latest editorial Power 108: Powering forward, I make some future predictions for 3 years and 10 years out. It's always difficult to know how far out on a limb to go on that kind of question, but all I ask is that, before you ridicule my predictions, let's see yours! However, I did note with a chuckle that, out of a list of 7 items predicted by a competitor for 10 years out, I believe Cadence customers already benefit today from 6 of them, with the remaining one on the roadmap slated for a release considerably sooner than a decade! Brian quite rightly pointed out that, 10 years out, you have to think a little outside the box.

Pete Hardee

Where There's Smoke, There's fire in the Belly of an Aspiring Engineer

Adam Sherilog — Mon, 02 Apr 2012 12:40:00 GMT

Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current generation? Have apps deadened the EE in the way video killed the radio star? I am happy to report that the answer, for one future EEs at least, is a resounding "power up!"

For some strange reason, my oldest son thinks EE is a great career path. Maybe its my incessent blabbing about it, but there has to be more. My freshman class had 2000 declared engineers but only 500 that made the junior year programs. Why? I think the answer lies in hands-on. Engineering isn't something you just dream about; its something you do. With your hands. When you literally feel it you know its yours.

To feel it you have to do real projects with raw parts. Two of my favorites from my childhood were my rocket sled and my hydrogen separation experiment. (Warning: DO NOT ATTEMPT THESE AT HOME. Sometimes I wonder how I survived...) My rocket sled idea was born from winter doledrums and boredom from building rockets that just went up. One icy New York day, I cut runners from a Coke can, glued them to a rocket tube with three stabalizing fins and lunched it across our frozen lawn. It worked! I then added wings to see if would lift a bit and, well, I'll leave that next part for another time.

The other experiment was more of a "learning experience." Having seen the apparatus for splitting hydrogen and oxygen from water in school, I decided to build one for myself. I decided to go cheap: a beaker, two 0.5m lengths of bellwire, and a wall outlet. The EMF blew the wires out of the socket and vaporized half of the insulation. Lesson learned. These and other "experiments" led me to create a novel solution leveraging a very fast (at the time) disk response and self-modifying code to fit an application on a BBC Acorn that could not possibly fit because I could "feel" the solution.

So what of this generation of internet kids? Is there hope? Well, I can proudly say for one aspiring engineer, there is.

My 17-year-old son Zach wants to be an EE and I'm proud of that. He knows my stories and, as his dad, I can't just say "burn an eyebrow" but secretly... He started with elaborate paper designs: a back-pack personal flyer, a car powered by a flywheel, and more. And then the "experiments" came. First was the tablet computer made from disassembling an old Macbook and then the bottoms-up assembly of his PC. All good, but no smoke.

Then came the video game cabinet. This was a big one. He had to research the construction, buy the components, then WIRE the system, and then configure the computer. Yes, wire it. Together, we designed and built the cabinet. Then we got the wire-strippers and soldering iron out and made some smoke. Yes, that made me proud, but that wasn't it the turning point. That started yesterday when he spent hours doggedly tracking down all the software components needed to configure Ubuntu to run M.A.M.E. but the real lesson came when he found one of the joysticks didn't work. He diagnosed which wires were cross-coupled and fixed them with my grandfather's screwdrivers. A fourth-generation engineer was born yesterday in smoke and debug. I could not be more proud.

Today, Zach is back in school working through his classes and I'm back at work but the world has changed in a subtle but substantial way. I had a convesation with one of Cadence's R&D managers today where we shared the magic of the "oh wow" moment and how he drives this with his children's Mindstorms Robotics league as well as his own team. Facebook has guaranteed that Zach is having the same conversation with his friends. Where there is smoke, there is fire in the belly of the aspiring engineer.

Now back to our regurlarly scheduled verification blog already in progress. (Thank you for indulging one exceedingly proud poppa. :-) )

=Adam Sherer

(P.S. If folks want references to the cabinet construction, M.A.M.E, and/or what Zach did to get it running on the ancient PC hosting Ubuntu I can probably get a guest blogger to post a comment. :-) )

CDNLive! -- The Other Side of the Low Power Design Techniques

QiWang — Thu, 29 Mar 2012 21:34:00 GMT

In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with state retention, dynamic voltage frequency scaling (DVFS), body biasing, and multi-bit flip-flops. Even though each technique can contribute some degree of power savings, not everyone is aware of the challenges and risks associated with each technique. During the Q&A session of the presentation, Annis revealed some interesting back-door facts that can provide some insights into these challenges and risks.

When asked about the challenges about multi-bit flip-flops, Annis brought up the following point. Dual or quad flops will deliver some significant dynamic power savings on the clock tree -- however, the benefits are marginalized when the bits go beyond four, except for highly structured data path logic. The biggest challenge of this technique is in physical implementation where routing congestion may be introduced due to the large cells. Designers may find that more than 90% of the flops need to be implemented with multi-bit flops to achieve the best power and timing.

Back biasing is a simple idea but it certainly has its own challenges. You need some extra routing for the bias supplies, but they tend to be much easier than the traditional power grid design because they carry very small amounts of current. However, to generate negative voltages for the NMOS biasing, you need a charge pump on chip, which by itself is very expensive in terms of silicon area and power!

To avoid this, designers can use reverse bias at the ground connection of NMOS. However, the challenge of doing this is that it requires a ground level shifter, which calls for a new IP design and new methodology for level shifter insertion and checking. How many people ever think about the need for a ground level shifter?

Finally, Annis brought up the importance of new design methodologies for low power mixed-signal designs because of the increasing popularity of low power design techniques in mixed-signal designs. There was another interesting presentation covering this subject in CDNLive! and we will cover it in a future blog post.

Lesson learned? There is no free lunch! Before you decide to use a low power design technique, think twice about the associated challenges and overall costs in terms of power, performance and area. The above presentation will be available soon for CDNLive! attendees from the Cadence CDNLive! site.

Qi Wang

Assertions Help Avoid Chip Melt

Adam Sherilog — Thu, 22 Mar 2012 20:16:00 GMT

When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “Avoiding Chip Melt” article!

Assertions are just the tip of the low-power verification iceberg. (Yep: iceberg + low-power +melting chips = metaphorical mayhem!) Kidding aside, in the article, both Erich Marschner from Mentor and I cite the breadth of issues facing complex, multi-domain power-aware chips. We agree that assertions are a simple starting point for designers to outline their power intentions for the verification team to verify. In the Cadence Incisive solution, we take it a step further by generating the power assertions directly from the power-format file.

But as we said, that’s just the start. Teams with power-aware designs should be running low-power in every regression test because any one of those tests could trigger a change in power-state and the simulator should respond appropriately. Doing so will also make it easier to verify the power-aware aspects of the verification plan. With Incisive, you can also generate verification plans from your power-format file and collect coverage to gain a better understanding of the quality of your power-aware circuits. To learn more about this, please attend John Decker’s upcoming “How to Avoid Low-Power Failures” webinar on April 4.

So whether you’re facing the risk of a melting 40nm chip or just trying to differentiate your product by making it power aware, consider low-power assertions as the first step toward a comprehensive low-power verification methodology.

=Adam “keep it cool” Sherer, Cadence Product Director

Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!

Pete Hardee — Thu, 08 Mar 2012 05:22:00 GMT

CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. This year's theme is Connect, Share and Inspire.

There's a particularly strong showing this year for low power designs and techniques, with many user papers in Track 2, a shared track featuring Low Power and Mixed Signal. Track 2 low power papers are:

9:00 Tuesday: A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP; Rambus Inc.
9:00 Wednesday: Conformal Low Power - Complex Low Power Design Verification; Qualcomm Inc.
10:00 Wednesday: Low Power Implementation on Freescale Kinetis Family; Freescale
11:00 Wednesday: Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification; Cadence

Those interested in mixed signal designs will benefit by staying with Track 2 for the duration, while for those interested in low power design and power optimization for purely digital designs could check out my personal picks from these other tracks:

Track 8 - High Performance

1:30 Tuesday: Being Green - what Good Design and ccopt (formerly Azuro) can do to Reduce Power; Netronome Systems Inc.
2:30 Tuesday: Mali-T604 Embedded General Purpose Computing for GPU implementation in CMOS32LP using Cadence Reference Methodology; ARM
3:45 Tuesday: Implementation strategies for a high performance and low-power ARM® Cortex^TM-A15 processor: Methodology and tools usage best practices; Texas Instruments
4:45 Tuesday: Improving Performance, Power and Area of a High Speed Dual-core ARM Cortex-A9 Processor with Clock Concurrent Optimization Technology; Broadcom

Track 4 - Verification

3:45 Wednesday: Techtorial: Low Power Failures - What not to Plan; Cadence
4:45 Wednesday: Low-power Verification using UVM SystemVerilog; Cadence

Of course, don't miss the keynote speeches from executives from ARM, TSMC and Cadence on Tuesday morning, and the Partner Expo on Tuesday evening. Go to CDNLive SV 2012 for more information.

See you there next week!

Pete Hardee

Does Substrate Biasing Have a Future?

Pete Hardee — Mon, 06 Feb 2012 23:06:00 GMT

At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more widely as many designs, and by no means only mobile designs, become increasingly power-sensitive. But while many advanced techniques (which we take to be the ones applied to power domains, such as power shut-off, as opposed to well-established optimizations like clock gating) are clearly growing rapidly in adoption, some less well-known techniques only seem to find favor with a few, and it's less clear whether adoption is increasing.

In particular, it's widely believed that substrate biasing (AKA body biasing) gives a lesser return in more advanced process nodes (45/40, 32/28 and beyond). What's the latest we're hearing about this?

First the stats...

When we delivered live full-day low-power "Tech on Tour" symposiums around the world in late 2010 and early 2011, we met with over 500 designers interested in low power design. That gave us a great opportunity to survey them. Here's what we found for the adoption of low power technqiues: Biasing is currently used by 5% of our sample of designers, and expected near-future use is 17%. In comparison, for power shut-off, we found the technique in use by 51% currently and 68% in the near future. That would certainly imply the technique's adoption is growing.

Now the anecdotal evidence...

Here's what has been heard by a few of our low power experts worldwide when discussing biasing with customers:

The top two reasons against using substrate biasing are bias supply routing congestion (which increases at more advanced nodes); and difficulty of generating all the bias supplies.
Mobile device SoC's at advanced nodes need all the low-power techniques at the designer's disposal, including biasing, according to one major mobile SoC platform provider. Another provider sees their ability to widely-apply substrate biasing in their libraries and process as a significant differentiator.
Some customers who do not apply biasing to the whole chip below 45/40nm instead apply the technique in conjunction with low voltage standby modes, especially in memories.
At least one customer who used biasing successfully in a 90nm chip is applying biasing successfully to their next generation at 45nm, while another company using forward and reverse biasing in volume at 90nm struggled to meet timing in the next generation at 65nm.

Future of substrate biasing:

Substrate biasing is useful primarily to control leakage at near-threshold voltage in planar CMOS. When FinFET becomes the norm (already used in some 22/20nm processes and will become commonplace for the 14nm node), leakage is better controlled by the gate's 3-D topology and many experts believe use of substrate biasing is unlikely to offer further benefit.

Current support for substrate biasing in the Cadence Low-Power Solution:

Regardless of whether you believe substrate biasing is worth the effort, be assured that the technique is fully supported in Encounter Digital Implementation System and Conformal Low Power. However, please ensure it is also supported by your library provider and foundry.

If you have any experiences to share about substrate biasing or any thoughts on its future, we'd be happy to hear them!

Pete Hardee

What’s Next in Low Power?

QiWang — Tue, 24 Jan 2012 19:00:00 GMT

Low power has become a major consideration in chip design in almost all applications. One major achievement of the industry over the past a few years is the alignment on the low power design methodology, which was considered as the biggest hurdle to automate advanced low power design techniques. No matter whether you are using the Common Power Format (CPF) or Unified Power Format (UPF), the methodology is the same -- it uses a power format file to capture the designers’ power intent to drive the RTL-to-GDSII flow. The recent announcement of 100+ low power design tape-outs from Global Unichip (GUC), along with many other customers who have successfully adopted the Cadence CPF enabled low power solution, indicates the maturity of the methodology in real designs. So, what’s next?

One trend I see is that the concept of low power design is starting to penetrate into every corner of the IC design community. Traditionally, only a handful of projects in a company, or a small group of implementation experts, needed to worry about low power designs. Nowadays, almost every new design start is low power, and every designer, no matter what functionality he or she designs or verifies, needs to understand low power requirements and do something about them. To facilitate such a transition, EDA companies and chip design companies need to collaborate on educating the design community for the new era of low power everywhere.

The recent release of the book Advanced Verification Topics is a good step forward to expand low power design concepts to core verification engineers. Verification experts applauded the release of UVM standard, but how to leverage the new standard for low power design verification is still new to most designers. The book includes a dedicated chapter on low-power verification, with an in-depth discussion on power-aware verification planning and how to configure a power-aware UVM environment.

By bringing together two hot design topics, advanced verification and low power, the book provides unique value for verification engineers who want to apply latest verification technology on complex low power designs. I am sure there will be more such education materials in the future to help the general design community embrace low power design concepts.

Qi Wang

Low Power Design in 2011 and Predictions for 2012

Pete Hardee — Thu, 22 Dec 2011 17:12:00 GMT

It's that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward to in 2012?

It's sometimes humbling to look at one's own technology predictions and see how things fared a year or so further on. Sometime in 2010, I forget exactly when, I was on a "virtual panel" on an on-line technology conference. One of the questions was to comment on developments for future technologies in low power design. I offered the following three points:

20nm node probably marks the end for continuing Moore's law on planar CMOS because process variability and leakage gets further out of control. What will emerge to enable 16/14nm node and keep Moore going? Will it be 3-D transistors, will SOI finally become economically viable, or will something else emerge?
Software is more and more influential on system power and we've got to move up the abstraction level to cope with that. New techniques in ESL power estimation and modeling will emerge
As application demands increase for mobile devices, and leakage becomes more of an issue even in standby modes, we will see the emergence of some energy harvesting techniques to compensate

Note that I was not necessarily saying we'd see all these within a year, but none-the-less, how did these predictions fare?

The end-of-the-line prediction for planar CMOS beyond 20nm was pretty good, as it turns out. What's even better news is that the leading emergent technology, fabricating transistors in 3-D which seems to be most popularly named FinFETs, looks like being very workable. So much so that Intel didn't wait for the 14/16nm node, but is already deploying the technology at 22nm (ref: http://www.nytimes.com/2011/05/05/science/05chip.html). Expected to be widely used at 14nm, FinFETs increase switching performance at reduced leakage, compared with planar CMOS, in a marvel of process technology engineering. This looks like it will have relatively little disruption on the current design tool flow, or current low power design techniques. Moore's Law looks good for a while yet.
As far as software's influence on power is concerned, real developments in ESL tools seemed few and far between. That's yet to happen and maybe we'll see progress in 2012. However, here at Cadence, we are witnessing greatly increasing usage of our Palladium Verification Computing Platform, with CPF support and the Dynamic Power Analysis (DPA) option, for executing the complete chip pre-silicon with software to both test the correct execution of power management (CPF) and estimate power in various real system modes (DPA). Not truly ESL you may argue, but getting the job done.
For energy harvesting, I thought we'd see much cleverer application of solar, thermal and mechanical harvesting in a wider range of mobile devices by now. Maybe we have been too good at deploying existing power management techniques to stretch battery life to at least a full day, to make the inclusion of such technologies in the device economically viable. We should start to see these emerging in the next few years, if not 2012, surely.

There you have it -- for what it's worth. I should mention that these predictions come with a money-back guarantee. If they fail to emerge as stated, I will happily refund exactly what you paid for them! Best wishes to you and yours for the Holidays and a happy and prosperous 2012.

Pete Hardee

Low Power Marketing Hype – And What They Don’t Tell You

Pete Hardee — Wed, 30 Nov 2011 18:00:00 GMT

Here in the USA, we're just back from the Thanksgiving holiday. This year, I got caught up in "Black Friday," which is the day after Thanksgiving, and one of the biggest shopping days of the year, especially for consumer electronics. I'm afraid to say I was convinced enough by some compelling advertising for Black Friday sales to brave the crowds to get a new large-screen HDTV. Doing some minimal research, I had decided I wanted a new "LED" TV -- which is a term that causes some confusion, leading some to think that the LCD screen has somehow been replaced by an array of tiny LEDs. Not the case -- it's an LCD screen with LEDs used for backlighting in place of the older Cold Cathode (CCFL) method. The claims of greater contrast and more even screen were borne out by what I measured in the store with my carefully calibrated instrumentation (mark 1 eyeball).

But since this is a low power blog, what I found really interesting was the degree to which the leading manufacturers marketed the low power aspects of their products. LED TVs do indeed have better power consumption than CCFL LCD. But the "SmartPower" technologies and comparisons of annual electricity costs for the models were prominently touted, with both green and economic benefits stressed.

However, it occurred to me that maybe the largest benefit of low power in consumer electronics is not marketed. Lower power means lower operating temperature which means typically much greater reliability. Engineers who have ever been involved with burn-in testing (or at least those who know what a bath-tub curve is) know this to be true, and probably, we've all had equipment fail at home. I still regularly find the need to clear out DVD covers and other stuff the kids have left that blocks the airflow to my DVR before that fails - again! Why isn't this marketed as an advantage? Maybe because that would involve admitting how poor the failure rates are on so many other models that don't have these smart power features.

I'd be interested to hear about any experiences out there with your electronics!

Pete Hardee

Si2 Interoperability Guide V2.0 Available for Download

QiWang — Mon, 31 Oct 2011 16:00:00 GMT

Recently, the Silicon Integration Initiative (Si2) announced the availability of the Interoperability Guide for Power Format Standards V2.0. This is an important milestone of power format interoperability between IEEE 1801-2009 and the Common Power Format (CPF).

This update was triggered by the Si2's CPF 2.0 release earlier this year. CPF 2.0 is a major CPF release on top of the previous CPF 1.1 and 1.0 releases. Many new features were introduced in CPF 2.0. To learn more about CPF 2.0, check out the online tutorial.

Another major accomplishment of this new version of CPF is that it has some noticeable enhancements to improve the interoperability with IEEE 1801. For those who are close to the two formats, here is a short list of enhancements made in CPF 2.0 to improve interoperability:

Support -pg_type in create_global_connection
More flexible mode specification to model functional modes
Ability to force isolation and shifter insertion on crossings that do not require isolation by default
Ability to model more types of state retention logic
Ability to enable/disable power aware simulation semantics

The recently released Interoperability Guide V2.0 is an update of the previous version with changes included. For those who are using a low power design flow with mixed power format languages, the new release is a must read.

Qi Wang