Cadence IP Blogs

Cadence Video Demonstrates PCIe Gen3 IP Silicon Performance

ashwinmatta — Mon, 06 Aug 2012 17:00:00 GMT

It is not often that an IP provider gets to showcase their IP performance in a real product demo. Those laurels usually end up going to the end product that uses the IP. But a recent Cadence video features our PCI Express (PCIe) Gen 3 core running flawlessly in silicon in a real system.

We thought we would raise some eyebrows since, as of today, there are very few products in the market that utilize the full power of the PCIe Gen3 protocol, let alone those that have been designed using a commercial IP offering. Cadence has been working very closely with its early PCIe Gen3 customer, PMC-Sierra, to develop a Gen3 X8 Dual-mode controller IP with full support for the PCIe 3.0 specification, including SR-IOV and all ECNs. This IP interfaces to the PCIe bus on PMC's 6Gb/s SAS/SATA controller chip that is installed in Adaptec's RAID controller card.

In this demo we are showing the high storage data throughput between the Intel Sandy Bridge PC and the array of SATA SSD drives via the Adaptec HBA card. All the hardware used in the demo, with the exception of the soon-to-be-available Adaptec card, uses off-the-shelf components that you can buy from any hardware store. The demo is around 4 minutes in length, and I invite you to take a look. And if you are a PCIe geek as I am, this might take your breath away!

Click on the icon below to view the demo, or click here.

Ashwin Matta

Martin Lund on the Future of IP (Video Interview)

Neil Hand — Wed, 13 Jun 2012 22:33:00 GMT

As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually trying to solve.

Martin Lund, Senior Vice President at Cadence, was recently interviewed at DAC2012 by EE Times’ Brian Fuller. Martin laid out a vision for commercial IP, describing requirements for integration, test benches, certification environments, integrity models, and test chips to deliver high quality, reliable IP that will truly reduce costs and improve time to volume.

Check out the interview here: http://video.eetimes.com/playlist-video/dac-2012/1653470487001/eetimes-live-stream-dac-2012-martin-lund/1675544149001

Neil Hand

Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

StellaM1 — Thu, 04 Aug 2011 00:00:00 GMT

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.

What is SR-IOV? Briefly, SR-IOV is a specification that allows a PCIe device to appear to be multiple separate physical PCIe devices. PCI-SIG created and maintains the SR-IOV specification with the goal of having a standard specification to help promote interoperability. One of the milestones achieved for Cadence’s design IP for PCI Express Gen3 is proving SR-IOV interoperability in silicon against an Intel chipset.

Why is it important? The two main advantages of an SR-IOV PCIe device are:

It allows multiple OS’s to have their own private view of the PCIe device
It helps improve I/O performance by reducing latency of the hypervisor

How have Cadence customers used PCI Express Gen3 SR-IOV to solve their design problems? In one example, a SAS RAID controller using 2 physical functions (PFs) and 16 virtual functions (VFs) was able to have 16 guest applications privately access the PCIe device. VFs are “lightweight” and have the advantage of requiring significantly less logic overhead than PFs.

Please see the video below for more details. Also, please comment on how you've seen PCIe Gen3 SR-IOV used in different applications.

Stella Murphy

Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)

StellaM1 — Thu, 28 Jul 2011 18:00:00 GMT

This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.

Highlights:

The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification
The demo shows Cadence's PCIe Gen3 high performance x8 configuration operating at full speed 500Mhz clock rate with a transfer rate close to 8GT/s
The display trace shows the PCIe Gen3 IP transition from Gen1 speed 2.5 GT/s to Gen3 8GT/s
LTSSM flow graph showing equilibrium between upstream and downstream packet transfers and speed of operation at 8GT/s

Please come back soon to view Part 2 of 2 showing the advanced features of Cadence's PCI Express Gen3 IP.

Stella Murphy

Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon

StellaM1 — Thu, 30 Jun 2011 19:00:00 GMT

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's ASIC. The Cadence PCI Express 3.0 controller in the ASIC reference card was attached to a LeCroy Summit T3-16 analyzer and Summit Z3-16 exerciser platform to demonstrate the Cadence PCI Express 3.0 core with traffic running at 8 GT/s per lane.

The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification.The PCI Express Gen3 IP successfully implemented in silicon advanced capabilities like Single-Root I/O Virtualization (SR-IOV), as well as the latest engineering change notices (ECNs) including ID-based Ordering, Re-Sizeable BARs, Atomic Operations, Transaction Processing Hints, Optimized Buffer Flush/Fill, Latency Tolerance Reporting and Dynamic Power Allocation. The Cadence PCI Express 3.0 IP has already been implemented in the recently announced PMC-Sierra 6Gb/s SAS Tachyon protocol controller.

To learn more about the Cadence Design IP for PCI Express Gen3 IP, please come back next week to see the PCI Express Gen3 IP video of the demonstration.

Stella Murphy

Can DRAM Contents Survive a Reboot? Surprisingly, In Most Cases The Answer is, “Yes”

Marcgr — Wed, 20 Apr 2011 17:00:00 GMT

A Cadence DRAM Memory Controller IP customer asks, "I have a DRAM subsystem with ECC and my system has the capability to use write data masks and partial-word writes. DDR3 has a reset pin, why can't I just reset it? Why do I need to initialize the memory?"

The answer is "yes, you must initialize it" but the reason may be surprising to many people: DRAM contents are not lost when the power is turned off! I stumbled upon this great research paper from Princeton University this week which is interesting in itself (it talks about how most encryption is vulnerable to hacking through the DRAM), but also has some interesting data about just how long data can persist in DRAM. The researchers found that some of the bits in DRAM were still capable of holding charge minutes after losing power, even when the memory is removed from the machine entirely. A video clip located here shows the process they used, and at one point shows them removing a DIMM from one machine and putting it into another - and then retrieving all the data out of that DIMM!

For those interested in information technology security, this data suggests the importance of encrypting the contents of DRAM as well as the contents of a hard drive - but that was not the concern of the customer who asked the original question. When using ECC (Error Correcting Codes) in DRAM, a typical arrangement is to have 64 bits of data and 8 extra ECC bits that hold a SECDED code that is capable of correcting a one-bit error and detecting a 2-bit error in the 64 bits of data (Cadence's DRAM controller allows other sizes like 32&7, 32&4, 16&2 but let's stick with 64&8 for now).

The problem arises when the system needs to write less than the full 64 bits of data, and the memory controller needs to do a Read-Modify-Write (RMW) operation on the memory location to be able to preserve the part of the write data that was previously in that memory location that is not being overwritten by the current write operation. If the 64 bits of data that are being partially overwritten have stale and partially-degraded memory contents from the previous time the DRAM was used (for example, if the machine was turned off momentarily and then turned back on again) then when the memory controller tries to read that memory location it will encounter ECC errors when it tries to do the read portion of the RMW operation.

Wait a minute, don't newer DRAMs like DDR3, DDR4 and LPDDR2 have a reset pin?

Yes they do - but that reset only resets the memory state machines; it is not guaranteed to reset (or not reset) the memory contents.

Umm... okay, so what do I do about it?

I'm glad you asked! The simplest thing is never to do masked or partial word writes - then any time you might use a memory location that had old data in it, you will overwrite it completely. You system will still have lots of errors, though, if you happen to read a location in memory that has not been written to yet. This solution is impractical for systems working with short and irregular data packets like networking and video.

In simulation, you can use advanced properties of your Verification IP (VIP) such as Cadence's VIP Catalog Memory Models (formerly known as Denali MMAV) to set a pre-assigned value into all the DRAM when you start simulations, so that you don't have to initialize the DRAM in simulation every time. Just be sure to do your final signoff on a memory with randomly assigned background data and do take care to initialize it.

For your real system, you can write a program for your CPU that writes to every DRAM location, although this could take a while. Cadence's DRAM Memory Controller IP has a BIST option that will run a hardware test on the DRAM as well as leave the DRAM's ECC check bits in a correctly calculated state and which will run significantly faster than in software.

Now... how do I encrypt that DRAM?

Maybe a topic for another blog...

Marc Greenberg

New Memory Technologies, New Possibilities

Neil Hand — Mon, 11 Apr 2011 15:30:00 GMT

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will impact everything from the user experience to the applications that are possible. There is nothing quite so sad as a shiny new gadget that falls short because of poor memory performance (something easily avoided with the right IP), or trying to install a new app only to have to decide what you must delete to make room for it.

It’s been a busy few weeks for the IP team with the announcement of support for two new memory technologies – DDR4 and Wide I/O.

With Wide I/O and DDR4 offering significantly improvements for the device classes they target for, it’s exciting to contemplate how design teams will leverage them to deliver on the next wave of devices. So whether it’s a high performance gaming desktop, a sleek new tablet, or enterprise equipment that interests you, new memory technologies will play a key role.

Learn more about Cadence Design IP for Memory and Storage.

Neil Hand

The 3D SSD

sleibson — Mon, 29 Nov 2010 23:22:27 GMT

You need three things from a solid-state disk (SSD): speed, capacity, and reliability.

You need three things from a portable SSD: speed, capacity, reliability, and diminutive size. And you can’t get much smaller than packing an SSD into the form factor of a USB memory stick. That’s exactly what LaCie has done with its FastKey drive. It’s packed a 30 to 120Gbyte USB 3.0 SSD into the form factor of a slightly oversized USB memory stick but the LaCie FastKey doesn’t perform like a memory stick. Depending on capacity, the read/write speeds of the LaCie FastKey are 210/70 to 260/180 Mbytes/sec. Add in 64Mbytes of DRAM cache and 256-bit AES encryption and you’ve got one Hulk of a memory stick.

Now I don’t know this for a fact, but it seems to me that you can’t build a product like this with conventional IC packaging. The volumetric allowances argue for more of a 3D chip assembly approach. And whether or not this particular product employs 3D assembly, the existence of the LaCie FastKey points the way to a future where the innards of many such memory-stick SSDs will make use of 3D assembly. After all, plastic IC packaging really adds no value to this sort of product and merely gets in the way.

Increasingly, 3D assembly is going to become a competitive advantage when the end product’s size matters. It already matters in mobile phone handset design and 3D assembly is widely used in this niched (but very large) market segment. As time unwinds, 3D assembly techniques will improve and get less costly because of high-volume mobile handset market demands. The rest of the industry will follow.

STT-MRAM -- from Seagate???

sleibson — Fri, 05 Nov 2010 16:58:03 GMT

On June 12, 1989, I flew to Minnesota from Denver, Colorado, picked up a rental car, and drove from Minneapolis to Bloomington to attend a special disk drive conference being held by the leading vendor of cutting-edge 5.25-inch hard disk drives--Imprimis--which was the disk-drive spinout subsidiary of Control Data Corporation (CDC). I had an ulterior motive on this trip: to get two of Imprimis’ 330Mbyte SCSI disk drives for my EDN “All Star PC Project.” The Imprimis drives were the biggest, baddest hard drives available at the time and Imprimis had a world-class lead in high-speed drive design attributable to CDC’s world-class magnetics research center in Bloomington. Unfortunately, June 12, 1989 was also the day that CDC announced Seagate’s purchase of Imprimis and the addition of Imprimis' magnetics research facility to Seagate’s growing technology arsenal. So I arrived at Imprimis to find the conference cancelled and no one to speak with. I left the Imprimis lobby to fly back to Colorado within an hour of my arrival at Imprimis, without the drives. (I did eventually get a pair of those drives for the All Star PC project, but that’s a story for another time.)

Fast forward to 2010--this week in fact. I’m at the 8th International SoC Conference in Newport Beach, California and I’ve just heard a presentation from Seagate’s VP of the Memory Products Group R& D team Pat Ryan. His topic: spin-transfer-torque magnetic RAM (STT-MRAM). This R& D group is part of the Minnesota magnetics research group that Seagate bought 21 years ago and that facility is just celebrating its 50th year of existence.

Despite having written several detailed articles about MRAM and STT-MRAM, I had no idea that Seagate had a team working on the technology, but it makes sense. The fundamental memory cell in an MRAM, STT or otherwise, is the magnetic tunnel junction (MTJ) and it turns out that MTJs are very familiar to disk drive vendors. “We make millions per day,” said Ryan, “to serve as read/write heads in disk drives.” The company has devoted some resources to investigating the use of MTJs in STT-MRAM.

It turns out that Seagate knows a lot about STT-MRAM and MTJs.

Researchers at the company know how to make thin anisotropic magnetic films that allow magnetic polarization that’s perpendicular to the junction, which improves storage stability. They also know how geometric scaling affects read and write currents for STT MTJs. They have put lots of read/write cycles on STT MTJ memory cells and know that the MTJ’s storage abilities do not degrade with extended cycling. They also know that the memory retention is well hardened against external fields and radiation.

Finally, they know that STT MRAM will be giving embedded SRAM, DRAM, and NOR Flash a run for the money starting around the year 2013.

But don’t look for Seagate to be a player in the STT MRAM IC competition. Ryan gave the clear impression that Seagate is currently only interested in enhancing hard-disk drive performance. It will leave the IC race to others.

Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only option

sleibson — Thu, 21 Oct 2010 16:42:42 GMT

Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced two new lightweight MacBook Air notebook computers. Significantly, neither HDD nor optical disk storage is an internal option for these two new laptops. SSD is the only storage on offer, with capacities from 64 to 256 Gbytes. Although Jobs claims that Apple placed the SSD “right on the motherboard,” the images he showed were of a small circuit board (clearly NOT a standard SSD board format) that plugged into the motherboard. Elements of the announcement that make the new MacBook Airs more resemble an iPad include multi-touch gestures on a generous touchpad below the full-size keyboard, a Mac-specific app store, an app home screen, full screen apps, auto save, and apps that resume when launched.

Here’s more coverage at MSNBC.com’s Techblog: http://technolog.msnbc.msn.com/_news/2010/10/20/5322959-live-coverage-apple-reveals-macbook-air-mac-os-x-lion-ilife-11-and-more