Industry Insights Blog

A UPF User Perspective on the Evolution of Power Standards

rgoering — Wed, 19 Jun 2013 13:00:00 GMT

With the recent release of the IEEE 1801-2013 (UPF 2.1) power intent format standard, prospects for "methodology convergence" between the Unified Power Format (UPF) and Common Power Format (CPF) are looking good. One company that has used both formats and is following the evolution of power standards is STMicroelectronics.

Fellow Cadence blogger Adam Sherer and I recently spoke with David Vincenzoni, who works in the Industrial and Power Conversion Division of STMicroelectronics. His group develops large, complex industrial ASICs with embedded processors, including mixed-signal ASICs and SoC power line modems. Low power design is key, and many chips have two, three, or more power domains that can be switched on or off or carry different power levels. "It is vital to have a proven, low-power flow that goes from RTL to signoff," Vincenzoni said.

According to Vincenzoni, key challenges in low-power design include the following:

Designers need to anticipate bad connections that could occur during RTL design. "This means that we have to simulate the power domains in the RTL using the power description that will be used in the next steps of the implementation phase."
The need for a language that can describe high-level power intent at the RTL stage, and also has the constructs to describe power intent at the physical level.
Developing formal checks between the power-off and isolation cells.

The last SoC developed by Vincenzoni's group had two power domains with three power modes. There were also several level shifters between the core logic and the I/Os. A separate power domain was represented by an analog front end. Engineers used CPF for verification and UPF for implementation, and also used equivalence checking for the power intent.

Using IEEE 1801 UPF

For a recent IP development, Vincenzoni's group used IEEE 1801 UPF along with verification from the Cadence Incisive simulator. The block has two power domains and three possible power modes. A block diagram of the IP block is below.

Vincenzoni explained: "Through Specman and the UPF 1801 description of the power intent, we simulated the power modes of this IP. The implementation engineer used the same UPF 1801 description during the synthesis and equivalence checks. This IP can be delivered with the UPF 1801 description file, which can be included with the power intent of the SoC that will integrate it."

According to Vincenzoni, the older Accellera UPF 1.0 standard could be good enough for a power intent description at the implementation level, but it is too detailed for an RTL description. IEEE 1801-2013, on the other hand, inherits several CPF constructs that allow a high-level description of the power modes of the design, and it also supports low-level descriptions for the back-end flow.

Advice for UPF Users

By leveraging CPF constructs and deprecating some of the older UPF 1.0 commands, IEEE 1801-2013 opens the door to methodology convergence between UPF and CPF. Power format convergence is the "right way," Vincenzoni said. "For the designers, it is essential to have a language that is supported by all the tools of the ASIC design flow."

At present, STMicroelectronics uses the IEEE 1801-2009 (UPF 2.0) standard, and expects to stick with that through the next few projects. Vincenzoni said his group is "interested" in IEEE 1801-2013 but has to take tool support into account.

Vincenzoni's advice to UPF users: "Start to use UPF 1801-2009 and follow the evolution of the standard. Start now with UPF 2.0, and when the tools support UPF 2.1 it will be easy to switch."

Richard Goering

Related Blog Post

A CPF User Perspective on IEEE 1801 (UPF) "Methodology Convergence"

What the Evatronix IP Acquisition Brings to Cadence

rgoering — Mon, 17 Jun 2013 04:00:00 GMT

On June 13, 2013, Cadence announced it had completed the acquisition of the semiconductor IP business of Evatronix SA SKA. So who is Evatronix, and what does their IP business include? At the recent Design Automation Conference (DAC 2013), a Cadence Theater presentation by Jacek Duda, marketing manager at Evatronix, answered those questions.

Based in Poland, Evatronix is a provider of USB, MIPI, display, and storage controller IP, as well as quite a few industry-standard microcontrollers - 8051, 68000, and 80186. Evatronix peripheral controllers, combined with PHYs from Cadence, promise complete interface IP solutions that include controller, PHY, verification IP, and integration kits. Cadence announced its intention to purchase Evatronix's IP business in May 2013.

As Jacek noted, Evatronix was founded in 1991 and sold its first IP - an 8051 controller - in 1995. The company has around 60 employees, mostly engineers. The company has sold over 700 licenses, and 90% of its business is in the ASIC market. Evatronix also offers design services.

Jacek's presentation highlighted the following offerings from the Evatronix IP portfolio.

USB Solutions

Evatronix has staked out a strong position in USB-IF certified IP. Offerings include a USB-IF certified USB 3.0 (SuperSpeed) device controller and a SuperSpeed USB 3.0 hub, as well as USB-IF certified USB 2.0 controllers for device, hub, and OTG (On The Go). Silicon success for their USB High-Speed Inter-Chip (USB HSIC) solution goes down to 28nm. Evatronix provides software stacks and class libraries with its USB offerings.

NAND Flash IP

Evatronix provides NAND Flash controller IP that comes with a soft PHY or an SDLL PHY and with software drivers. Jacek showed the following diagram of the Evatronix NAND Flash controller. "We decided to keep the data buffers outside the controller," he remarked. "It is, therefore, really small, so it's got a lot of benefits for mobile applications."

Evatronix NAND Flash controller

Features of the NAND Flash controller include:

Support of memories from all major manufacturers (Toshiba, Micron, Samsung)
Legacy asynchronous mode
Synchronous mode support ONFi up to 3.0 (400MT/s) and Toggle Mode 2.0
Raw NAND and Clear NAND support
Error correction code (ECC) support for the BCH algorithm up to 128 bits
Support for small and large block NAND Flash devices

The NAND Flash IP can be customized in a number of ways, including custom sets of programmable error corrections, number of devices per bank, generic command sequence, support for small-block NAND Flash devices, and optional features including bad block management support.

SD Host 4.0

Secure Digital (SD) host IP supports the eMMC 4.51 specification, SD Host Specification version 4.0, the SD Physical Layer Specification 4.0, and the UHS-II Addendum 1.0. Features include a selectable, integrated DMA controller, support for single or multiple SD memory card slots, and UHS-II speed support.

MIPI SLIMbus IP

Evatronix has been providing MIPI SLIMbus IP solutions since 2006, and its Manager and Device controllers are now in their sixth generation, according to Jacek. The architecture for the SLIMbus Device IP (shown below) implements Interface, Generic Device and, optionally, Framer Device classes. The SLIMbus Manager IP implements Interface and Manager classes, with Framer and Generic Device class support being extra features. The Manager also supports message channel monitoring.

Evatronix Slimbus Device IP architecture

8051 Controller IP

Evatronix started its IP business with 8051 controllers and that's still a very strong market, according to Jacek. Three options are available - a configurable 8051, a fast 32-bit 80251, and a small 8051 that takes only 3,000 gates. The company also developed its own proprietary 8051 debugging environment.

Value Proposition

Jacek ended his talk by noting the following advantages of Evatronix IP:

Full compliance with the relevant specifications
Many successful customer designs
Silicon-proven IPs that are shipping in mass production
High configurability
Complete solutions with controller, PHY, and software (where applicable)
Support for industry-standard interfaces such as AXI, AHB, OCP

In my opinion, this IP will be a worthy addition to the Cadence family. It will complement IP previously acquired from Denali, Tensilica, and Cosmic Circuits, and allow Cadence to provide an even more comprehensive SoC design solution. Welcome Evatronix!

Richard Goering

DAC 2013 Panel – Can Better Organization Solve the Verification Crisis?

rgoering — Thu, 13 Jun 2013 08:45:00 GMT

Automated tools and standardized methodologies have made functional verification easier, but verification is still arguably the biggest bottleneck in getting chips out the door. The good news, according to panelists at the recent Design Automation Conference (DAC 2013), is that organizational and management changes can ease the verification crisis.

The not-so-good news is that architects, design engineers, and verification engineers will have to step out of the comfort of their "silos" and work much more collaboratively than they have in the past. And companies must foster a culture in which verification engineers are valued.

The panel, held at the DAC Pavilion June 4, was titled "Organizational and Management Solutions to the Verification Crisis." It was moderated by Mike Stellfox, Cadence fellow. Panelists were as follows, shown left to right after Stellfox (far left) in the photo below:

Scott Runner, vice president of advanced methodologies and low power design, Qualcomm (San Diego)
Neeta Ganguly, validation manager, Intel (Austin)
Alan Hunter, verification architect, ARM (Austin) and chair of the Accellera Unified Coverage Interoperability Standard (UCIS) committee

Here are some of the key takeaways from the panel.

1. It's hard to find qualified verification engineers

Stellfox: One of the biggest issues I'm seeing is the lack of verification engineers and expertise in the industry now.

Runner: Certainly verification resources are a critical constraint, and I think all of us are looking at a variety of solutions to address that. One approach is for people who already have the requisite skills to come into a company. Another is to train people to develop verification skills.

Hunter: Here in Austin, it can be difficult getting well qualified people. We are starting to see some graduate courses now, but it is still a challenge.

Ganguly: I notice there's not enough verification talent for the amount of work that needs to get done. In Austin it is very tough to find people with the right kinds of skills.

Runner: I'm from San Diego. I'll add San Diego to that list. And folks in the [San Francisco] Bay Area would say it's hard to find DV [design verification] folks. It's a collective problem overall.

2. Verification must include power and performance

Runner: Not only does lack of verification impact quality, it impacts power. If a power feature is insufficiently verified and doesn't work, it affects the power budget and impacts performance. Performance validation is another critical issue.

Ganguly: Just knowing one particular area isn't good enough. The verification engineer really needs to know, from front to back, where the power is going, and what gates get turned off to enable power management functions.

3. Companies must foster a good verification "culture"

Stellfox: I've seen companies that have a good verification culture, and I've seen companies that don't even have a career track for verification engineers.

Runner: One of the challenges is that verification engineers don't feel appreciated, or don't feel they're on par with design. You need to hold verification on par with design and say both are responsible for verification milestones. For example, if the verification guy finds a bug and the designer has to debug it, whose test plan will be used? It's a joint test planning activity.

Hunter: We try to foster a community around verification. We have a verification conference once a year and we've invited designers as well.

Ganguly: The end result is a joint effort between architecture, design, and verification teams. All of them have to be responsible for the design. I think that at Intel, verification people are treated on par with RTL designers.

4. Designers should be more involved with verification...within limits

Hunter: We try to get designers to think about interface constraints from day one, rather than trying to do it piecemeal after the fact, which just never works, to be honest. We have a good buy-in from the designers.

Runner: In the past we've tried to force the issue that designers should also be DV engineers, in addition to micro-architectural design, RTL coding, timing analysis, synthesis, and documentation. It's not very feasible. But clearly, having designers participate in test planning is very critical. Design for verification is another key area. The problem is to figure out the right roles and responsibilities for the team rather than force designers to do verification.

5. Verification engineers can help the design effort

Ganguly: We were trying to define an architectural protocol, and we had architects, designers, and verification people all in the same room going through that protocol. The verification engineers actually had a lot of perspective and they could point out holes as the architecture was being defined. This cleaned up a lot of problems before they got coded in.

6. Specialized verification engineers need to step out of their silos

Stellfox: Verification is not just simulation. You've got virtual platform teams, software integration teams, emulation teams, simulation teams, post-silicon environments -these groups tend to be working in silos in the company, because they're specialists.

Ganguly: This verification continuum is, I think, the biggest challenge out there. Because of the complexity of our designs we can't do it all in pre-silicon, or emulation, or virtual platforms - we have to have all these working together in order to verify.

Runner: When you have completely independent organizations that don't interact, things become more skewed. If you have disciplined interactions like joint reviews, I think you start to coalesce.

7. Don't try to change too much at once

Runner: When you come in and try to throw a new methodology over the wall to people who have been there 10 or 15 years, it's tough. It's better to align yourself with people who get it and maybe try an initial project. Don't try to do too much.

Ganguly: You might want to start with a joint team including architecture, design, and verification. Once they have proven that it works, you can get more buy-in from the rest of the company.

Conclusion

All in all, this was a very thought-provoking panel that delved into a topic we don't hear much about - how company culture, organization, and management can ease the verification crisis. This discussion was long overdue.

Richard Goering

Note: Scott Runner was also a speaker at the Designer Keynote at DAC. For a report on that keynote, click here.

DAC 2013: Qualcomm, TI Keynoters Present Mobile SoC Design Challenges and Solutions

rgoering — Tue, 11 Jun 2013 08:50:00 GMT

Keynote speeches at electronic design conferences tend to focus on high-level industry issues. The "Designer Keynote," part of the Designer Track at the recent Design Automation Conference (DAC 2013), was different. In engineer-to-engineer talks, design managers from Qualcomm and Texas Instruments discussed challenges and solutions for designing mobile communications systems-on-chip (SoCs).

The first speaker was Scott Runner (right), vice president of advanced methodologies and low-power design at Qualcomm. He spoke about SoC design for mobile applications, particularly smartphones. The second speaker was Sanjive Agarwala, TI fellow and director of worldwide silicon development at Texas Instruments. He focused on the design of mobile infrastructure processing systems from a base station point of view.

Both reached essentially the same conclusion - whether it's an SoC for a cell phone or a base station, it's a system-level problem that needs system-level solutions.

Mobile SoC Processor Challenges

Runner started his talk by pointing to the complexity of smartphones today. Far more than phones, they are "integrated platforms for providing seemingly disparate technologies that have come together to provide a new user experience." What is required to create such a device? "The heart of it is a mobile SoC processor that must be married together with power management ICs, with RF, sensors, display, and battery, into a small form factor that has to be light and low cost," Runner said.

Runner identified three key challenges in smartphone design - low power, verification/validation, and hardware/software co-design. Illustrating the power challenge, he showed a plot of the relative performance increase of the CPU, GPU, and memory bandwidth over time, compared to the power savings provided by process node shrinks. Conclusion: "Process scaling is insufficient to support the increase in performance that's required to enable all these exciting new applications."

Runner noted that there's a tremendous amount of "feature growth" in smartphones today, translating into a demand for performance and memory. And yet, designers have a thermal envelope with a limitation of 4 or 5 watts (compared to about 20 watts for a laptop). Battery technology is not keeping up with the increasing demand for power consumption.

DAC chair Yervant Zorian (right) presents Scott Runner with an appreciation certificate following Runner's talk.

How can we solve the power problem? "First and foremost, we must realize this is a system design problem," Runner said. That requires an awareness of system architecture, workload partitioning, hardware/software partitioning, and power modeling and optimization. Also, there's a need for effective power management strategies - such as dynamic CPU and GPU control, dynamic voltage and clock scaling, and power gating. Designers need to determine where return on investment is best.

Complex Verification Task

Runner's second challenge was verification and validation, and he noted the difficulty of validating complex system-level scenarios. And it's not just a matter of finding functional errors. "I have to pay attention to performance and security validation, power validation, regulation and conformance testing, interoperability and field testing, compliance and qualification testing, and user interface testing," he said. And to top it all off, process variability is on the rise.

The solution, again, is working at the system level. That means validating the architecture at a high level of abstraction, and re-using verification and validation throughout the flow. It also calls for a variety of engines including simulation, formal verification, acceleration, and emulation, since all have different performances and timeline requirements.

The third challenge, hardware/software co-design, is driven by a realization that "software is growing faster than hardware" and is experiencing a state space explosion of its own. Runner takes a realistic view: "Do I expect hardware and software teams to use the same tools, to be on the same design timelines, to use just one model abstraction? No. I see collaboration between hardware and software teams in terms of documentation and specifications and the overall platform."

Challenges of the Infrastructure

To use mobile communications devices, you have to have an infrastructure that supports them, and that's what Agarwala (left) oversees. He first noted the complexity of embedded systems such as base stations and the myriad of requirements they must meet - not only power and performance, but also safety and reliability. "Putting all this together is the crux of being able to grow in this industry," he said.

Agarwala noted that there are about 6 billion mobile subscriptions today, growing to 9.1 billion in 2018, and about one billion smartphones, growing to 4.5 billion in 2018. "What this means for networks," he said, "is that the expected growth of network capacity in five years is expected to be 12X over what you have today, and 46% of that will be mobile traffic."

Certainly there has been progress in the past 10 years. Today, Agarwala noted, a two-chip solution can implement an entire multi-standard base station. While a typical IC in 2000 had 40-50 million transistors, today we're planning designs with 3 billion transistors. A number of different types of cores are being pulled into systems, increasing bandwidth requirements. No wonder building a platform such as TI's KeyStone can be a $100 million investment.

Agarwala noted the following "complexities" in mobile infrastructure SoC design:

Semiconductor IP. "An industry ecosystem needs to come together for us, and the key challenge for the industry is how to make IP easy to use, integrate and deploy."
Power Management. Whether static or dynamic, this is a huge issue. "Don't just think from a device or block level - think of it from a system and board level."
System Management. To build asynchronous systems, designers must be aware of reset, clocking, design for test (DFT), interrupts, and interconnect fabric.
Board-level Integration. Power management and integration of devices at the board level continue to be big challenges.

"Systems knowledge is key" is the primary lesson learned, Agarwala said. "Think back to the $100 million investment required," he said. "You have to figure out where to spend dollars and time in terms of optimization. Don't just optimize at the individual entity level - focus on the system. Are you optimizing the part or are you optimizing the whole?"

Richard Goering

Related Blog Posts

Gary Smith at DAC 2013 - the $170M SoC Design is a "Myth"

NI CEO Sounds Call for Platform-based Design at DAC 2013

Cadence CEO at DAC 2013: 'I've Doubled, Tripled Down on Semiconductor Investment'

Freescale CEO at DAC 2013: "Internet of Things" Brings Opportunities, Challenges

Samsung DAC 2013 Keynote: EDA, Semis "Not Well Prepared" for Next Mobile Revolution

Samsung DAC 2013 Keynote: EDA, Semis “Not Well Prepared” for Next Mobile Revolution

rgoering — Fri, 07 Jun 2013 00:22:00 GMT

Stephen Woo, president of Samsung Electronics, came to the Design Automation Conference (DAC 2013) with what amounted to a wake-up call. While the EDA and semiconductor industries are doing a great job enabling the most exciting applications of our times, and have some "tricks to play" for the next two to three years, "we are not well prepared" for the technology revolution coming down the road in the next three to five years, he said.

Woo's keynote speech, delivered June 4, was titled "New Challenges for Smarter Mobile Devices." It included a look at the evolution of smartphones, starting with the i-mode phone (introduced in Japan in 1999) and, much more recently, the Apple iPhone and Samsung Galaxy phones. This year, Woo said, smartphones will offer full HD resolution, and high-end smartphone cameras will provide up to 13 megapixels.

And yet, he noted, if you take a smartphone apart, you will find a big battery—and a pc-board with about 1,000 components. "We still have to use more than a dozen chips and many passive components to build a phone," Woo said.

Engineering Challenges

The demand for newer and better smartphone applications leads to three engineering challenges, Woo said. These challenges, and their current solutions, are as follows:

Space: Form factor can be reduced by moving to lower process nodes, and potentially by 3D integration.
Applications: New apps demand a lot of processing power, which is now provided by dual-core, quad-core, and even 8-core processors. Software developers originally resisted multi-core processors, but these are expected now.
Battery and Heat: The EDA community has developed many useful low-power technologies, such as dynamic frequency and voltage scaling (DFVS). Further power reductions can be found through hardware/software integration. Thermal-aware design tools are available.

Going forward, how are we going to address new applications and new requirements? Woo said there are three "tricks" we can play—FinFETs, 3D architectures with the JEDEC Wide I/O memory standard, and new architectures for display.

While the power and performance advantages of FinFETs are well known, Woo observed that "FinFETs are not a free lunch. There are difficulties associated with them, and you have to understand them to really take advantage of the benefits of FinFETs."

As for 3D architectures with Wide I/O, Woo said it is "conceptually very beautiful" to put memory on top of logic using thousands of connections. But there aren't many such devices, because they require logic design, memory design, and packaging expertise. Woo showed pictures of a 3D-IC with Wide I/O that provided 14% more bandwidth than LPDDR3 memory, while using 60% less power.

New display architectures represent a "niche" area that has a lot of promise, Woo said. If you can put memory inside the display driver IC, then the applications processor can just "shift data and forget it," allowing a greatly reduced workload. In some cases, application processor power can be reduced by 90%.

Are We Ready for 2018?

The above "tricks" will work for a few years, but something more fundamental is needed to the "magnitude of the revolution" that is coming in three to five years, Woo said. He noted that the first public demonstration of a flexible display occurred at the Consumer Electronics Show this year. This kind of display opens some interesting possibilities—for example, you could fold it like a handkerchief and put it in a pocket.

But what good is a flexible display if your smartphone still has a rigid PCB and a back cover? "None unless we change the PCB structure," Woo said. But if we could reduce all the chips and passive components into one or two chips, then we could have a flexible smartphone, he noted.

"Are we, as EDA and semiconductor companies, ready to take advantage [of flexible displays]?" Woo asked. "My assessment is, not really. We're still trying to figure out how many gates to put into a chip, not how to reduce the total number of chips to one." An SoC is supposed to place an entire system on a chip, but today's reality is more like "a system on 1,000 chips," he said.

"We should be able to come up with a new way to integrate the system, and a new way to take advantage of the flexible display," Woo concluded.

Richard Goering

Other DAC 2013 Keynotes and Speeches

DAC 2013—Kaufman Winner Hu: FinFETs Will Serve Analog Design Very Well

Gary Smith at DAC 2013 - the $170M SoC Design is a "Myth"

NI CEO Sounds Call for Platform-based Design at DAC 2013

Cadence CEO at DAC 2013: 'I've Doubled, Tripled Down on Semiconductor Investment'

Freescale CEO at DAC 2013: "Internet of Things" Brings Opportunities, Challenges

DAC 2013: Accellera Panel Updates Power Format Standards

rgoering — Thu, 06 Jun 2013 09:10:00 GMT

In what was billed as a "town hall meeting" about the new IEEE 1801-2013 (UPF 2.1) power intent format standard, the Accellera Systems Initiative sponsored a breakfast panel at the Design Automation Conference (DAC 2013) Monday, June 3. The discussion took a broader look at power intent formats, how they're used, and where they're headed.

At the beginning of the meeting, EDA standards veteran Stan Krolikoski -- distinguished engineer at Cadence -- received the annual Accellera Leadership Award. Krolikoski was a co-founder of Accellera in 2000, and today he serves on the board and heads the IP Rights Policy committee. Accellera chair Sishpal Rawat (right in photo) noted Krolikoski's long involvement with Accellera, the Open SystemC Initiative (OSCI), the Spirit Consortium, and the IEEE, where he serves as chair of the IEEE Design Automation Standards Committee (DASC).

Accepting the award, Krolikoski observed that "I really think we need a new generation of standards leaders to come forward. We're seeing a few people, but we're not seeing enough."

The panel was moderated by Ed Sperling of System-Level Design. The panelists had participated in an IEEE 1801-2013 tutorial held the day before. Panelists were as follows, shown left to right below:

Jeffrey Lee, Staff Corporate Application Engineer, Synopsys
Qi Wang, Solutions Group Director, Cadence
Sushma Honnavara-Prasad, Principal Engineer, Broadcom
John Biggs, Senior Principal Engineer, ARM (and chair of IEEE 1801 Working Group)
Erich Marschner, Verification Engineer, Mentor Graphics

Following are some notable excerpts from the discussion.

What's new in IEEE 1801-2013

Biggs: We took out some constructs that needed to be deprecated. We made some new additions. Syntax and semantics are a lot clearer and crisper now. We also have a new section on the attribution of pins and cells.

Marschner: This sounds like a laundry list of a lot of different things, and it is, but what may seem to be small changes improve a number of things. First, users have more fine-grained control over what their power strategy is. The second thing is the fidelity of the models. You can make sure what you specify actually represents the hardware.

Wang: More and more small companies are doing low-power design. What's most important is getting the methodology right. One thing we added in the 2013 version is an appendix that talks about methodology. This should be a very good start for people who have not been using a low-power flow.

What's driving adoption of power intent formats

Marschner: Over the last 30 years, HDLs [hardware description languages] have replaced schematics. The same thing is happening with power intent - there's a migration from ad-hoc methods towards standardized techniques.

Honnavara-Prasad: There's been an explosion in the number of power states. It's often in the 30s if not 100s. And more and more of them are software controlled, so it's not a HDL problem. It's a big challenge for verification.

Wang: To Sushma's point, verification will become a huge issue, and not just for functional verification but also for electrical verification.

Convergence between Unified Power Format (UPF) and the Common Power Format (CPF)

Biggs: Two years ago it was said that UPF and CPF are the same in every intent and different in every detail. But Si2 [Silicon Integration Initiative] has contributed the entire text of CPF to the IEEE, and Qi Wang of Cadence has been a significant contributor to the [IEEE 1801-2013] standard. I would not say we have format convergence, but there is a degree of methodology convergence.

Wang: The new standard does improve interoperability with CPF. What will make it most useful is if all the vendors support the new features.

Moving power intent beyond RTL

Marschner: Verification really ought to start in the front [of the design cycle]. If you wait, it will be a lot slower. You want to make sure you're making the right decisions for power management as early as possible in the flow. Today RTL, tomorrow we'll move up to the systems level.

Lee: We need to sit down in the next working group, for [UPF] 3.0, and see how we can move the standard so everyone can get that early power estimation.

What's next for IEEE 1801

Marschner: We are moving up the design chain to system-level power. We are moving forward with the next round of development in low-power model estimation. Anyone interested in participating in that process is welcome as a member of the committee.

Wang: We are talking with Si2 about their modeling approach. We can work together.

What you can do

Marschner: We need input from users, and if you would like to participate in the working group that would be great.

Honnavara-Prasad: I would encourage you to read the standard.

Note: If you want to follow this advice, IEEE 1801-2013 is available for free download through the IEEE 1801-2013 Get Program.

Richard Goering

Related Blog Posts

Insider Story of the New IEEE 1801-2013 (UPF 2.1) Standard

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

A CPF User Perspective on IEEE 1801 (UPF) "Methodology Convergence"

DAC 2013 Panel: What’s Needed to “Fix” Timing Signoff?

rgoering — Wed, 05 Jun 2013 01:54:00 GMT

Has timing signoff innovation become an oxymoron? What happened and how do we fix it? That was the provocative title of a Cadence-sponsored lunch panel at the Design Automation Conference (DAC 2013) June 3. Panelists from ARM, Altera, GLOBALFOUNDRIES, and Cadence talked about the challenges of timing signoff and discussed what's needed to make it work better.

Timing signoff is a hot topic right now. Two weeks before DAC Cadence introduced the Tempus Timing Signoff Solution, which includes a massively parallel timing engine that can scale to hundreds of CPUs, optimizes as well as analyzes, and provides accurate path-based analysis that is fast enough to be practical.

The panel was moderated by EE Times veteran Brian Fuller, who recently joined Cadence as editor in chief (you can read his new blog here). Panelists were as follows, shown left to right in the photo below:

Dipesh Patel, Executive Vice President for Physical IP, ARM
Tom Spyrou, Design Technology Architect, Altera
Richard Trihy, Director of Design Methodology, GLOBALFOUNDRIES
Anirudh Devgan, Corporate Vice President and General Manager, Silicon Signoff and Verification, Cadence

"Timing closure is one of the largest poles in the design flow today, with the increase in multi-mode multi-corner timing analysis views, the lack of closure signoff tools, and increasing variation," Fuller said. "We find ourselves in the middle of a paradigm shift. We need a new injection of technology."

Here are some excerpts from the conversation.

What are the main challenges with timing signoff?

Patel - Timing closure is taking up a huge portion of the design cycle. Some metrics say it takes 60% of the time. Reducing time to closure is the big challenge we're trying to solve.

Spyrou - With static timing analysis, people want three things - capacity, run time, and accuracy. Hierarchy is one way to approach these goals, but its context-dependent models are only good for one design. As designs get bigger, memory capacity will become more of a problem.

Trihy - From a foundry perspective the main issue is variation. You need to be able to control the margins. I'm not seeing very effective solutions for that.

Devgan - There are three main issues in signoff. They are speed and capacity, accuracy, and closure in terms of fixing things. One thing the EDA industry has to do better is to use parallel hardware.

Is timing signoff really an oxymoron?

Spyrou - No, there has definitely been innovation in timing. But there are still big problems getting designs out.

Trihy - Solutions have been proposed for different kinds of OCV [on-chip variation] and timing analysis. I don't think it's easy for the customer to design with these technologies.

Devgan - Innovation happens either in the commercial space or in academia. In the commercial space there has only been one solution for the last 20 years. In academia, a lot of papers were written, but I think they got too focused on features like statistical timing analysis that were not mainstream.

Why statistical timing analysis (SSTA) didn't catch on

Patel - One reason statistical analysis failed is methodology. Trying to create SSTA models from libraries, and use them in the flow, was incredibly complicated. Since then we've tried different things, including AOCV (advanced OCV) which has some context dependency. We need to come up with something context independent.

Trihy - It's true, generating libraries for statistical timing was painful. There was a huge investment on the part of the customer. But variation is here and is getting worse. We'll see how AOCV can help deal with variation problems.

How parallelism can speed timing signoff

Devgan - The hardware industry is going to massively parallel platforms. If you look at EDA, many tools are multi-threaded, which can only get you a low-level speedup. The maximum you can squeeze out is about 8 CPUs. If you redesign the algorithm rather than doing bottom-up multi-threading, you can scale much larger. This requires top-down parallelism rather than bottom-up multi-threading.

How has advanced node design changed the signoff challenge?

Trihy - Design flows didn't change that much down to 28nm, but at 20nm and beyond there are lots of new effects - double patterning, triple patterning, FinFETs - that really change the way you do design. Double patterning is a source of variation. With FinFETs, we are potentially seeing the Miller effect on steroids. The current drive is very high and the gate capacitance is larger.

Patel - We see the same effects - double patterning, the variability of metals. With FinFETs we've seen run times go up exponentially. You not only sign off IP at more corners, but time for each signoff is going up.

Spyrou - Because our fabric [Altera] is a regular structure, we don't have to depend on the accuracy of timing models. But at some point it would be good to have a static analysis tool that is "library-less" or that takes advantage of massive parallelism.

Devgan - I think accuracy will be a big problem. That's due to variability but it's also inherent when you drop the voltage to 0.5 or 0.6 volts, and things are no longer digital. The other thing is that the number of views is just absurd. OCV can solve some issues, but when there's variation with 100 corners, we have to handle things more intelligently than we've been doing.

The importance of optimization in signoff

Devgan - Signoff is not just analysis. I think signoff has to be able to fix, and fix in the right context. Having the same timer in place and route can help, but place and route is not signoff, it has different accuracy. The right answer is that signoff should have all the views and all the accuracy, and it should be able to fix in the physical context.

What's the connection between timing signoff and power?

Patel - For me, timing and power are linked. You can't have one without the other. We have to make sure any solution we deliver takes power into account.

Devgan - Timing and power should be done together from an analysis and signoff perspective. Right now I see power as mostly design techniques. Tools haven't contributed as much, and power analysis comes too late in the design cycle. The power number is pessimistic -- it's like a worst-case signoff number.

Spyrou - Delay calculation and noise analysis used to be separate, and now they're coming together with static timing analysis. Power consumption analysis and power grid analysis are still separate. In the future, I think power grid analysis will be part of timing signoff. Then eventually we'll bring in power consumption analysis, which is a harder problem.

If we hold the same panel two years from now, what will we be talking about?

Patel - I think we'll solve the MMMC [multi-mode, multi-corner] stuff, and the other thing I'd like to see is a new approach to OCV.

Spyrou - In the next couple of years enough people are working on memory scaling across CPUs that I think we'll see breakthroughs in that area.

Trihy - With AOCV or whatever method, I hope we have a solution. Other challenges may break the paradigm, if you look at FinFETs or double patterning.

Devgan - We just launched a tool [Tempus] and the next year will be very exciting for us. I think the industry has to solve the performance problem and the accuracy problem, and do the fixing in signoff.

Richard Goering

Related Blog Posts

Q&A: Anirudh Devgan Discusses New Cadence Signoff Strategy

Tempus - Parallelized Computation Provides a Breakthrough in Static Timing Analysis

Freescale CEO at DAC 2013: “Internet of Things” Brings Opportunities, Challenges

rgoering — Tue, 04 Jun 2013 00:01:00 GMT

The "Internet of Things" has become a common buzzword, but what potential does it bring, and what design challenges must be overcome to create it? Freescale president and CEO Gregg Lowe has done some serious thinking about these issues, and he shared his thoughts in an entertaining keynote speech at the Design Automation Conference (DAC 2013) June 3.

"The Internet of Things is not a stretch," Lowe said. "It's happening today. It kind of crept up on us and it's evolving at a very rapid pace." In 2010, he noted, the number of connected devices in the world exceeded the number of humans. According to some predictions, there will be 50 billion connected devices five years from now.

But this sea of smart devices raises some challenges. "If the Internet is going to reach everywhere, then embedded processing solutions need to get a heck of a lot smaller," Lowe said. One example is the Freescale Kinetis 32-bit microcontroller, an "ant size device that is moving us closer to the concept of digital dust."

Smart Diagnostics, Smart Energy

Lowe didn't dwell on the Kinetis, but he noted that the inspiration for it came from a customer who wanted to place a wireless diagnostic device into a pill that an individual could swallow. This could provide a high-quality video of the inner workings of the human body, resulting in significantly less invasive diagnostic procedures.

Another area of opportunity for the Internet of Things is "smart energy" in the home. Lowe observed that utilities are beginning to deploy smart meters that monitor energy consumption and improve distribution. Someday, Lowe said, as you leave work "the system will know you're on your way home. It will cool down your billiard room, put on some tunes, and crack open a cold one for you." (Well, maybe not the last one, but the first two are very possible, he said).

But automotive electronics are possibly the most dramatic example of the shift towards the Internet of Things. The car, said Lowe, is "the ultimate mobile device. Electronics makes cars more comfortable, greener, safer, and connected." Today the car industry is developing vehicle-to-vehicle communication that could be used to avoid accidents - warning of a car that's running a red light, for instance.

But what are the requirements for these advances? The Internet of Things will require cost-effective solutions for connected nodes that will access cloud-based services. The demand for bandwidth will "continue to explode" and solutions are underway that will be smaller, smarter, and more energy efficient, Lowe said.

Design Challenges

The primary challenge for the engineering community, Lowe said, is to increase performance while reducing energy consumption. He noted that half the energy consumed in datacenters is used to cool the heat generated by the datacenter itself. With a car, by some estimates, only 13% of the fuel actually moves the car forward. "IC designers will have to find a way to dramatically reduce power, or we'll have a whole bunch of connected devices that don't have juice to run."

As more smart devices connect to the Internet, security will also become very important. "The days of simple software bolt-ons are gone," Lowe said. "Security will need to be embedded at the hardware level and in the ICs themselves."

Lowe also noted that processor complexity is advancing faster than EDA tools. The challenge for EDA, he said, is to enable "deterministic circuits" with predictable performance. He suggested that new types of behavioral models could dramatically reduce power consumption by tapping into ideas like bio-synthetic deisgn, where "replicating the efficiency and massive parallelism of a cellular structure could make energy per bit a million times more efficient."

"I and the rest of this industry are counting on people in this room to rise to these challenges and come up with solutions that will move our industry forward," Lowe concluded. "Together we can unlock the potential of the Internet of Things."

For live coverage from DAC 2013, see our multimedia site.

Richard Goering

Other Cadence blog posts from DAC 2013

DAC 2013 - System Design on Monday, June 3rd

DAC 2013 -- Kaufman Winner Hu: FinFETs Will Serve Analog Design Very Well

Gary Smith at DAC 2013 - the $170M SoC Design is a "Myth"

Welcome to DAC 2013!

Gary Smith at DAC 2013 – the $170M SoC Design is a “Myth”

rgoering — Mon, 03 Jun 2013 02:47:00 GMT

Analyst Gary Smith of Gary Smith EDA is not afraid to tackle what he sees as myths and misconceptions. At his annual night-before-DAC talk at the Design Automation Conference Sunday, June 2, he debunked a "myth" that SoC design will become too expensive for all but a handful of large companies.

Smith also predicted an $8 billion EDA market (excluding services) by 2017, said the electronic system level (ESL) flow is nearly complete, and claimed that the EDA industry is well positioned to take over the embedded software business. But he acknowledged that the transition from RTL design to ESL is going more slowly than he had expected.

Smith said there are lots of rumors that SoCs are so expensive that the semiconductor industry as we know it won't survive. Nonsense, he said. "Look at the numbers for a change. Don't believe the rumors."

Things are Improving

The basic problem with the doom-and-gloom predictions, Smith said, is that those who spread them don't think things will improve. So what will chip design be like in 10 or 20 years? Today, performance is really viewed as latency plus power. Power budgets (such as 5 watts) are design constraints. Fortunately, according to the International Technology Roadmap for Semiconductors (ITRS), dramatic improvements in low-power design technology are in store between now and 2027.

Smith talked about maximum usable gates due to power constraints. In 2011 we could use 11% of the total available gate count (of around 200M); in 2027 we'll be able to use up to 93% of the available gates (of around12.7B). To explain why, Smith presented an ITRS chart that showed a number of improvements in design technology that are expected between now and 2027.These include the silicon virtual prototype, intelligent testbench, reusable platform blocks, heterogeneous parallel processing, and transactional memory.

Now suppose the cost of the design is $50M, adding another constraint. In 2027 a design team will be able to design up to 5 billion gates - not 12 billion, but "not bad." What about a startup with $25M in venture funding? They can come within both their power budget and their cost budget and design up to 3 billion gates in 2027, Smith said - and you can do a lot with 3 billion gates. The bottom line - semiconductor startups will still be able to compete.

"Predictions that design will cost $170 million are just wrong," Smith said. "Intel, maybe, but that's for a custom design. We are not in a design crunch. Designs are opening up."

Progress in the ESL Flow

Smith then talked about the ESL flow and how it's evolving. With the advent of the silicon virtual prototype, and the increasing use of transaction-based acceleration and emulation, it's all coming together, he said. Gary Smith EDA has come up with some seat counts. For example:

Silicon virtual prototype - 129,346
Software virtual prototype - 326,747
Architect's workbench - 17, 435

The "disconnect" in this flow is that architects don't have enough information to do proper power-aware hardware/software partitioning. This task gets handed off to the RTL engineers, and they're not familiar with software development. Smith said, in fact, that the transition to ESL "is not working out as I expected. Not many RTL guys are moving up to ESL because they're not capable of grasping the software side of it."

Smith said it will take another 10-15 years for RTL to "fade" into ESL. Fortunately, a new generation of younger engineers has a better understanding of software. He cited Cadence architect and blogger Jason Andrews as a "prototype of the new ESL software guy."

Smith said there's an opportunity for EDA to extend its influence into the embedded software development world. We have (or should have) the models that the architects and software developers need. "You can give away your tools, but don't give away your models," Smith implored the EDA community. "This is where we monetize the embedded software world."

"We'll replace the whole embedded world, which is suffering from poor financial performance due to the free Linux software kernels that are out there," Smith predicted.

Smith concluded with his Q2 2013 forecast of EDA growth. The prediction is one of steady growth. Here are his predictions (again, not including services) for the next few years:

2013 -- $6.1B
2014 -- $6.5B
2015 -- $6.7B
2016 -- $7.5B
2017 -- $8.3B

And there's plenty of room for EDA startups, Smith said. "This industry runs on startups."

There's a lot of good news for a lot of DAC 2013 attendees in Smith's talk this year.

Richard Goering

Cadence Multimedia Site Captures Spirit of DAC 2013

rgoering — Fri, 31 May 2013 21:09:00 GMT

Are you having to miss the Design Automation Conference (DAC 2013) this year, or unable to attend everything you'd like? One way to keep up with what you're missing is to tune into the Multimedia Channel at the Cadence DAC microsite. Starting Sunday June 2, you'll find live blogs, tweets, photos, and videos that bring you the excitement of DAC in real time.

A similar multimedia site was created for the CDNLive Silicon Valley conference, held in March 2013. This CDNLive site, located here, includes blogs, videos and photos. One thing that's new for DAC is live blogging provided through ScribbleLive. Live blogging provides a quick and interactive way to post short text items as well as photos and videos. We also encourage you to engage with us through our live blogging tool -- simply post your questions or comments directly to the feed, just as you would for social media channels such as LinkedIn and Facebook.

Of course, our Cadence Community blog posts will have a lot of DAC coverage extending throughout the month of June. And we're welcoming a new blog to the fold by veteran technology editor Brian Fuller, who worked at EE Times for the better part of 20 years before joining Cadence as editor-in-chief in May 2013. Brian's blog is named The Fuller View and his first blog post is available here. The blog will focus on issues affecting the electronics industry and the design chain.

Meanwhile, you can follow us on Twitter at @Cadence, and you can find DAC-related tweets by searching for #CDNSDAC13. The live blog feed will also pick up our tweets.

Again, the Multimedia Channel is located here. For a complete listing of Cadence activities at DAC, see our DAC microsite.

Richard Goering

Related DAC 2013 Preview Blog Posts

Cadence DAC 2013 and Denali Party Update

DAC 2013 - Cadence Customers, Partners Speak About Design Challenges and Solutions

DAC 2013: "IP Talks!" Shows What's New in Semiconductor IP

DAC 2013 - Software Driven EDA for the "Age of Gods"

DAC 2013 Panel: Where's the Innovation in Timing Signoff?

DAC 2013: Panel to Reveal FinFET Deployment Challenges

DAC 2013: User Perspectives on System-Level Verification