Hiroshi Ishikawa Blog

Introduction to Cadence Virtuoso Advanced Node Design Environment

Hiro Ishikawa — Mon, 28 Jan 2013 13:00:00 GMT

What can designers do about advanced node technology? This is an introduction to the Cadence Virtuoso Advanced Node design environment, announced Jan. 28, 2013, as a custom/analog design development environment for leading edge-advanced node technology.

Problems of Advanced Node Design

When designing with the most advanced node technologies including 22nm technology and beyond, you will encounter many new problems that no one could have anticipated from previous design work. New tools in the design flow need not require a completely new design flow. You should maximize the effectiveness of the current design environment. Then, you need to handle new problems appropriately and accordingly.

Generally speaking, you will need to pay special attention to the following things with advanced node design.

Multiple Patterning
Layout Dependent Effects (LDE)

o Length Of Diffusion (LOD) / STI Stress
o Well Proximity Effect
o Interconnect R, C, and inductance

Use of Local Interconnect Layers

Fig 1 (a) Length Of Diffusion (LOD)

Fig 1 (b) Interconnect layers

Fig 1 (c) WPE (Well Proximity Effects)

Fig 1(c) shows the WPE (Well Proximity Effect), one of the LDEs. The performance of the devices is different for 26db (~12x) depending on the placement locations of the devices from the edge of the well.

For advanced node design, those problems must be evaluated and considered in the design flow.

Current Design Flow

The current generic design flow that is mainly used for the 45nm and 32nm process nodes is shown in the following Fig 2. The current design flow represents the collected wisdom of many designers over many development processes. Indeed there is a big advantage of the current design flow because the designer has been familiar with it for a long time.

However, it is also true that the flow has the limitations listed below.

Each step is connected serially. When some steps have problems, many undesired iterations will be induced.
Automation is not used to its full potential.
Additional and incremental analysis during the design is not easy.
Hidden problems in the design including performance variance affected by LDE can go undetected until a very late phase in the design process.

The problems in the advanced nodes listed above all occurred with the previous technology, too. However, the reason that the current (existing) flow that is like the flow shown in Fig 2 is that the effects of those problems in the previous process technologies were very small, and they could be ignored. In the advanced technology required for 20nm or 14nm designs, those problems cannot be ignored. Therefore, the design process cannot be concluded unless designers detect these problems at an early stage of the design, and take necessary actions.

Also, the architectures of double patterning and Interconnect layers have already emerged in the previous technologies. However, these architectures will make a huge impact on performances of designs in advanced node technology. The design process itself needs to be re-evaluated for the advanced node design.

Fig 2. Current generic design flow

Therefore, an ideal design environment for advanced node technology is a design flow that allows the user to detect and resolve the non-ignorable problems in advanced node technology without invalidating the usability of the current design flow.

Cadence's design flow for advanced node technology

Fig 3 shows the design flow realized by Cadence Virtuoso Advanced Node design environment.

Fig 3. Cadence Virtuoso Advanced Node design environment for advanced node technology

At first, this flow does not require the user to change his current design flow. It has various enhancements for advanced node technology and inherits properties of the familiar, current design flow.

Several enhancements for advanced node technology are introduced below.

Analog Prototyping Step

In this step, the user can perform a simulation and consider the LDE before starting the actual layout. This is realized by prototyping the device layout, and simulating the design while considering LDE parameters. With this step, one can dramatically reduce the design modification work caused by performance gaps between the actual design after place and route is completed, and the initial simulation result.

It will work most effectively for considering the WPE (Well Proximity Effect) and performance effects caused by physical stress of the STI (Shallow Trench Isolation).

This step is very powerful because it not only shows LDE effects in a window, but it also allows the user to quickly check and verify characteristic changes due to LDE by running a simulation.

The following figure (Fig 4) shows this part of the step (Analog Prototyping).

Fig 4. Analog Prototyping

Module generation, Device placement Step

In the real design generation phase, the user can generate modules using Modgen and can place devices using the newly enhanced Pcells. Device placement work in advanced node technology is like pulling teeth. Very complex and rigid design rules need to be satisfied. Fig 5 shows sample complex-design rules related to the device placement. To effectively support those complex design rules, the Pcell abutment function in Cadence Virtuoso Advanced Node design environment was dramatically enhanced. The Pcell abutment function evaluates the relationship between the device to be placed and adjacent devices and realizes the best placements of devices automatically.

Fig 5. Example of complex device placement

Routing step

Routing work on the Local Interconnect Layer (LI) differs dramatically from the routing on the other routing layers. As the figure (Fig 6) shows, the LI layers exist between Metal1 and base layers. The layers allow contact-free connection. Also, the length and width of wires on the LI layers are tightly specified. The layers have very rigid constraints.

Fig 6. Local Interconnect Layers

In Cadence Virtuoso Advanced Node design environment, the user interface has been enhanced as well as the technology file so that the user can smoothly work on routing wires on the local interconnect layers (Fig 7).

Fig 7. Routing Environment for Local Interconnect Layers

Also, the DPT Assistant (Fig 8) can be used in Cadence Virtuoso Advanced Node design environment so that the routing can easily be done when considering double patterning architecture. The DPT Assistant immediately informs the user where in a design that double patterning conflict occurs.

Fig 8. Dynamic Coloring Assistant

Fig 9 shows the Odd-Loop Error Detection done by Virtuoso Integrated PVS (IPVS). In Cadence Virtuoso Advanced Node design environment, PVS, a sign-off level Design Rule Checker is fully integrated. It performs "Dynamic Signoff Checking" when a design is updated.

Fig 9. Odd-loop error detection

Conclusion

This document has been a quick introduction to new features that are available in Cadence's design development environment for advanced technology. The Cadence Virtuoso Advanced Node design environment is the brand-new design environment that not only supports each new requirement but also integrates new steps into the existing design flow without needlessly disrupting that flow.

Also, the biggest and hidden advantage of this design flow is that software will obviate the possible design problems inherent in advanced node design even if the designer is unaware of these new problems. As the result, the flow can minimize undesired iteration in the design process that was the limitation of the previous design flow. This "Correct-by-Construction" approach realized by Cadence Virtuoso Advanced Node design environment can dramatically reduce the entire design turnaround time.

Hiroshi Ishikawi

Improved IDF Tool Automatically Fixes Design Rule Violations in Virtuoso

Hiro Ishikawa — Tue, 13 Dec 2011 19:00:00 GMT

Although many automatic layout generation tools are available to automate design creation, the layout modification/correction step (fixing design rule violations) is not automated very well. Consequently, design modification including error correction typically needs to be done manually. A good solution to automate the layout modification/correction step can be provided by a layout optimization tool that optimizes the areas containing design rule violations in a layout, and fixes the violations automatically. Such a capability is provided by the Interactive Design violation Fixing (IDF) tool that was first provided in the Virtuoso IC6.1.4 release.

The primary advantages of IDF are:

1. Only required areas are modified and corrected (nothing will be changed outside of the selected areas.)

2. It can be called any time in any design phase (even if the layout has not been finalized.)

3. Quality of the modified layout is stable (the results won't vary according to engineers' experience or design manner.)

As the first step to realize the above requirements, IDF was implemented in our IC6.1.4 software release by freezing (not changing) details outside of specified areas. (Fig 1)

Fig 1. IDF- IC6.1.4 (freeze outside of the area to be optimized)

Although the IDF in IC6.1.4 worked very well, freezing areas around the area to be optimized had the following two limitations:

1. It takes long time when a design is big because the entire layout data needs to be loaded on the dynamic memory.

2. When multiple areas are selected, one optimization failure ("infeasible") causes the optimization failure of all selected areas. (All areas must be optimized at the same time since optimizing a design means generating a result that satisfies all requirements simultaneously.)

Therefore, IDF needed to be enhanced so that automated layout modification/correction worked regardless of the design size, and without infeasible results interrupting the flow. In the latest release, IC6.1.5, the IDF has successfully been enhanced to realize the above requirements.The solution to the problem is applying the automated correction (IDF) only to the affected region. The areas to be optimized from a design are extracted. Then, the extracted areas are sent to the IDF engine one by one (Fig. 2)

Fig 2. IDF in IC6.1.5

IDF works very fast in most cases because the size of the data is very small. The following table compares benchmark results of IDF in IC6.1.4 and in IC6.1.5. IDF in IC6.1.5 finishes all error fixing within 1 minute.

Table 1. Runtime comparison (Frozen Donut Area vs. Area Segmenting Method)

Unit [h:m:s]

Design	Size (um x um)	# of Design Rule Errors	IDF in IC6.1.4	IDF in IC6.1.5
Stdcell MX2X1	2.61x2.61	1	3s	1s
Stdcell DLY1X4	4.06x2.61	1	2s	0.5s
Stdcell ADDFX1	7.54x2.61	2	2s	0.5s
CustomDigital 1	15 x 15	7	3min 52s	4s
Analog 2	4.5 x 6.5	8	4s	1s
Analog PLL	650 x 550	30	> 2hours ^*1)	30s ^*2)

Note:

*1) Job was terminated during constraint generation phase.
*2) 2 Infeasible results were reported.

Runtime (User time) was measured.
Test Machine:
VMWare Virtual Machine
Redhat Linux 4
RAM: 1 GB

Physical Machine:
Dell Laptop PC M65
CPU :Intel Core 2 CPU 2.16GHz
RAM : 3.25 GB
OS Windows XP SP3

Figure 3 shows the biggest design used for this benchmark test.

Fig. 3 Analog PLL design 650um X 550um（# of DRC Errors 30 -> 2 : runtime = 30sec)

This approach (loading only the specified area) allows the following benefits:

No design size limitations
Very fast
Non-stop optimization despite some infeasible results

IDF in IC6.1.5 works effectively for medium / large designs. It can also handle designs of chip-level complexity. Because each optimization task is discrete, the flow does not become interrupted by an infeasible result error. Also, the runtime is very fast, since the size of each extracted cell tends to be small.

Actually, IDF in IC6.1.5 consists of multiple small IDF fixes in IC6.1.4. Because a huge amount of design time is wasted on inefficient manual modifications, IDF in IC6.1.5 is a great solution to correct errors. IDF in IC6.1.5 is the answer to industry’s demand for automatic error correction.

Hiroshi Ishikawa

Sr. Engineering Manager, Physical Design
San Jose R&D, Custom IC, Silicon Realization Group

Optimization Environment Enables Effective Reuse of Existing Design Modules

Hiro Ishikawa — Fri, 26 Jun 2009 13:00:00 GMT

In order to complete a brand new design on time, it is an important factor to effectively reuse existing design modules. The use of an automatic optimization quickly and easily increases design reuse efficiency. The following figures are examples of a source layout and an optimized result made by Virtuoso Layout Migrate. Virtuoso Layout Migrate optimizes a design automatically by satisfying design specific constraints. The shape of the source layout can be maintained in the optimization result perfectly.

Before Migrate

After Migrate

One important issue that we need to carefully consider is how easily the result can be obtained. Even though the high quality optimization is possible, it would be useless if a lot of work is required to get it.

Cadence’s Virtuoso_XL, and GXL automatically extracts design constraints including Symmetry placement required for a design optimization from connectivity information in a schematic view and delivers them to a layout view via Constraint Manager. The design constraints delivered to the layout view will be applied as well as constraints added by a user manually during the optimization.

This optimization flow is as follows.

The following Fig 1-a shows the contrarians extracted by Circuit prospector. Fig 1-b is a migration result with respecting the design constraints extracted by Circuit prospector, and added by the constraint manager.

Fig 1-a. Automatic design specific constraints extraction by Circuit Prospector

Fig 1-b. Automatic design constraints addition via Constraint Manager (Schematic -> Layout)

Cadence Virtuoso XL, GXL can easily and automatically achieve extracting, maintaining, and applying complex design specific constraints that was "impossible" a decade ago. Cadence is only company offers robust, and comprehensive integrated design re-use flow in Virtuoso XL, GXL.

Hiroshi Ishikawa