https://community.cadence.com/searchen-USTelligent Community 11https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59537/circular-arrays-in-layout-lFri, 07 Jun 2024 23:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59537rb1993/cadence_technology_forums/f/custom-ic-design/59537/circular-arrays-in-layout-l0 Hello all, I am new to cadence platform. I have an entity (linear array of rectangles) that I want to replicate in a circular form (say 10 degrees apart). create an array that follows a circular path around origin. What is a quick and easy way to do this? https://community.cadence.com/cadence_technology_forums/system-analysis/f/clarity-3d-solver/59536/how-display-near-and-far-field-plots-in-clarity-3d-solverFri, 07 Jun 2024 17:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59536SimTech/cadence_technology_forums/system-analysis/f/clarity-3d-solver/59536/how-display-near-and-far-field-plots-in-clarity-3d-solver0 Starting with Clarity 2024.1 Release, the near and far-field results have been consolidated under a common GUI in both Clarity 3D Layout and Clarity 3D Workbench. The consolidated GUI lets you view the Near Field, 2D Far Field, and 3D Far Field plots which is useful in debugging large and complex structures. You can display the mesh using the following steps. . Near Field: After the simulation, right-click on Field-Plot from Project > Results and select Field Plot as shown below. If MagE is the Field option, it will display the E Field as shown below. You can use the Parts Selector tab to select the metal parts and uncheck parts for better visualization. Far Field: In the Field Canvas , choose Far Fields > 3D . Then, right-click 3D and select Add 3D Plot . It will open the Far Field pattern, as shown below. Team SimTech Cadence Design Systems https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59535/are-the-schematic---spectre-names-mapping-valid-when-a-netlist-of-a-subckt-is-attached-to-the-test-benchFri, 07 Jun 2024 15:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59535MFahmy/cadence_technology_forums/f/custom-ic-skill/59535/are-the-schematic---spectre-names-mapping-valid-when-a-netlist-of-a-subckt-is-attached-to-the-test-bench0 Hi, After creating the maestro testbench netlist using the "maeCreateNetlistForCorner" command, I am using a post processing script to replace some subckts of given subblocks (for example subckt of blockA is replaced with a modified subckt of that block) in the netlist, followed by running the simulations, now as the contents of this sub-block (instances and their respective subckt names and definitions) has changed, would this invalidate the "amap" data ? how to ensure that when opening the results, the evaluation of the schematic names would be still correct, or what would need to be modified in the amap data, I would also appreciate some extra information or a pointer to documentation on how spectre to schematic name mapping is done while evaluating the results expression and how can to ensure this is correct if the simulations are done from through a spectre cmdline "virtuoso version ICADVM20.1-64b " "sub-version ICADVM20.1-64b.CUSTISR33.24 " Thanks, Fahmy https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59516/ic618-vs-ic231/1398618#1398618Fri, 07 Jun 2024 13:47:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398618cato/cadence_technology_forums/f/custom-ic-design/59516/ic618-vs-ic231/1398618#1398618 OK, thank you! https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/59531/verilog-ams-xcelium-version/1398617#1398617Fri, 07 Jun 2024 13:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398617IssacW/cadence_technology_forums/f/mixed-signal-design/59531/verilog-ams-xcelium-version/1398617#1398617 hi Saloni, thanks for your tips. this approach works and shows again 21.03-s009. also the tricky point is simulator=ams still doesn't work ...... https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59516/ic618-vs-ic231/1398616#1398616Fri, 07 Jun 2024 13:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398616Saloni Chhabra/cadence_technology_forums/f/custom-ic-design/59516/ic618-vs-ic231/1398616#1398616 IC231 is the next stream of Virtuoso releases (after IC618), so same licenses will work, unless you want to use a new product feature. https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/59531/verilog-ams-xcelium-version/1398615#1398615Fri, 07 Jun 2024 13:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398615Saloni Chhabra/cadence_technology_forums/f/mixed-signal-design/59531/verilog-ams-xcelium-version/1398615#1398615 A simple way to check is to bring up a terminal from Virtuoso. You can type this in CIW: > system("xterm &") Now, you run 'xrun -version' in this terminal - do you still see 21.03-s009? https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59534/changing-transient-simulation-step-size-during-the-simulation/1398614#1398614Fri, 07 Jun 2024 13:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398614Saloni Chhabra/cadence_technology_forums/f/custom-ic-design/59534/changing-transient-simulation-step-size-during-the-simulation/1398614#1398614 Yes, you can do this by changing errpreset or steppreset (if using SpectreX) through dynamic parameter. The article below explains this, let me know if you are unable to view it: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009fo7PEAQ&pageName=ArticleContent https://community.cadence.com/cadence_blogs_8/b/cic/posts/virtuoso-studio-_2d00_-how-do-you-name-simulation-histories-in-virtuoso-ade-assemblerFri, 07 Jun 2024 12:16:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1363065NamrataM/cadence_blogs_8/b/cic/posts/virtuoso-studio-_2d00_-how-do-you-name-simulation-histories-in-virtuoso-ade-assembler0 Our new AI-powered custom design solution, Virtuoso Studio, leverages our 30 years of industry knowledge and leadership, providing innovative features, reimagined infrastructure for unrivaled productivity, and new levels of integration that stretch beyond classic design boundaries. In this blog series, learn how the best analog design tools just got better to help you keep pace with your challenging design issues. Using meaningful names, grouping, and sorting items are some well-known ways of staying organized. These simple actions make it easier to save, search, and fetch data! The same is true for simulation histories saved by Virtuoso ADE Assembler. Your design simulation and optimization requirements might require you to run multiple simulations for the same cellview with different run modes. The question arises: How do you name the histories saved by the simulation runs to keep them organized? You must be aware that ADE Assembler already provides settings to use separate pre-defined or custom names for histories saved for each run mode. For example, all simulations for Monte Carlo Sampling run mode are saved in histories named with the MonteCarlo. prefix by default. However, you can modify this default value by using the "adexl.historyNamePrefix" "monteCarloSampling" environment variable. envSetVal("adexl.historyNamePrefix" "monteCarloSampling" 'string "dsgn1_MC_June24") There are more environment variables that similarly set the default history prefixes for different run modes. We bet that is how you have been configuring the default history prefixes in ADE Assembler. How about changing the history prefix for runs from within the tool right before a simulation run? Yes, that was possible by using the Specify History Name form that could be displayed by setting an environment variable. However, it required you to specify a custom name before each run, which would have been a little inconvenient. The new History Name toolbar removes all those hassles and retains the custom name you want to use for all simulations run from a maestro cellview. All you need to do now is to toggle between the default or a custom history name for the next simulation run. For this, you can use the button highlighted below. By default, the History field on this toolbar shows the default prefix set for the current run mode. If you want to use a different prefix, click the Change between default and custom history name button and specify a custom prefix. The next simulation will use that custom prefix while saving the history. By using this feature, you can conveniently specify different prefixes for the histories saved for a maestro cellview. Next time you run a simulation, do try this new way to specify a custom prefix for histories. You will surely find it useful! Related Resources Virtuoso ADE Assembler User Guide For more information on Cadence circuit design products and services, visit www.cadence.com . Contact Us For any questions, general feedback, or even if you want to suggest a future blog topic, write to custom_ic_blogs@cadence.com . Happy Reading! Namrata Malhotra https://community.cadence.com/cadence_blogs_8/b/fv/posts/usb4-version-2-0-gen4-link-recoveryFri, 07 Jun 2024 12:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1363103Neelabh/cadence_blogs_8/b/fv/posts/usb4-version-2-0-gen4-link-recovery0 USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in asymmetric mode. Here, we take an overview of the Gen4 link recovery mechanism, which is an autonomous process. It is initiated by a router when it encounters uncorrectable error events. These error events could be a timeout error, de-skew buffer error, or RS-FEC decode error. Gen4 link recovery uses the newly defined ELT_recovery transaction of the sideband channel. This transaction is used for both Gen4 Link Recovery initiation and completion. A router sends ELT_recovery transaction if there is an error case that requires Gen4 link recovery, or it receives ELT_recovery transaction, or ‘Initiate Gen 4 Link Recovery’ bit in PORT_CS_19 is set to ‘b1. Gen4 link recovery preserves the current configuration space and the router states. It would also stop time-sync handshakes and transport layer scheduling, but other than that, it would stop idle packets. An ELT_recovery transaction is sent on the sideband channel to the other router. When the other router receives this ELT_Recovery transaction, it also sends an ELT_Recovery Transaction back to the initiating router. Once the last bits of ELT_recovery transactions are sent and received, the router starts the lane initialization from phase 4, but the last set of TxFFE parameters are used prior to Gen4 link recovery without performing the TxFFE negotiation flow. Once the link is active again, the router with the downstream facing port on the recovered link sends a link recovery Notification Packet. It is important to note that Gen4 link recovery takes precedence over all other flows except for Disconnect. Hence, in cases when the conditions to initiate Gen4 link recovery are met but if either the value of the ‘Target Asymmetric Link’ field does not reflect the actual negotiated link width as described in the ‘Negotiated Link Width’ field or ‘Enable Gen4 Link Recovery’ bit in PORT_CS_19 is set to ‘b0, a disconnect is initiated instead by driving Sideband TX to a logical low. Verification of Gen4 Link Recovery gives rise to a large scope, which should be covered for various combinations. It is applicable whether the link is symmetric or asymmetric. Within an asymmetric link it can happen whether the router is in 3Tx or 3Rx. It can also happen during the CL0s state or during the process for entry and exit for CLx. One needs to carefully test out all the combinations of symmetric/asymmetric with 3Tx/asymmetric with 3Rx, with all possible FSM flows, along with different ways of error insertion and recovery via both Gen4 link recovery or disconnect due to it not being enabled. To achieve all of this, the user should be able to generate conditions for injecting the right kind of errors, like RS-FEC error or de-skew buffer error with any type of link. Also, the user should be able to detect such errors and the consequent link recovery flow and get the protocol traffic up and running after it. Cadence USB4 VIP provides capabilities for all such aspects of Gen4 Link Recovery verification. Cadence has a mature Verification IP solution for the verification of various aspects of USB4 Version 2.0 and Version 1.0 design, with verification capabilities provided to do a comprehensive verification of these. You may refer to https://www.cadence.com/en_US/home/tools/system-design-and-verification/verification-ip/simulation-vip.html for more information. https://community.cadence.com/cadence_technology_forums/computational-fluid-dynamics/f/marine/59478/maneuvering/1398612#1398612Fri, 07 Jun 2024 09:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398612Benoit Mallol/cadence_technology_forums/computational-fluid-dynamics/f/marine/59478/maneuvering/1398612#1398612 Oh I see, thanks. In that case, what we propose is the following: for a static drift, the ship does not have to rotate around its gravity center. However, it is moving in X and Y directions. That's the way to impose an angle with the flow. In terms of values, you should not impose an angle such as degree or radian but knowing the angle with the flow and the speed in X direction, you can compute the required velocity in Y direction, that will be imposed through Ty. You can impose the same ramp duration for both Tx and Ty. I hope I was clear enough. Best regards, https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/59497/i-wanted-create-void-on-holes-as-using-my-code-its-removing-the-shape-dbid/1398611#1398611Fri, 07 Jun 2024 09:27:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398611Hoangkhoi/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/59497/i-wanted-create-void-on-holes-as-using-my-code-its-removing-the-shape-dbid/1398611#1398611 Hi ! try this code (defun for_cut_voidshape () airgap = "5";axlFormGetField(form "airgap") net_name = "VSS"; axlFormGetField(form "net_name") void_size= "200";axlFormGetField(form "void_size") airgap = atoi(airgap) net_name = upperCase(net_name) void_size = atoi(void_size) antipad_half = void_size/2 axlSetFindFilter(?enabled '(noall VIAS SHAPES NAMEFORM) ?onButtons '(noall ALL)) axlSelect() l_shapes = setof(e axlGetSelSet() e->objType =="shape") l_vias = setof(e axlGetSelSet() e->objType =="via") axlClearSelSet() temp_list = nil foreach(via,l_vias foreach(shape, setof(e l_shapes e->net == via->net) tmp = shape->segments foreach(void shape->voids foreach(seg void->segments tmp = cons(seg tmp2) ) ) foreach(seg tmp gap = axlAirGap(via seg seg->layer) if(gap != nil && caddr(gap) xy) r_path = axlMakeDynamicsPath(list(list(d d 0.0 via->xy antipad_half t) list(d d) ) ) poly = car(axlPolyFromDB(r_path ?layer shape->layer ?endCapType 'ROUND)) if(member(poly temp_list) == nil then temp_list = cons(poly temp_list) ) ) ) ) ) foreach(poly temp_list axlClearSelSet() axlSetFindFilter(?enabled '(noall SHAPES NAMEFORM) ?onButtons '(noall ALL)) axlSingleSelectBox(poly->bBox) shape = car(axlGetSelSet()) openShape = axlDBOpenShape(shape->shapeBoundary) axlDBCreateVoid(openShape, poly) axlDBCreateCloseShape(openShape) ) ) HoangKhoi. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59534/changing-transient-simulation-step-size-during-the-simulationFri, 07 Jun 2024 08:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59534AmirMasnadi/cadence_technology_forums/f/custom-ic-design/59534/changing-transient-simulation-step-size-during-the-simulation1 In virtuoso ADE transient simulation, I know we can change parameter values during a transient simulation at a given time using Dynamic Parameter feature. Is there any way to change the simulation step size during the simulation ? For example lets say I am simulating a PLL for 3us and for the first 2us I want low accuracy time step size (e.g. liberal sim) and for the last 1us of simulation I want to have a very high accuracy step size (e.g. moderate or conservative) , is there any way to change the step size at a given time frame ? https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/59533/syscap-tip-of-the-week-placing-multisection-part-on-schematicFri, 07 Jun 2024 06:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59533DesignTech/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/59533/syscap-tip-of-the-week-placing-multisection-part-on-schematic0 System Capture offers a unique feature to let you place other sections of a multisection part. There is no need to select other symbols manually after placing the first symbol/section of the part. Just enable the settings in Edit > Preferences > General > Schematic . Click OK to save the setting. Now, try placing the multisection part on the schematic. It will place all sections of the selected part on the canvas with every mouse click. Team DesignTech Cadence Design Systems https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/59532/units-of-parameters-in-lossy-transmission-lines/1398610#1398610Fri, 07 Jun 2024 05:56:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398610TechiEE12/cadence_technology_forums/pcb-design/f/pspice/59532/units-of-parameters-in-lossy-transmission-lines/1398610#1398610 For a l ossy line, LEN is the electrical length. R, L, G, and C are the per unit length values of resistance, inductance, conductance, and capacitance, respectively. LEN is electrical length. It can be in any unit, like feet, meters etc. If LEN is in meter, R unit would be Ohm/meter and so on. Similarly L would be Henry/meter. Hope this helps. https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/59532/units-of-parameters-in-lossy-transmission-linesFri, 07 Jun 2024 03:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59532Zhengzhi Wang/cadence_technology_forums/pcb-design/f/pspice/59532/units-of-parameters-in-lossy-transmission-lines1 I am trying to use the lossy transmission line model in PSpice. As shown in the figure, the key parameters are C, G, L, LED, R. What are their units? https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59530/why-can-not-get-the-display-property-of-a-part-with-tcl-script-in-orcad/1398609#1398609Fri, 07 Jun 2024 02:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398609Jadystone/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59530/why-can-not-get-the-display-property-of-a-part-with-tcl-script-in-orcad/1398609#1398609 Great Thanks ! I get it. https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/59497/i-wanted-create-void-on-holes-as-using-my-code-its-removing-the-shape-dbid/1398608#1398608Fri, 07 Jun 2024 01:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398608eDave/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/59497/i-wanted-create-void-on-holes-as-using-my-code-its-removing-the-shape-dbid/1398608#1398608 This might help: Note that you need to open the shape after all the other processing of the shape. defun( monro (airgap, net_name, void_size) l_layers_visible = '("ETCH/TOP") net_name = upperCase(net_name) antipad_half=void_size/2.0 axlSetFindFilter(?enabled list("noall") ?onButtons list("noall")) axlSetFindFilter(?enabled list("VIAS" "SHAPES") ?onButtons list("VIAS" "SHAPES")) axlSelect() l_vias = setof(obj, axlGetSelSet(), obj ->objType == "via" && obj ->net ->name == net_name) l_shapes = setof(obj, axlGetSelSet(), obj ->objType == "shape" && memv(obj ->layer, l_layers_visible)) axlClearSelSet() foreach(shape, l_shapes l_poly_shape = axlPolyFromDB(shape) voidPolys = nil foreach(via, l_vias list_shape_layer = unique(setof(obj, axlDBGetConnect(via t), obj ->objType == "shape") ~>layer) l_airgap = axlAirGap(via, shape, shape ->layer, 'enhanced) airgapsize = l_airgap ->airGap || 0.0 when(!memv(car(l_layers_visible) list_shape_layer) && airgapsize xy, antipad_half) rpath = axlPathStartCircle(l_location, 0.0) poly_circle = car(axlPolyFromDB(rpath)) voidPolys = cons(poly_circle, voidPolys) ) ) openShape = axlDBOpenShape(shape->shapeBoundary) foreach(poly, voidPolys axlDBCreateVoid(openShape, poly) ) shape = car(axlDBCreateCloseShape(openShape)) axlShapeDynamicUpdate(shape t) ) ) https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59513/shape-to-void-conversion/1398607#1398607Thu, 06 Jun 2024 23:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398607masamasa/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59513/shape-to-void-conversion/1398607#1398607 thank u for ur reply. this feature on the property is the one u told me years ago and i use it frequently. i have a design with a void in which about a thousand of pads created by shapes exist. i guess i have create the void manually. regards masa https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59496/exporting-sub-drawing-with-saved-query/1398606#1398606Thu, 06 Jun 2024 23:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398606masamasa/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59496/exporting-sub-drawing-with-saved-query/1398606#1398606 thank u for ur reply. i hope u can add this feature on the next version. regards masa