Andreas Lenz Blog

Re: Differences between pins from digital and analog views of a schematic

AndreasLenz — Tue, 22 Jan 2013 18:06:37 GMT

Hello -G,

which IC and EDI version do you use ? Since you're talking about layout views I assume you work on an Open Access Database.

Is you're PDK Mixed Signal enabled - means do you have your technology LEF available as an OA library referencing the Base PDK?

Cheers

Andreas

Re: Export LEF via problem

AndreasLenz — Mon, 07 Jan 2013 09:55:59 GMT

Hello Gangadhar,

Did you manage to export a LEF from Virtuoso meanwhile? Does the view name exist (please check with the library manager) ?

The LEF export uses the foundry section of the technology library - is the via defined ? You could use CIW - Technology Manager - Dump to write out an ASCII text file and search for the via.

Regards,
Andreas

Re: Config files

AndreasLenz — Wed, 21 Nov 2012 09:40:47 GMT

What tool version do you intent to use?

The lib.defs isn't needed using EDI11. The cds.lib file is read in automatically using the open Access database.

Cheers

Andreas

Re: open the GUI

AndreasLenz — Mon, 19 Nov 2012 08:52:40 GMT

You can't open a GUI starting with nowin. The graphic initialization doesn't happen if you start with -nowin. Alternative start encounter without nowin, use the win off command to disappear the GUI and win to raise it again.

Cheers

Andreas

Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes

AndreasLenz — Thu, 15 Nov 2012 14:00:00 GMT

Are you working in the area of mixed signal?

Then you may want to exchange information and experiences with other engineers.

At the Cadence Community, a new Mixed-Signal Design Forum has been launched, providing a place to discuss topics that cross between analog and digital domains.

It doesn't matter if you're just starting with mixed-signal design, or you have a lot of experience. This is a customer-driven forum that allows you to get in touch with other engineers, ask questions, and discuss a wide variety of mixed signal topics. You can use your Sourcelink account to set up a forum subscription.

Are you interested in learning more about mixed-signal implementation?

In this case the Mixed Signal Analog on Top training might be appropriate for you. It's a three day training that instructs you in mixed-signal Implementation design techniques using the Cadence Encounter and Virtuoso platforms.

Day 1 - Introduction to Encounter for analog engineers, to get an understanding of how the digital implementation works.
Day 2 - Mixed-signal introduction with respect to Analog on Top (AoT) OpenAccess database preparation. Understanding the Incremental Technology Database (ITDB) and Virtuoso mixed-signal floorplanning. Design interoperability using OpenAccess and digital implementation with Encounter.
Day 3 -- Data exchange from Encounter back to Virtuoso. Using power aware CPF techniques in Virtuoso chip assembly and top level routing. Full timing model and analog top level static timing analysis (STA).

The training is based on the latest IC615 and EDI11 tool releases.

Getting interested?

Find out more at Cadence Training overview and select the training course applicable for you, or contact your local Cadence training department.

Kind regards

Andreas Lenz

Re: Virtuoso Library size limit

AndreasLenz — Thu, 15 Nov 2012 12:21:16 GMT

Hello Vipin,

The number of objects handled in one single directory is limited.

If you would like to increase the number of objects in a directory try strmin -help and you find a variable named maxCellsInTargetLib.You could increase this variable up to the limit defined by the LINK_MAX of your system. The default setting as implemented in Virtuoso is 20.000.

Regards,

Andreas

Re: writing out a .vcd file from spectre

AndreasLenz — Tue, 13 Nov 2012 12:36:18 GMT

Hello Geezmaneti,

even if this Forum might not suitable for your request (I would try functional verification) I might be able to help you.

Did you looked into SimVision already? Here you're able to write out a vcd file as shown below:

From the menu choose export and change the database format.

Managing Inherited Connections with CPF in Virtuoso

AndreasLenz — Wed, 23 May 2012 17:10:00 GMT

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso.

Why use CPF?

The Common Power Format (CPF) describes the design power intent for the whole flow, including digital implementation in Encounter, custom/analog implementation in Virtuoso Schematic Editor, and further into simulation. In Virtuoso Schematic XL, CPF creates the inherited connections for you in an automated way. You may want to reuse the same CPF that was used for your digital block implementation in Encounter.

What might CPF contain?
- Power domains with their shutoff conditions if applicable
- Power and ground nets
- Technology for low power: isolation cells, level-shifters (need to be registered as special cell in Virtuoso)
- Isolation, shifting and retention policy
- Power modes and analysis views
- Library sets
- Global connection

What does CPF not contain?

CPF is not a command file. It doesn't contain power domain coordinates, power routing details, number of power switches, or implementation details.

How can I handle the inherited connections ?

Within the Virtuoso IC 6.1.5 release it is possible to describe your low power intent through a CPF file. This posting describes the method according to the use model described above. Further information, including supported CPF commands, is available in the Virtuoso Schematic XL User Guide.

What are the requirements?

A consistent power intent for the analog and digital parts of your design is required. You could have explicit power pins and implicit net sets and net expressions defined in parallel. CPF will update or create the net sets and expressions.

All of the power and ground nets (PG nets) in your design should have the signal type Power or Ground. The default signal type is Signal. This might be the case if you take a closer look at your standard cell library. Power and Ground nets are very often defined as type signal. Another requirement is that your standard cell power connection must be described as an inherited connection. Before you start, make sure that the CPF created is verified for correctness using the Cadence Conformal Low Power product.

And as mentioned before, you need Schematics XL to make use of CPF.

Step by Step introduction

Setup Schematics XL

After Verilog import Open Check - Rules Setup - Inherited Connections and enable the CPF nets error switch.

To verify the signal types choose Options - Check and enable "set Signal Type from Net and Type Registration."

Applying the right signal type

As mentioned above, we need to make sure to set the right signal type. Descend in the hierarchy by double clicking on a symbol until the standard cells occur. Are your PG nets defined as inherited connections, but the signal type is Signal? If so you need to change it. Because your standard cell library usually is set to read only, we need to change the cells in your design using the register API to provide a complete list of all your PG nets (don't miss the std cell PG nets):

ciRegisterNet("power" list("VDD" "vdd" "VDD!" "VDDA" "VDDD" ....) )

ciRegisterNet("ground" list("VSS" "vss" "VSS!" "GND" "gnd" ....) )

Now check if the PG Signal type gets applied correctly:

ciGetNetNames("power") ciGetNetNames("ground")

Finally we use the Check - Hierarchy command to propagate the changes to the schematic. Don't enable save schematics since you may don't have write access to the Library

Shortcut: schHiCheckHier()

Import the CPF file

Open "File - Import Power Intend" or type schHiAddCPFNetSets() in the CIW command line to open the CPF import form. Library, Cell and View Name are already filled in. The View Name List may be changed by adopting by editing "Options - Check - Views to check.

Specify your CPF File name

Use ‘Register Special Low Power cells' for Isolation cells , Level shifter cells, Power switches, ...Use ‘Remove existing Power Intend' if you are not sure which power is defined and you want to rebuild the power connection. The alternative is to use "Edit - Power Intend - Remove netSet properties." The progress is logged in CIW and CDS.log files.

Again, the last step is to propagate the power intent through the hierarchies and we use "Check - Hierarchy."

Verify the power intent

After importing and applying the CPF file you may want to verify the created power intent. To verify the created power domains, rules, mappings ... Enable "Window - Assistant - Power Intend Export" for a review.

To verify the created inherited connections on a specific instance open "Edit- Net Expressions - Available properties" and select a block or instance.

If you want to verify the evaluated names from net expressions open "Edit- Net Expressions - Evaluated Names." In case you want to review which instances are connected to a PG net, use the Search assistant to search for a net and check the User properties.

Kind Regards,

Andreas Lenz