Broadcom Presentation Shows Value of Transaction-Based Acceleration

rmathur — Tue, 16 Nov 2010 14:00:00 GMT

Wow - what a paper! At CDNLive! Silicon Valley 2010, the joint paper from Broadcom and Cadence, titled Transaction-Based Acceleration: Strong Ammunition in any Verification Arsenal, showed evidence that simulators are running out of steam for system level simulations. At Broadcom, simulators certainly maintain their value from sub-block to chip-level simulations, providing their users with tremendous debug and ease-of-use efficiencies. However, the lowered performance profile for simulations at the system-level are impeding Broadcom's ability to meet their tight schedules while verifying and producing high-quality products. After evaluating several verification solutions available in the marketplace, Broadcom has now added transaction-based acceleration to their verification arsenal.

On some of their initial results using transaction-based acceleration, Broadcom achieved 230X acceleration over a chip-level simulation. Even at block level, they ran a 1.2 million packet tests at a rate of 304 packets per second, achieving 292X over simulation. Not too shabby! In addition, they've improved their return-on-investment of their hardware assisted verification solution with Palladium by extending its value from in-circuit emulation to include transaction-based acceleration technology.

I believe Broadcom is not alone in this respect. Many verification managers at other companies have told me that they are developing their verification test plans hampered by the performance of their simulators at the system level. So, if they too can run system level simulation much faster than their current simulator allows them to, yet maintaining the usability and methodology defined by simulator vendors, their tight verification schedules can be met with high coverage, allowing application software validation to take place at earlier stages.

By the way, a related yet still a side note regarding Broadcom -- the following was mentioned during Cadence's 2010 Q3 earning's call. Broadcom selected the Palladium XP for in-circuit emulation, transaction-based acceleration and software development. Palladium XP provides Broadcom with a state-of-the-art platform to validate their next generation SOCs. Broadcom now has one of the largest Palladium installations. So, do check out the video recording and see why Broadcom thinks transaction-based acceleration is an essential strength of their verification arsenal.

Raj Mathur

Accelerating Metric-Driven Verification With “Hotswap” on Verification Computing Platform

rmathur — Wed, 09 Jun 2010 16:30:00 GMT

For a while now, Cadence has been providing leading verification solutions and methodologies such as metric driven verification (MDV). MDV guides verification projects from initial planning to verification closure. Engineers need automated verification management solutions that utilize metrics. Cadence metric-driven technologies automate time-consuming manual verification tasks at the block, chip, system, and project levels. Using a metric-driven approach, system designers and verification teams can streamline the verification process and better analyze failures and coverage to debug their designs.

This year, to meet the system level requirements of the System Realization component of the EDA360 industry vision, Cadence has augmented its metric-driven verification methodology to collect metrics from accelerated hardware and to analyze design failures more quickly. But this capability works with no ordinary hardware platform.

You see, in order to efficiently collect metrics and analyze failures from a hybrid verification environment consisting of both software simulation and hardware acceleration, the use model must allow a seamless transition from software to hardware - and back. The engineer should be able to easily choose whether to run simulation on a workstation motherboard or in an accelerated hardware - and maintain control while reaping the benefits of a familiar software debug environment. In Cadence's verification computing platform, called Palladium XP, we refer to this capability as "hotswap."

If you're planning on attending Design Automation Conference (DAC) 2010 in Anaheim next week, be sure to stop by the Cadence booth to learn more about MDV for acceleration and hotswap. Cadence will be demonstrating "Metric Driven Verification for acceleration with Palladium XP." You'll see how metrics can be collected from hardware and how users can easily "hotswap" back and forth between software simulation and hardware acceleration. You'll see how this capability can help you reach design closure more quickly.

Other System Realization demos at DAC 2010

Live: HW/SW co-debug with ARM based design demo

ARM VSTREAM demo

Wind River Simics demo

Look for these at the System Realization pod at the Cadence booth, Hall B #1334.

DVCON 2010 tutorial: OVM Advanced Application tutorial with OVM Acceleration

Palladium XP video demo - Preview

Raj Mathur

Raj Mathur Blog

Broadcom Presentation Shows Value of Transaction-Based Acceleration

Accelerating Metric-Driven Verification With “Hotswap” on Verification Computing Platform