Raj Mathur Bloghttps://community.cadence.com/searchSearch resultsen-USTelligent Community 10RE: PCB 17.2 Step Mapping troubleshttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/HYOgAYUdSeo/1353775Mon, 19 Feb 2018 15:27:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353775steve/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troubles/1353775#1353775Can you attach the filename.dra you are trying to map the model tohttps://community.cadence.com/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troubles/1353775#1353775RE: PCB 17.2 Step Mapping troubleshttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/D4wKBm6iszc/1353774Mon, 19 Feb 2018 15:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353774PIPE/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troubles/1353774#1353774Hi Steve, than ks i follow your Information regarding the Support!. I can not map the Capacitor within the Step Maping Dialog. We have already try to reduce the step with a external tool "Freecad" but in General i can not map this capacitor. i send you a Screen shoot from a solidworks easm. thats explain the Situation. Thanks Peterhttps://community.cadence.com/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troubles/1353774#1353774RE: PCB 17.2 Step Mapping troubleshttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/SLCqHzEFtfM/1353773Mon, 19 Feb 2018 15:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353773steve/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troubles/1353773#1353773So what's the problem here? The capacitor looks like it's lying down on the board with the holes off to the side. Mount the legs inside the holes with the body touching the surface of the PCB - or do you need a vertical version of the step model.https://community.cadence.com/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troubles/1353773#1353773RE: Feature Request: New 3D Engine PCB 17.2http://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/6lz96_ZZLi0/1353772Mon, 19 Feb 2018 15:08:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353772steve/cadence_technology_forums/f/pcb-design/38327/feature-request-new-3d-engine-pcb-17-2/1353772#1353772This isn't the place for enhancement requests, you need to either file a case with cadence online support or with the channel partner you bought the software from.https://community.cadence.com/cadence_technology_forums/f/pcb-design/38327/feature-request-new-3d-engine-pcb-17-2/1353772#1353772RE: Feature Request: New 3D Engine PCB 17.2http://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/p-yZtzQGEkg/1353771Mon, 19 Feb 2018 13:36:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353771PIPE/cadence_technology_forums/f/pcb-design/38327/feature-request-new-3d-engine-pcb-17-2/1353771#1353771Hi All. I am a liitle confused now. I have assumed that i receive some feedback after a i write to this Forum. Is this the wrong Methode ? I pay a lot off Money for the subscription and i allready a member within the Altium Beta Forum. This Forum typical answer my question. thanks. Peterhttps://community.cadence.com/cadence_technology_forums/f/pcb-design/38327/feature-request-new-3d-engine-pcb-17-2/1353771#1353771PCB 17.2 Step Mapping troubleshttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/FMFfwk8eTHY/pcb-17-2-step-mapping-troublesMon, 19 Feb 2018 13:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:38337PIPE/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troubles3Hi i have some Troubles to map some 3D Step files. Here a view Samples. community.cadence.com/.../Step.zip Regards Peterhttps://community.cadence.com/cadence_technology_forums/f/pcb-design/38337/pcb-17-2-step-mapping-troublesRE: Change Pins from VSS to DVDD and vice versa in the Schematichttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/8Or_nlLDffI/1353770Mon, 19 Feb 2018 08:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353770Andrew Beckett/cadence_technology_forums/f/custom-ic-skill/38332/change-pins-from-vss-to-dvdd-and-vice-versa-in-the-schematic/1353770#1353770Hi Utkarsh, rexReplace is a general pattern matching/replacement function - it takes a string as input and returns the updated string. It does not update any variable or expression. schReplaceProperty is explicitly for updating a named property on an object - it's not a matter of updating a variable, but it's designed specifically to modify a parameter on an object. So they do completely different things... Anyway, glad the updated code is working. Regards, Andrew.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/38332/change-pins-from-vss-to-dvdd-and-vice-versa-in-the-schematic/1353770#1353770RE: customizing ViVA result browser traces default settingshttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/hQip0eArlRc/1353769Mon, 19 Feb 2018 08:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353769HoWei/cadence_technology_forums/f/custom-ic-design/38328/customizing-viva-result-browser-traces-default-settings/1353769#1353769Update: Itwas working with the ".cdsenv" entry as well, but the testing I performed was misleading. When I start a new virtuoso session and the result browser opens automatically it opens with the Settings of the last sessions. I expected the result browser to open with the Settings given by .cdsenv. When the result browser is closed and openend again, then the Settings of the .cdsenv are applied. Problem solved, entries in ".cdsenv" are correct, testing was wrong !https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38328/customizing-viva-result-browser-traces-default-settings/1353769#1353769same value for a RANDC variable of base class in extended class objectshttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/Kw2kyeMzwhk/same-value-for-a-randc-variable-of-base-class-in-extended-class-objectsMon, 19 Feb 2018 07:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:38336santhog/cadence_technology_forums/f/functional-verification/38336/same-value-for-a-randc-variable-of-base-class-in-extended-class-objects0i have a randc variable "index" in c_base . i've two new classes ( class_1 & class_2 ) extended from base_class. when randomizing the extended class objects, i observed the variable "index" is having same values in C1 & C2 objects. Below is the simplified copy of my code: class c_base extends uvm_sequence_item; rand bit [9:0] index; `uvm_object_utils_begin(c_base) `uvm_field_int(index,UVM_ALL_ON) `uvm_object_utils_end function new(string name="c_base"); super.new(name); endfunction endclass class class_1 extends c_base; rand bit [3:0] var1; rand bit [7:0] var2; rand bit [3:0] var3; `uvm_object_utils_begin(class_1) `uvm_field_int(var1,UVM_ALL_ON) `uvm_field_int(var2,UVM_ALL_ON) `uvm_field_int(var3,UVM_ALL_ON) `uvm_object_utils_end function new(string name="class_1"); super.new(name); endfunction endclass class class_2 extends c_base; rand bit [4:0] var4; rand bit [10:0] var5; `uvm_object_utils_begin(class_2) `uvm_field_int(var4,UVM_ALL_ON) `uvm_field_int(var5,UVM_ALL_ON) `uvm_object_utils_end function new(string name="class_2"); super.new(name); endfunction endclass module tst; class_1 c1[]; class_2 c2[]; c_base q[$]; initial begin c1=new[20]; c2=new[20]; foreach(c1[i]) begin c1[i]=class_1::type_id::create($sformatf("c1_%0d",i)); assert( c1[i].randomize() ); q.push_back(c1[i]); end foreach(c2[i]) begin c2[i]=class_2::type_id::create($sformatf("c2_%0d",i)); assert( c2[i].randomize() ); q.push_back(c2[i]); end q.sort with(item.index); $display("---------------"); $display(" Index Name "); $display("---------------"); for(int i=0; i<q.size();i++) begin $display(" x%h %s",q[i].index,q[i].get_name()); end end endmodule EdaPlayground link: https://www.edaplayground.com/x/3pk2 For the above code in EdaPlayground, I'm creating 20 objects for both classes and got same index value ( x398, x2d7) for a class_1 & class_2 objects. What I expected was, the index value of all objects will be unique until all combinations are exercised. My intention is to use "index" as the location of SRAM address to store the packed data of each extended class object. Is this the expected behavior in SimVision15.20?? Can't i get unique values for variable index ?https://community.cadence.com/cadence_technology_forums/f/functional-verification/38336/same-value-for-a-randc-variable-of-base-class-in-extended-class-objectsRE: customizing ViVA result browser traces default settingshttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/Ss8v72IauyM/1353768Mon, 19 Feb 2018 06:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353768HoWei/cadence_technology_forums/f/custom-ic-design/38328/customizing-viva-result-browser-traces-default-settings/1353768#1353768I added the following line to the .cdsenv: viva.rectGraph stripChartOn string "true" The .cdsenv is not located in my ~ Folder because I redefined the searchpath in "setup.loc" to my workarea via $CDS_WORKAREA. In the workarea there is the "csfLookupConfig", that defines to search for .cdsinit, .cdsenv and display.drf in the $CDS_WORKAREA folder. This mechanism works fine.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38328/customizing-viva-result-browser-traces-default-settings/1353768#1353768RE: Change Pins from VSS to DVDD and vice versa in the Schematichttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/y8aKc4eBAn8/1353767Mon, 19 Feb 2018 05:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353767Utkarsh Arora/cadence_technology_forums/f/custom-ic-skill/38332/change-pins-from-vss-to-dvdd-and-vice-versa-in-the-schematic/1353767#1353767Hi Andrew The code is working fine. Thanks. Utkarshhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/38332/change-pins-from-vss-to-dvdd-and-vice-versa-in-the-schematic/1353767#1353767RE: resizing a schem symbolhttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/PQKULyLHej4/1353766Sun, 18 Feb 2018 21:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353766Jim Viau/cadence_technology_forums/f/pcb-design/26967/resizing-a-schem-symbol/1353766#1353766Had the exact same problem. After selecting All bits and pieces including the bounding box many square dots became pink, showing objects that did not appear when downsizing the bounding box. I managed to strictly select those invisible lines and deleted them. I was then able to downsize the bounding box as desired. What puzzle me is how can one manage to insert invisible objects in a part? Whatever, problem solved. Thanks oldmouldy !https://community.cadence.com/cadence_technology_forums/f/pcb-design/26967/resizing-a-schem-symbol/1353766#1353766Why 1 Is Not a Prime Numberhttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/qMdglrJccDY/fundamentalSun, 18 Feb 2018 21:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1340740Paul McLellan/cadence_blogs_8/b/breakfast-bytes/posts/fundamental0It's Presidents' Day and Cadence is on holiday. So time for me to write about something that is interesting (well, it's interesting to me, anyway) but not directly anything to do with semiconductors or EDA. The Fundamental Theorem of Arithmetic Somebody asked me recently why 1 is not a prime number. After all, it is only divisible by itself and 1, which is the most concise definition. In fact, a prime number is any number greater than 1 that is only divisible by itself and 1, and so the definition explicitly excludes 1. We (by which I mean mathematicians through the years) defined what a prime number is, and we could have made 1 a prime number without it being a silly definition (which it would be if we defined a prime number to be any number containing a 7, for instance—there wouldn't be much you could use that concept for). If 1 was a prime number, then some things in math wouldn't require an exception. For example, Goldbach's conjecture states that any even number greater than 2 is the sum of two primes. The reason for the "greater than 2" wrinkle is because 2 is 1+1 and we have defined 1 not to be prime. If 1 was prime, then Goldbach's conjecture would simply be that any even number is the sum of two primes. However, if we let 1 be a prime, then it would mean that the prime factorization theorem would not be true without adding a lot more wrinkles of its own. The prime factorization theorem says that any number can be uniquely factored into a product of prime numbers. So 6 = 2 x 3, and 20 = 2 x 2 x 5. We are so used to this that it doesn't seem amazing that it is true, but there is a sense in which it is surprising that, say, 51 = 3 x 17 and it can't also be 7 x something or 13 x something. The prime factorization theorem is so important that it has a second name, The Fundamental Theorem of Arithmetic. Here is a more rigorous definition: The fundamental theorem of arithmetic states that every positive integer (except the number 1) can be represented in exactly one way apart from rearrangement as a product of one or more primes If 1 was prime, we wouldn't need the little exception in parentheses. But then we wouldn't need the theorem at all, since it wouldn't be true. 6 would still be 2 x 3 but also 2 x 3 x 1 and 2 x 3 x 1 x 1 and 2 x 3 x 1 x 1 x 1 and so on. So going back all the way to Euclid, and probably before, 1 has been explicitly excluded from being a prime number. What Euclid proved was that if p is prime, and p divides A x B without a remainder, then either p divides A without a remainder, or p divides B without a remainder. The Fundamental Theorem of Arithmetic is a corollary of this, since it wouldn't be true if there was a number with two different factorizations. Fundamental Theorem of Algebra There is also a Fundamental Theorem of Algebra. However, it is not exactly the "Algebra I" you learned in middle school: The fundamental theorem of algebra states that every non-constant single-variable polynomial with complex coefficients has at least one complex root This is more important than it sounds. When you were in primary school, you learned about positive numbers: 1, 2, 3... Then you discovered that you can't solve 3 - 5 with only positive numbers, so you learned about negative numbers: -1, -354... Then you discovered that you can't solve 3 / 7 and so you learned about fractions, what mathematicians call rational numbers: 1/2, 3/4, 22/7... Then you discovered you can't solve x 2 = 2 with only rational numbers, so you learned about real numbers. 1.414... and 3.14159... Then you discovered, if you went far enough in math, that you can't solve x 2 = -1 so you learned about complex numbers: i , 1+2 i , and so on Then...nothing. The fundamental theorem of algebra tells you that you are done. You don't need to learn about some new type of number. Or, as mathematicians put it, the complex numbers are algebraically closed. I looked to see if there are any more interesting Fundamental Theorems I've never heard of, but Google only has these two. However, there is another really important fundamental concept... The Central Dogma of Biology As stated by Francis Crick back in 1958: The Central Dogma. This states that once 'information' has passed into protein it cannot get out again. In more detail, the transfer of information from nucleic acid to nucleic acid, or from nucleic acid to protein may be possible, but transfer from protein to protein, or from protein to nucleic acid is impossible. Information means here the precise determination of sequence, either of bases in the nucleic acid or of amino acid residues in the protein. This refutes Lamarckism, that an organism can pass on traits it learned to its offspring. It is more simply (but not 100% correctly) expressed as "DNA makes RNA, and RNA makes protein." Do You Know What Tau Is? I started this post saying that mathematicians had a choice as to whether they made 1 prime or not. Another place where mathematicians had a choice is the value of π (pi). It turns out that a lot of the time that π occurs in math, it shows up as 2π, starting with when you learned about the circumference of a circle as being 2πR. There is a whole subspecies of mathematicians who feel very strongly about this, and even have a letter τ (tau) for 2π. The math doesn't change just by renaming the concept, but a lot of math is simpler to express this way, from Fourier transforms, to the normal distribution (often called a bell-curve), and more. It even has a day, Tau Day, June 28th. If you want to go deep down the rathole, then read The Tau Manifesto , subtitle "No really, Pi is wrong.." Do You Know What Your Erdős Number Is? In my recent post on Zombies , I published an XKCD comic that doesn't make a lot of sense unless you know the story of Paul Erdős. He was the most prolific mathematician ever, publishing over 1,500 papers. He also had a notoriously weird lifestyle. He didn't live anywhere, he would stay at other mathematician's houses and say "my mind is open." Often, his host would explain some problem he'd been working on for a long time and Erdős would solve it almost instantly. They would then write a joint paper. The badge of honor for many mathematicians is to have a low Erdős number. Here's how it works. Paul Erdős has an Erdős number of zero. If you published a paper with him, you have an Erdős number of 1. If you published a paper with someone who has an Erdős number of 1 then your Erdős number is 2. And so on. So it's a sort of mathematical version of a Bacon number, as in the 6 degrees of Kevin Bacon game. There is even an Erdős-Bacon number, which is the sum of the two. One notable holder of a low Erdős-Bacon number is actress (and mathematician) Danica McKellar, who has an Erdős number of 4 and a Bacon number of 2, making a total of 6. President's Day Puzzle This isn't anything to do with Presidents, it's not one of those puzzles that looks like it's mathematical but is not: 16 20 25 35 ? (these are the numbers of the US Presidents who were assassinated—hopefully, the "?" never gets filled in). So here's your Presidents' Day puzzle. What comes next? 110 20 12 11 10 ? Sign up for Sunday Brunch, the weekly Breakfast Bytes email.https://community.cadence.com/cadence_blogs_8/b/breakfast-bytes/posts/fundamentalInnovus: Does not detect Inverters in libraryhttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/dmxlNHboIzM/innovus-does-not-detect-inverters-in-librarySun, 18 Feb 2018 15:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:38335Schriek/cadence_technology_forums/f/digital-implementation/38335/innovus-does-not-detect-inverters-in-library0Dear all, I'm using Innovus to P&R a design consisting of custom made cells. The cells have been characterized and compiled into a .lib file using Synopsys SiliconSmart. Everything works as expected, but I cannot do clock synthesis as Innovus does not detect my inverters as usable; Total number of combinational cells: 16 Total number of sequential cells: 2 Total number of tristate cells: 0 Total number of level shifter cells: 2 Total number of power gating cells: 0 Total number of isolation cells: 0 Total number of power switch cells: 0 Total number of pulse generator cells: 0 Total number of always on buffers: 0 Total number of retention cells: 0 List of usable buffers: Total number of usable buffers: 0 List of unusable buffers: Total number of unusable buffers: 0 List of usable inverters: Total number of usable inverters: 0 List of unusable inverters: Total number of unusable inverters: 0 List of identified usable delay cells: Total number of identified usable delay cells: 0 List of identified unusable delay cells: Total number of identified unusable delay cells: 0 My .lib file does not have cell footprints, according to the Innovus user guide this should be fine as it figures out the footprint automatically, depending on functionality. This is the output from 'reportFootPrint': # footPrint: INVX1 nrCell: 3 Library: Library: INVX1 INVX1 1 66.039 64.064 Y=(!X) INVX2 INVX1 2 32.803 32.654 Y=(!X) INVX4 INVX1 3 16.598 16.955 Y=(!X) # footPrint: INVX1 nrCell: 3 Library: Library: INVX1 INVX1 1 130.344 127.401 Y=(!X) INVX2 INVX1 2 64.316 65.580 Y=(!X) INVX4 INVX1 3 32.618 34.204 Y=(!X) Clearly, Innovus also sees that indeed it is an inverter and detects all inverters having the same footprint. Finally, I checked the 'dont_use' property, which is false. Hence the question, how can I further debug this, or even better, what would be the solution? (I am not allowed to upload the .lib files) Thanks.https://community.cadence.com/cadence_technology_forums/f/digital-implementation/38335/innovus-does-not-detect-inverters-in-libraryRE: How to properly handle wave family in custom calculator functionhttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/vXBLtMKa_RE/1353765Sun, 18 Feb 2018 09:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353765Andrew Beckett/cadence_technology_forums/f/custom-ic-skill/38325/how-to-properly-handle-wave-family-in-custom-calculator-function/1353765#1353765Alex, Yes, famMap will iterate over families in all the arguments together, so it will work pair-wise as you desire. The second question I can't really answer, as it almost certainly depends on what platform you're running your web browser on and which browser you're using. I use Mac and Safari (mostly) and Chrome (occasionally). I do from time to time have problems with preserving indentation - but I've not really done an exhaustive analysis of what works when (it has changed over time with different versions of the forum software too). Regards, Andrew.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/38325/how-to-properly-handle-wave-family-in-custom-calculator-function/1353765#1353765RE: How to find frequency for ring oscillator in Monte-Carlo analysis?http://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/eHAy1tV_uQo/1353764Sun, 18 Feb 2018 08:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353764Amin Zayed/cadence_technology_forums/f/custom-ic-design/38333/how-to-find-frequency-for-ring-oscillator-in-monte-carlo-analysis/1353764#1353764Hi Andrew first of all thank you for your replay. I use cadence 6.14 and calibre 2011, and tsmc 130nm technology. i need to how the process variation of nmos and pmos affect the frequency of the ring oscillator (5 inverters ), i will use this ring to make PUF for IOT applications. Regards, Aminhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38333/how-to-find-frequency-for-ring-oscillator-in-monte-carlo-analysis/1353764#1353764RE: How to properly handle wave family in custom calculator functionhttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/qVUaFM4vWUs/1353763Sun, 18 Feb 2018 08:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353763alexstepanov75/cadence_technology_forums/f/custom-ic-skill/38325/how-to-properly-handle-wave-family-in-custom-calculator-function/1353763#1353763Andrew, Thank you for replay. I have two additional questions: 1. I saw examples of famMap usage like you described. I checked manual for function famMap. It says "Applies a function with a set of arguments to each member of a family". It is not clear if an argument can be family too. In my case, pointsWave can be family of plots exactly like sourceWave, and resampleByWave should be applied to appropriate pairs. So will famMap work properly if used like you proposed? 2. How can I copy past code with indentation? I tried a couple of formattings but in each case spaces at the beginning of line removed. Alex.https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/38325/how-to-properly-handle-wave-family-in-custom-calculator-function/1353763#1353763RE: Assura LVS Parameter Mismatch Errorhttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/-Tbu3ORGCvQ/1353762Sun, 18 Feb 2018 08:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353762Andrew Beckett/cadence_technology_forums/f/custom-ic-design/38179/assura-lvs-parameter-mismatch-error/1353762#1353762Jim, auLvs and auCdl are two different netlisting approaches. auLvs was originally a netlister for Diva - for Assura it doesn't actually produce an "auLvs" netlist, but uses the same CDF information to control which parameters are read for LVS. auCdl produces a "CDL" (Component Description Language, a SPICE-like format which originated with Dracula and has been extended considerably by various LVS tools since). Both are means of providing the input to the schematic side of LVS. For the second part, this is controlled by the filterDevice and filterOptions functions in the rules. Look in the Assura Physical Verification Command Reference manual for more details. Regards, Andrew.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/38179/assura-lvs-parameter-mismatch-error/1353762#1353762RE: controlling mismatch & other related queries.http://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/l3VX0Mq8Fe0/1353761Sun, 18 Feb 2018 07:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353761Andrew Beckett/cadence_technology_forums/f/mixed-signal-design/38305/controlling-mismatch-other-related-queries/1353761#1353761Some attempts at answers: Yes, although the variation probably isn't "the same statistical variation". The standard deviation is likely to be different for mismatch and process variation. The approaches that you describe are not just for current mode circuits; it's any time you need the behaviour of the devices to be as consistent as possible. I'm not sure there are any different techniques that you'd apply just because the device is in a different region. Note, I should point out that mismatch analysis in Monte Carlo is really to analyse the remaining random variation and is not about the variation caused by poor layout matching practices. Of course, if you're looking at a circuit that is sensitive to mismatch of certain devices then the ones you need to focus on are likely to be the same as those which show up as significant contributors based on their random variation. Can't answer this, sorry. Regards, Andrew.https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/38305/controlling-mismatch-other-related-queries/1353761#1353761RE: PhysConfig: force to descendhttp://feedproxy.google.com/~r/cadence/community/blogs/63200/~3/FDTawSeYhNM/1353760Sun, 18 Feb 2018 07:47:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353760Andrew Beckett/cadence_technology_forums/f/custom-ic-skill/38326/physconfig-force-to-descend/1353760#1353760That would be cphSetInstForceDescend. You'd need to have an open physConfig (e.g. using cphFindOpenConfig or cphOpenConfig). There are also APIs to set force descend on cells and occurrences too. Search for any function that begins with "cph" in cdsFinder and then you can hit the "More Info" button (in IC617/ICADV122 onwards) to take you to the full documentation for the function. Regards, Andrewhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/38326/physconfig-force-to-descend/1353760#1353760