Steven Brown Blog

Virtual Flash Memory Gets Real

Steve Brown — Mon, 08 Aug 2011 23:00:00 GMT

This week's Flash Memory summit will not only highlight the IP Cadence delivers, but will touch on innovative application of virtual prototype technology for Flash Memory firmware and system development. Developing complex memory controllers is challenging, and an increasing portion of the capability is delivered as firmware. Virtual prototypes of hardware for memory controllers, and the systems within which they operate, enable software to be developed months ahead of the first RTL for simulation or FPGA prototyping. In a fast paced consumer marketplace where memory speed and capacity are central to delivering the value of the device, time to market is everything.

The Cadence Virtual System Platform offers the ability to model hardware at the TLM abstraction to provide speed needed for rapid software development. In addition, Incisive Software Extensions provides advanced verification of software and systems using the Universal Verification Methodology to automate use case generation and explore corner cases of the system. These technologies will be discussed on a panel Wednesday morning, as well as in the Cadence booth.

A virtual prototype enables early development of software, as well as coarse grained architectural assessment. Certain types of system timing, throughput, performance, and system capacity measurements can be estimated, enabling teams to adjust design decisions early in the project. Detailed, accurate architectural analysis isn't possible until RTL is available and the system is fully functioning. The transition to RTL from TLM can be more easily achieved with the Cadence System Development Suite, which combines virtual prototypes with simulation, emulation, and FPGA prototyping as an open, connected, and scalable solution.

Fig. 1 -- Virtual prototype for a memory controller

The panel is Thursday @ 8:30am, session #302: "Nonvolatile Design Challenges and Methodologies" and the participants are:

Steven Shrader, Cadence
Mike Strickland, Altera
Steven Brown, Cadence
Aaron Olbrich, Pliant Technology

Come visit the Cadence booth to learn more!

Steve Brown

Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!

Steve Brown — Mon, 23 May 2011 16:00:00 GMT

It's been an exciting month for the System Realization team with the announcement of our System Development Suite. One of the new products, the Cadence Virtual System Platform, made its debut at the Embedded Systems Conference and has generated a lot of interest from our customers. DAC is right around the corner, and we'll be there with the latest demos of the System Development Suite, and a suite demo focusing on the VIrtual System Platform on Monday at 3pm, Tuesday at 9am, and Wednesday at 4pm. Register online now to reserve a seat for a suite demo.

In parallel to the the Embedded Systems Conference was the CDNLive EMEA user conference in Munich. Cadence offered a tutorial on the System Development Suite that was very well attended. In addition to the demos and roadmap, there was a customer presentation by Ericsson describing their transition to TLM. ARM's Rob Kaye presented about architectural exploration with ARM Fast Models and the Virtual System Platform. Watch for repeats of this presentation at other venues.

Cadence's IP efforts in the SoC Realization organization are also taking advantage of the Virtual System Platform. In this video Sanjay Srivastava, Senior Vice President SoC Realization, discusses the benefits his team derives from using a virtual prototype instead of waiting for FPGA prototypes.

Below is a video demo of the Android SDK running on an ARM-based virtual prototype in the Virtual System Platform. The virtual prototype is connected to the internet through a virtualized Ethernet model, and is accessing actual Internet webpages. It also shows some of the hardware/software debugging capabilities that are needed for hardware-dependent software development.

Part of the Cadence System Development Suite, the Virtual System Platform enables pre-RTL software design, verification, and system analysis before committing to hardware design. It automates the process of creating a virtual prototype, debugging software, and deploying the virtual prototype to the software team—allowing software development to begin months earlier and preventing schedule slips in prototype delivery. The Virtual System Platform also enables transaction-level model (TLM)-aware hardware/software debugging with complete visibility and controllability, and supports mixed TLM/RTL simulation with the Incisive Verification Platform, as well as co-simulation with the Cadence Verification Computing Platform (Palladium XP).

Features/Benefits

Begin software development months before RTL and FPGA prototypes are available
Create a first working virtual prototype in days versus weeks
Improve collaboration between hardware and software development teams
Rapidly debug complex hardware and software issues
Easily connect to the implementation flow

Steve Brown

Building Open Virtual Platforms - Bridging the Gap of Model Availability

Steve Brown — Wed, 04 May 2011 13:00:00 GMT

Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing model syndrome" -- essentially the lack of adequate pre-built IP to assemble into the prototype, and the challenges of creating those models themselves. Some providers have created libraries of models, but without a standard language the models are proprietary and cannot be used in any other environment. The SystemC language (IEEE 1666) has added the important TLM 2.0 extensions, but writing models with TLM 2.0 requires practice and a methodology for reusability.

Cadence announced its new Virtual System Platform as part of the System Development Suite May 3. The Virtual System Platform enables pre-RTL software development, system functional verification, and system analysis and optimization before committing to a hardware micro-architecture. One of its key capabilities is its open modeling approach supporting processor models, and automating the creation of TLM 2.0 for interconnect and IP blocks. It incorporates high performance processor models from ARM, Imperas, and others that utilize SystemC TLM 2.0. What is new and valuable is the generation of TLM 2.0 code to speed the process of creating new virtual prototype models.

In order for models to be truly open and reusable, they must be written using SystemC TLM 2.0. The Virtual System Platform has TLM-aware capabilities that provides non-intrusive debugging and observability of the system behavior. Any TLM 1.0 or TLM 2.0 models will execute in the Virtual System Platform. It also comes with a TLM generation capability that uses a description of the pins and registers to generate all the TLM 2.0 interface code. As you can see from the process flow below, this code can be compiled and linked into a virtual prototype that can be used for early software compilation and simple register activity testing. Subsequently the function of each virtual prototype IP block can be added, in order to bring-up the operating system, such as Linux.

The TLM generation uses a textual or IP-XACT description of the interface pins and registers, and produces all the TLM 2.0 for the IP. This includes all the pin and register declarations, access functions, and C++ templates for implementing the functionality of the IP. Not only is this an open, standards based approach, but it provides an easy way to maintain the code as registers or pins are added, changed, or deleted. It also produces the header files needed for embedded software compilation, program files that test all the register read/write behavior, and the header files for integration with the rest of the virtual prototype.

There are other capabilities and benefits of the Virtual System Platform related to its connection to the rest of the System Development Suite, and its scalability for today's multi-core systems. Watch this space!

Steve Brown

DATE Spotlights System Development University Investment in Europe

Steve Brown — Thu, 10 Mar 2011 21:00:00 GMT

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's attending the University Booth at the DATE Conference in Grenoble, France March 14-18.

I’m getting ready for a busy upcoming week with DATE conference in Grenoble, France. Besides organizing a workshop and a panel about embedded system debug and test, presenting Cadence ESL tools at the Europractice event and helping representing Cadence at GlobalFoundries (booth 1& 2), I’m squeezing customer visits into my tight schedule. I’m already created a short list of presentations I will attend at this always worth visiting conference.

Despite a busy day, however, I’m already planning ahead to spend enough time at the University Booth on the exhibition floor. This is not only because Cadence is a co-sponsor of this event, which I found out lately, but because it is a great opportunity to discuss upcoming solutions and to get in contact with the people behind these research projects.

Since a visit at DATE has to be planned ahead, I already know when I will stop by at the University Booth. This year I picked three topics. First, power estimations and optimizations; second, methods to shorten time to market for multi-threaded and multi-core applications; and last but not least, a very interesting high level approach to combine simulation and formal verification. Starting with the later presentation titled “Demonstration of a Coverage Driven Verification Environment for UML Models of Systems-on-Chip” I’m interested in learning how the authors enhanced simulation with static analysis of UML models and model checking techniques.

Two presentations are promising solutions if your design complexity increased lately due to the usage of hundreds of processors, instead of just one as in the good old single core SoC days. The first one presents “Daedalus” – a system-level flow that does auto-parallelization of sequential programs as well as system-level simulation and high level synthesis. The second presentation is from TIMA, in Grenoble, about their solution “VOCIS” -- a simulation model that enables quantitative comparison of interconnect architectures regarding power, performance and reliability.

Power and energy optimization is an important topic for Cadence R&D, so hopefully will have time to chat with Kyushu University to learn how memory access optimizations in embedded systems can improve power consumption. If I miss the booth of Open-PEOPLE to learn how their power and energy optimization platform and estimator is working I can check that later on their home page.

So take the chance to say hello next week in Grenoble, France and leave a comment if you visited University Booth at DATE.

Markus Winterholer

Do You Have a DATE with Software? Cadence Does!

Steve Brown — Mon, 28 Feb 2011 14:00:00 GMT

How important is the software market to Cadence and as an element of the EDA360 vision? Important enough that Cadence is sponsoring several relevant sessions at the upcoming Design, Automation, and Test in Europe (DATE) conference in Grenoble, March 14-18, 2011. If you're anywhere near Grenoble in March, these are must-see events!

First there is a panel on the confluence of virtual platforms, the use of IP-XACT for assembly, and their potential for changing the RTL-based SoC design flow, on Tuesday, March 15, from 16:15-17:15.

ET02: "What is missing to enable global IP collection, assembly, and virtual platform distribution?"

Abstract:

The domains of RTL design, virtual platforms, high level synthesis, and IP assembly automation are converging to enhance the productivity and reliability of system level design methodology. A significant number of companies are creating RTL IP catalogs and leveraging assembly automation to rapidly produce incrementally innovative SoCs. Virtual platforms are enabling a growing practice pre-RTL software development. High level synthesis is increasing the productivity to create new RTL IP. The confluence of these forces is creating a plethora of opportunities, and presenting several challenges. This panel will explore and debate the priorities and benefits of these emerging trends and discuss the following questions:

How far along are customers in creating internal virtual platform IP catalogs?
What are the challenges of organizing virtual platform and RTL IP catalogs?
How do IP-XACT and assembly tools help with this internal management problem?
Are companies starting to use 3rd party IP suppliers to provide virtual platform and RTL IP, as well as IP-XACT?
What are the challenges in defining IP catalog requirements to 3rd parties?
Are standards needed in addition to IP-XACT to enable freer IP creation and exchange?

Second, there will be a joint tutorial on a methodology for leveraging IP-XACT for virtual prototype IP creation and assembly, on Wednesday, March 16, from 13:30-16:30.

TS-1: Tool Seminar: "Unifying IP-XACT platform assembly with virtual platform modeling"

Description:

The goals for IP-XACT have expanded from RTL IP warehousing and easier SoC assembly. As virtual platform adoption has grown, the natural need arises to assemble TLM IP into a virtual platform, and refine it into the resulting RTL SoC. This tutorial will highlight the creation and assembly of SoCs starting from virtual platforms, key decisions to be taken, and potential issues to avoid.

And finally, there will be a panel discussion on trends in software verifcation and organizations, on Wednesday, March 16, from 1100-1230.

6.8 PANEL SESSION – Embedded Software Debug and Test

Today’s complexity of embedded software is steadily increasing. The growing number of processors in a system and the increased communication and synchronization of all components requires scalable debug and test methods for each component as well as the system as a whole. Considering today’s cost and time to market sensitivity, it is important to find and debug errors as early as possible and to increase the degree of test and debug automation to avoid quality losses. These challenges are not only requiring new tools and methodologies but also organizational changes, since the hardware and software developer have to work closer together to achieve the necessary productivity and quality gain. The panel will discuss new strategies in hardware and software development to make embedded software more reliable and easy to debug.

It should be a very interesting conference. Don't miss your DATE with Cadence!

Steve Brown

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Steve Brown — Thu, 24 Feb 2011 17:00:00 GMT

Don't lose touch with what's new in the world of SystemC! Cadence is a long time contributor and sponsor of SystemC initiatives, and that commitment continues to show during next week's SystemC Day and North American SystemC User Group (NASCUG) at DVCon. The conference is being held at the DoubleTree hotel in San Jose, California, February 28th-March 3rd. Cadence has been involved in SystemC initiatives for so long I sometimes forget that not everyone knows the extent of our involvement. You can see the evidence in next week's activities!

As a Corporate Member of the Open SystemC Initiative (OSCI), Cadence is active in leadership of the organization and funding activities. Stan Krolikoski is on the board of directors directing investment in OSCI to continue funding the standards development activities. We participate in working groups, and most recently contributed to the IEEE P1666 2011 efforts.

Cadence is a sponsor of the upcoming SystemC Day on Monday, Feb 28th, an important part of this years NASCUG 15:

Agenda

8:30 am - 12:00 pm		NASCUG 15 Meeting View agenda
10:00 am - 2:00 pm		Sponsor Tabletop Exhibits
12:00 pm - 1:00 pm		Town Hall Lunch with OSCI and Accellera Details
1:30 pm - 5:00 pm		DVCon Tutorial: "Software-Driven Verification Using TLM-2.0 Virtual Platforms" Tutorial information

NASCUG 15 with Jim Hogan Keynote

The day starts off with the NASCUG 15 (North American SystemC Users Group) meeting featuring a keynote speech by Industry expert and private investor Jim Hogan. Jim will discuss the semiconductor industry’s growing adoption of SoC design and its reliance on diverse sources of hardware and software IP, developed both internally and externally.

NASCUG also includes technical presentations on architectural modeling, verification, and analog/mixed-signal design using SystemC. An update of technical working group activities will be presented.

Agenda is now available at www.nascug.org.

DVCon Tutorial: "Software-driven Verification using TLM-2.0 Virtual Platforms”

Presenters:

John Aynsley - Doulos
David Black - XtremeEDA Corp.
Bill Bunton - LSI Corp.
Volkan Esen - Infineon Technologies
Trevor Wieman - Intel Corp.

In addition to embedded software development, virtual platforms can effectively be deployed for software-driven verification, in which SystemC TLM-2.0 loosely-timed transaction-level platforms are connected by using transactors to signal-level representations of new subsystem hardware at the RT-level.

This tutorial will provide both a detailed technology overview of software-driven verification techniques using loosely-timed SystemC TLM-2.0 based virtual platforms, and real-world case studies describing how these techniques benefit design teams.

Find out more and register: http://dvcon.org/events/eventdetails.aspx?id=121-2-T

Steve Brown

Open Mobile Summit -- What‘s Happening in the World of Applications

Steve Brown — Mon, 15 Nov 2010 23:00:00 GMT

I attended last week's Open Mobile Summit in San Francisco last week. This is a twice-a-year event, once here and once in London. The conference attracted over 600 attendees to discuss the world of mobile applications -- open mobile, to be precise. There were chip suppliers (TI, Qualcomm, Intel, etc), device suppliers (HTC, Motorola, RIM, Samsung, etc), applications developers (Zynga, LinkedIn, Foursquare, etc), carriers (AT&T, Orange, Verizon, Sprint, Rogers, etc), advertising agencies, content providers (Disney, NPR, BET, NBA, MLB, etc), and more. The main topic discussed was monitization trends. No surprise, we were all there to figure out how to make money.

Several interesting comments and questions arose during the panels:

- Application development for mobile devices is targeted at 6 weeks

- Porting applications between devices/OS is non-value add; they want a "build once, sell everywhere" model

- How will the industry ease application development, porting, and testing for new devices, while simultaneously enabling chip differentiation (innovations/features) to be leveraged by applications?

- The dominant device (billions of users) for the next several years will be feature phones (camera, music, text, etc)

- The future important wireless device categories are smart phones, tablets, and machine2machine (M2M). M2M is seen as a 2 order-of-magnitude larger volume over phones. Coming smart phone innovations will be in the area of display (projection) and control (virtual keypads, kinetic input).

- Google is claiming there are 300,000 software developers writing for Android

- Will applications be packaged with bandwidth, or will the business models of carrier/bandwidth, device, and applications remain separate?

- The advertising world is finding great value in the targetability of mobile-enabled advertising and branding, though it is not yet possible to launch an ubiquitous campaign

-The speed of Android code revisions is causing serious headaches for both device and application developers

One of the panel discussions in particular discussed the device and chip market place. It was titled: Mobile Platform Wars and the Device Future

On the panel were:

Alain Mutricy, SVP, Motorola
Jason Mackenzie, President Americas, HTC
Mike Bell, Vice President Ultra Mobility Group, Intel
Omar Khan, Chief Strategy Office, Samsung

Each made some very provocative statements about their businesses and prospects:

Alain/Motorola

"In 3 years there will be no difference between PC and mobile devices." Android will displace Windows, or is it the other way around?

Jason/HTC

"I've forced myself to use the Microsoft phone OS for two months. Don't count them out!" Does he personally prefer Android?

"We have accelerated our transition from traditional hardware manufacturer to differentiate on software/user experience, designing the hardware to enable that." Is HTC getting into applications?

Mike/Intel

"Those that invest in Android will benefit in the long run. There will be consolidation in the device area, and they will be differentiated by applications."

Omar/Samsung

"We have 100,000 applications, and are developing a signature user experience on top of that. We invested in a few services (aka Apps) to standardize across mulitple platforms for a common user experience."

"We want to deliver specific promise around innovation in each device, in services (eg Apps) and hardware enabled experiences. Supply chain planning must now consider software lifecycles as well as hardware availability."

Another fantastic panel delved into super smart phones: What Makes a Superphone Super?

On the panel were:

Jerome Nadel, EVP, Sagem Wireless
Mike Bell, Vice President Ultra Mobility Group, Intel
Sayeed Choudhury, Director of Product Management, Qualcomm
Seshu Madhavapeddy, SGM Smartphones Business Line, TI

They started by distinguishing the Superphone in the spectrum: Fossil phones, Feature phones, Smart phones, and Super phones

Seshu/TI

"More performance for same power. Human/machine interface innovation is in the future...smell, touch, gesturing, projection, etc"

"All phones will be smart phones in 4 years time."

"All chipset vendors are software guys. We offer software with hardware, but it is enabling technology."

Sayeed/Qualcomm

"Joules law - the battery is more limiting than Moore's law is giving."

"Android isn't a performance core base, and must be tuned accordingly. Enabling Android well is what is so expensive."

"Google will be foolish to stiffle innovation and require Android compliance."

"We have more software people than hardware. We develop software and throw in the chips for free."

"Apple monetizes through devices, iTunes is the razor. Google is making ad sales revenue, and zero on devices. RIM Blackberry enterprise server is how they make their money. Nokia is using OVI. All these plays have a strong services (eg Apps) revenue stream, or an agenda around that play."

Jerome/Sagem

"Aggregation of software, brought together in a meaningful way, is what will be enabled and will distringuish the Super phone."

Mike/Intel

"Apps have to be hand tuned/compiled to take advantage of the multi-core devices, and we don't have those tools yet. Using multi-core is rocket science."

"Intel has more people working on Android than Google does."

In summary, this was an excellent conference with very dynamic discussions around chip, board/device, OS, and application trends. Much was debated, but not a lot was decided. One thing is clear -- this group firmly believes that the explosion in applications (290 applications are downloaded to smart phone/iPad every second) is the driving factor around which we must organize our business strategies.

Steve Brown

Will Your Next System Project Succeed?

Steve Brown — Wed, 29 Sep 2010 18:30:00 GMT

Will you have the System Realization tools you need? Will you know how to apply them and not waste 6 months of your schedule? The Cadence System Realization webinars are here to help you succeed! They provide a unique view into the rapidly expanding System Realization domain, and detailed technical insight into adopting ESL methodology, modeling virtual prototypes, debugging multi-core software, and high level sequential logical equivalence checking (whew!). The September webinars were impressive in their scope from virtual prototyping, multi-core debugging, and equivalence checking.

Continuing in October the webinars begin with TSMC detailing TLM design and verification, then continue with ARM describing embedded software development and optimization, Cadence illuminating our ESL services offerings, and after Thanksgiving, TSMC focusing on high level synthesis.

These technical webinars are ideal for engineers and managers who have to deliver not only silicon but embedded software, and who want to learn about new areas of system and software design and verification, strategies for adoption, and the benefits of these solutions.

Participants can register here.

TSMC Reference Flow 11 – ESL focus on TLM design and verification methodology – Oct 6, 10am PST

The growing complexity of systems is impacting the ability to produce and verify new IP to meet functional specifications as well as performance, power, and area constraints. TSMC established a new ESL scope for their reference flow to help customers more easily adopt methodology to increase productivity. Cadence contributed to the ESL reference flow, a part of which was the TLM design and verification methodology.

The methodology focused on IP blocks and describes the creation and refinement of high level models through to RTL (reusing high level models at the next subsequent level of abstraction), and the verification methodology to apply functional verification through those stages of refinement (reusing the test bench applied to higher levels of abstraction at the next subsequent level of abstraction) .

This webinar will introduce the various levels of abstraction in the stages of refinement, and the approach to architect an advanced UVM verification environment to reuse through the entire flow. A key design concept consideration addressed in the methodology is creating models that can be used for virtual prototypes, high level synthesis, and functional verification. A key verification concept in the methodology is the use of verification planning and management to document and measure the function verified at each stage of the design refinement, including RTL. Ashok Mehta, Sr. Engineering Manager, TSMC, will open the webinar with an overview of TSMC RF11. Leonard Drucker, Solution Deployment Director, Cadence, will then overview technical details of the methodology.

Developing software for ARM-based devices– Oct 13, 10am PST

Software content in embedded designs is growing fast to meet consumer demand for capability, integration, and mobility. Embedded devices are being released to consumers at a faster rate and semiconductor design times are shrinking, so software is becoming a significant aspect for system design and verification. Creating application software rapidly, debugging efficiently, optimizing performance and power, and completing hardware/software co-verification is more complex than ever. In this presentation you will learn about the latest solutions from ARM and Cadence for ARM-based embedded and application software creation, debug, and functional co-verification. Solutions include ARM Fast Models that enable early software development and co-verification with Cadence Incisive SystemC simulation; the ARM VSTREAM running with the Palladium XP Verification Computing Environment, enabling accurate co-verification with ARM cores and RTL SoCs; and both solutions sharing the widely used RealView Development Suite (RVDS) for software development.

System Realization Services from Cadence – Oct 20, 10am PST

The need for shorter time to market and optimized system design is driving adoption of new system design methodologies using higher abstraction. SystemC modeling for system analysis, high level synthesis, and virtual platforms for early software development are the most common areas customers are requesting help. This webinar will highlight project examples that illustrate how customers are employing new methodology and technology for system design and verification, and the benefits of using Cadence products. It will also describe various ways that Cadence services uniquely enable customer success and adoption of these new solutions.

TSMC Reference Flow 11 – ESL focus on High Level Synthesis – Nov 3, 10am PST

High level synthesis is one of the key motivators for higher productivity IP design and verification. TSMC established a new ESL scope for their reference flow to help customers more easily adopt methodology to increase productivity. Cadence contributed to the ESL reference flow, a part of which is enabling adoption of high level synthesis. The methodology focuses on creating high level models in C, C++, or SystemC and using an interactive approach to understand the resources and timing of the design.

This webinar will introduce the concepts of modeling for high level synthesis, and a repeatable approach to creating high quality of results (QoR) RTL designs that meet area, timing, and power constraints. Ashok Mehta, Sr. Engineering Manager, TSMC will open the webinar with an overview of TSMC RF11. Mark Warren, AE Director, Cadence, will then overview the technical details of the methodology.

Steve Brown

System Realization Webinars Start Sept 8th

Steve Brown — Tue, 24 Aug 2010 20:00:00 GMT

Starting September 8th Cadence will be hosting a series of webinars about various topics in the area of System Realization. Several of these webinars will be led by members of the System Realization Alliance, sharing their particular views and contributions of the industry, and their connection and interoperability with Cadence methodology and tools.

Readers who want to learn about adoption strategies and benefits of leading edge ESL methodology, modeling, synthesis and verification can do so efficiently in these technically-based webinars.

The webinars all run Wednesday at 10am Pacific time, starting Sept 8th.The first webinar will be led by XtremeEDA, followed by CircuitSutra, Imperas, and Calypto Design Systems, Inc.

Participants can register here. Recordings will be available afterwards if you can't make that particular time.

XtremeEDA - Sept 8th, 10am

ESL has come a long way since its formal identification several years ago; however, it has not made the sweeping changes that early promoters expected. This talk will look at a few of the reasons why ESL adoption has been slow, and show why a new approach using a holistic methodology is changing the rate of adoption. This includes a look at what drives real design, the fundamentals of change, and some of the missing elements for a realistic approach to ESL. In particular, this new methodology embraces System Realization holistically—from architectural investigation to gates, embracing design, verification, and validation with an emphasis on reuse of all components.

CircuitSutra - Sept 15th, 10am

In this presentation, we will talk about various SoC modeling standards and how they work with Cadence tools to enable the TLM-driven design and verification methodology. The SoC modeling standards include: OSCI SystemC IEEE 1666, OSCI TLM 1.0, OSCI TLM 2.0, OSCI SystemC synthesizable subset draft, STARC TL guidelines, and the OCP-IP modeling kit.

Imperas - Sept 22nd, 10am

This presentation will show how the integration of Incisive SystemC simulation, Incisive Software Extensions, processor models from OVP, and software simulation and verification tools from Imperas enable software functional verification. When the virtual platform is coupled with Incisive Software Extensions and Imperas software verification tools, software engineers can verify the functionality of code (such as drivers) in the context of the complete OS running on the platform. This software verification capability, including white-box functional coverage, has not been possible until now. Key new technologies from Imperas (fast simulation and verification tools) and new flows (the integration between Cadence and Imperas tools) have made this possible.

Calypto Design Systems, Inc - Sept 29th, 10am

During this webinar, Calypto will describe its shared vision and provide a complete overview of how its sequential analysis-based products play a key role in today’s new era of application-driven design. The discussion will highlight the advantages of Calypto’s SLEC System-HLS product, which comprehensively verifies the RTL generated by high-level synthesis tools using its patented sequential analysis technology. In addition, Calypto will review the benefits of incorporating Cadence C-to-Silicon Compiler as well as how SLEC enables the broader adoption of TLM-driven design. Calypto will also provide a detailed review of its sequential analysis-based PowerPro products, which deliver both dynamic and leakage power savings and enable customers to produce the most energy-efficient designs possible.

Steve Brown

TLM-driven Design And Verification Methodology Book Author Interviews

Steve Brown — Fri, 06 Aug 2010 16:00:00 GMT

The recently published TLM-driven Design and Verification Methodology book has been an immediate hit, receiving critical acclaim. The authors each labored and reveled in the creation process. To give you a little insight into each author's perspective they've shared some of their thoughts about the book, the process, the content, and the future.

Brian Bailey (If video fails to open click here)

Felice Balarin (If video fails to open click here)

Michael McNamara (If video fails to open click here)

Guy Mosenson (If video fails to open click here)

Mike Stellfox (If video fails to open click here)

Yoshi Watanabe (If video fails to open click here)

Steve Brown