Axel Scherer Blog

Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013

Axel Scherer — Tue, 12 Mar 2013 14:00:00 GMT

Coinciding with the first day of CDNLive! Silicon Valley, our Udacity MOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and we are happy this day has finally come.

Last week we gave you a sneak preview of the interactivity featured in the course. However, as you all know there is nothing like trying something by yourself to really get it.

So now it is your turn. Go ahead - enroll and check it out.

To give you more motivation to enroll, we are providing you another glimpse of the course. This time the clip is from unit 2, where we model packets for a data router.

Let's verify!

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

JBYOB (Just Bring Your Own Browser): Interactive Labs on Udacity CS348 Functional Hardware Verification – No Installation Required

Axel Scherer — Tue, 05 Mar 2013 14:00:00 GMT

On February 19, we announced the launch date for our Udacity MOOCs course: CS348 Functional Hardware Verification, which will launch in exactly one week from now on March 12, 2013.

When we communicated the launch date, we also released the first clip of the first unit.

Now we want to give you a glimpse of one the coolest features of this course: Interactive labs executing in the web browser.

The best way to describe it is to give you a short demo that shows you how this works, even before you can try it out yourself.

The first time I saw this it totally blew my mind. No installation, no setup of labs, everything is fully sandboxed!

Just enroll here, and when the course is live log into the course on a web browser, and you are ready to go. It's simply amazing!

Get ready to code!

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

It’s Coming: Udacity CS348 Functional Hardware Verification Course Launches on March 12, 2013

Axel Scherer — Tue, 19 Feb 2013 14:00:00 GMT

On October 18, 2012 Google, NVIDIA, Microsoft, Autodesk, Cadence and Wolfram announced their collaboration with Udacity. Working with Udacity, each of the companies listed above is developing new massive open online courses (MOOCs).

The Cadence contribution is CS348 Functional Hardware Verification.

You can enroll in this course by clicking on "Add to my Courses" on this page.

https://www.udacity.com/course/cs348

Today, we are happy to announce that our course will launch on Tuesday, March 12, 2013. The full course consists of 9 units and will include industry cameos from several distinguished engineers from different companies around the world. These engineers provide additional perspective to the topics of the particular units in the course.

To give you a little taste of the course, we are releasing the first clip of the first unit today.

As you watch the video, you will notice this is going to be different.

One key aspect that is not shown in the first clip is the high level of student engagement and interaction. Besides micro-lectures, the course will contain lots of interactive quizzes and many online coding exercises to ensure the concepts are well understood and can be put into practice immediately.

We will preview some of the interactive capabilities in the next weeks.

This is the list of units:

Introduction to Hardware Verification
Basic stimulus modeling and generation
Interfacing to the Hardware Model
Monitoring and Functional Coverage
Checking
Aspect Oriented Programming
Reuse Methodology
Debugging
Conclusion and Exam

The course will be completely self-paced, which means you can take it at your own pace and leisure.

Finally, the course will close with a final exam and Udacity certificate to show your performance.

Get ready to verify and check for course news on Facebook and Twitter!

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

Do you MOOC? Expanding Access to e (IEEE 1647) Verification Training Globally

Axel Scherer — Thu, 18 Oct 2012 16:00:00 GMT

Two of the key factors for successful and productive simulation-based hardware verification are an efficient verification language and an associated methodology. As the global design and verification eco system is scattered and evolving rapidly, it is hard to keep all engineers trained.

We are looking at MOOCs, Massive Open Online Courses, as popularized by organizations like Khan Academy, to address the need for more accessible and globalized training. To determine how MOOCs can be applied to verification training, we are partnering with Udacity, one of the premier players in this field.

MOOCs require a very different approach. Repurposing traditional, in-person training is not sufficient. The challenge is to keep students engaged while keeping the material at a high standard. This is not trivial, as online users can be distracted very easily and the online drop out rate is even higher than in the real world.

Our class on Udacity is called: Functional Hardware Verification: How to verify chips and eliminate bugs. More information on this class can be found here:
http://www.udacity.com/overview/Course/cs348/CourseRev/1

Udacity announced our class and classes from other industrial partners such as Google, Microsoft, AutoDesk, and Wolfram, in their press release today

See the promotional video below.

Get your MOOCs on!

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

Speed of “Light” – My First iPhone 5 Impression

Axel Scherer — Fri, 21 Sep 2012 18:00:00 GMT

So what’s the big deal with the iPhone 5?

Some folks have commented: "It is just a bit faster, taller, lighter – no big deal."

Let me tell you one thing: Seeing, no handling and touching is believing. Like so many devices in the past, you have to try it yourself to appreciate it. It is a similar experience as with the original iPhone and iPad.

The minor weight difference actually makes a huge difference in holding and handling the device. It feels unbelievably light and still very sturdy.

The other major take away is speed. It is particularly noticeable in web browsing. (See video below.) The engineering efforts put into the A6 SOC have paid off. It is very impressive!

As expected the build quality is superb. It is a very noticeable improvement over the iPhone 4S. I love great, high quality tools and hardware. The iPhone5 is smoking and takes the crown.

Go check it out for yourself.

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

The Cowbell Rings On – We Have Completed the “UVM SystemVerilog Basics” Videos in Chinese

Axel Scherer — Tue, 04 Sep 2012 13:00:00 GMT

In July we released 12 videos of the UVM SystemVerilog Basics series with Chinese audio . Now we are completing the set and releasing the remaining 13 videos.

Once more I would like to thank my colleague, Yih-Shiun Lin for his great job in translating the audio. It is his voice you hear on these videos.

Besides releasing the videos to YouTube, we are also publishing them on

YouKu, the Chinese version of YouTube.

Link to YouTube Playlist (Chinese)

Link to YouKu Playlist (Chinese)

Link to YouTube Playlist (English)

Link to YouKu Playlist (English)

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus

Axel Scherer — Wed, 01 Aug 2012 13:30:00 GMT

Ernie & Duracell

"I feel great" - long pause - "I feel great, I feel great".

6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great".

I hear this sound coming out of my son's room. What is going on in my house? Is there such a thing as too much euphoria? No, sometimes my son does utter this phrase, but most of the time it is coming from an Ernie toy he inherited from his cousin several years ago.

This particular toy is over 14 years old and still "feels great". We had it for over 5 years. So, by now the batteries should have given up. Nonetheless, we still get these random, out of the blue utterances of the phrase: "I feel great". This is supposed to be triggered by some sort of child-toy interaction. However, it mutated into sound generation at random intervals. This phenomenon is very bizarre, as the pauses are very long, causing completely random operation.

The other day the toy went off again: "I feel great". My suspicion was that this might wake up my son in the middle of the night. As Ernie's electronics and wiring obviously have some issues, and as Ernie does not have an on/off switch, my first recourse was to remove the batteries.

To my surprise, the batteries are more than 10 years old and we have never replaced them since we received the toy. The circuit is not supposed to draw a lot of current. However, it is always on and ready to "speak". Overall, this is pretty amazing battery longevity - Hats off to Duracell!

Moving From Sesame Street to the Real World

In verification, your goal is to put the DUT into all known scenarios, and as many unknown scenarios as possible. Constrained random test generation is particularly helpful in achieving the latter. In e [IEEE 1647] constrained random generation is front and center. It is a core principal of the e language and the associated methodology. By default, everything, every aspect and every field, is random in e. This will ensure that you get to as many unknown and unanticipated scenarios to test your device as thoroughly as possible, and that you identify the associated bugs during simulation.

When everything is random by default you are not at risk of forgetting to randomize any aspects. Consequently, you are less dependent on the quality of your coverage model to detect flaws in the test generation ability of your environment.

JL Gray, VP of Verilab North America puts it like this : "Setting up a verification environment where you have to decide what not to randomize ends up being far more randomized in the end than one where you have to decide what to randomize."

Another effect of default randomization is that it enables early bug detection. More randomization shakes out more bugs. Since detecting bugs early is less costly than detecting them later, this has a positive impact on the overall verification cost.

Default randomization does not imply that you bring up your environment with the wildest transactions imaginable. You still control what you want to see initially. However, it does mean that you are typically moving to a high level of randomization more quickly.

This principal of a default randomized environment, is called Infinity Minus (∞-) and is illustrated by the following code:


// apb_trans_s.e (abridged file) - sequence item definition
struct apb_trans_s like any_sequence_item {

   addr : 		uint;
   data : 		uint;
   direction :	read_write_t;
   delay :		uint;

   ...
}

In this simplified and abridged example of an APB transaction definition, all fields are randomized by default. In other words, you get random addresses combined with random data, random direction (read or write), and random delays between transactions. Subsequently, you impose rules by adding constraints and reigning in the randomization to suit your particular testing needs.

E * D ≈ ∞- Ernie * Duracell ≈ Infinity Minus

The broken electronics in the Ernie toy, and the almost infinite longevity of the Duracell batteries, are behaving just like they are driven by an infinity minus stimulus generator. Ernie feels great at random times, but you will feel great all the time knowing your designs have been verified using the infinity minus verification approach.

Keep on verifying!

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

Global Cowbell Fever Spreads – We Are Launching 12 “UVM SystemVerilog Basics” Videos in Chinese

Axel Scherer — Mon, 23 Jul 2012 13:30:00 GMT

A little over two and a half months ago we started sounding the "cowbell" with the release of the UVM SystemVerilog Basics videos.

The resonance has been strong. As there can (almost) never be too much of a good thing, we are expanding this series by re-releasing the videos audio dubbed into Chinese.

We are kicking it off with the first 12 videos titled:

I would like to thank my colleague, Yih-Shiun Lin for his great job in translating the audio. It is his voice you hear on these videos.

Besides releasing the videos to YouTube, we are also publishing them on YouKu.

http://www.youtube.com/playlist?list=PLA1A32A7461300910

http://www.youku.com/playlist_show/id_17869812.html

We plan to complete the audio translation for the remaining tracks in the future - So stay tuned to this blog so you don't miss any of them.

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

UVM SystemVerilog Class Library Overview Video – Inspired by 1600 Cowbells in Action

Axel Scherer — Mon, 16 Jul 2012 13:30:00 GMT

Just after releasing the original cowbell video series I found that Ben and Jerry's had discovered a great way to combine cowbells and charity. In April of this year, they held an event for a new world record of over 1600 cowbells in action. It is a must see for the cowbell aficionado.

Coincidentally, this happened up north in Burlington, Vermont, which is the home of the University of Vermont. As the University has been using the acronym UVM much longer than us, a lot of confusion in Internet searches can occur.

For example if you google "UVM library" you end up with this. However, if you want to know more about key aspects relevant to UVM SystemVerilog library users, you want to check out our latest cowbell video.

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer

My Clark Kent Moment – How I Discovered Aspect Oriented Programming in e (IEEE 1647)

Axel Scherer — Tue, 10 Jul 2012 16:00:00 GMT

Growing up on VHDL, moving on to Verilog and then to SystemVerilog, I eventually discovered e (IEEE 1647)

Initially I thought: "What is the fuss all about?"

While exploring the language during the development of the cowbell videos, it hit me -- I started to recognize the power of Aspect Oriented Programming (AOP). Indeed, it is the antidote to Verification-Kryptonite!

Let me explain my newfound capabilities. When you verify complex systems you will certainly end up in situations where you have to deal with unanticipated changes to the original requirements, as well unanticipated requirements of your verification environment. These are just two of many areas where AOP can provide enormous flexibility and efficiency.

Using AOP you can take any environment, and with a flip of a finger change the behavior of any component, transaction type, coverage model or the entire system. The best part is, this can all be done without altering your existing code base. Therefore, code maintenance does not need to compete with flexibility any longer.

Consider the following situation. It is summer and the project is well underway. You are writing and running some tests and you encounter a bug. In your team, the roles and responsibilities are clearly separated and you need information that the current verification environment does not provide. However, the person owning the verification environment is on vacation.

This dilemma can have serious consequences on productivity.

Even if a backup resource for the verification environment is available it would still take time and effort to communicate what you need. In addition, you are introducing risk by altering code, and potentially adding bugs. Lastly, you are dependent on another player the team. Altogether you are in a bad place.

With AOP, however, you can mitigate the risk, break the dependencies, and create flexibility. In fact, you can add the required functionality to the verification environment from the outside, without having to bother anyone, and without touching the existing, stable environment.

To be more specific, let's say you need to log the start time when an APB transaction is driven. Traditionally, you would have to add a field to store the value of the transaction in the sequence item file, and then you have to change the method call in the BFM file. Instead, with AOP, you just create a new extension file for your particular debug purpose. For example:

// apb_trans_s.e (abridged file) - sequence item definition - unaltered struct apb_trans_s like any_sequence_item { addr : uint; data : uint; ... } ---------------------------------------------------------------------------------------- // apb_master_bfm.e (abridged file) - BFM definition - unaltered unit apb_master_bfm like apb_bfm { ... drive_transaction_address (cur_transaction : apb_trans_s) @tf_phase_clock is { ... } } ---------------------------------------------------------------------------------------- // debug_start_time.e - (entire file) - extension with AOP extend apb_trans_s { start_time: time; }; extend apb_master_bfm { !history_list: list of apb_trans_s; drive_transaction_address () @clk is first {
cur_trans.start_time = sys.time; history_list.add(cur_trans); }; };

In this example you added a new field, start_time, to the sequence item and you added additional functionally to the beginning of the drive_transaction_address method of the BFM.

After you load this extension file in your next simulation run, you automagically gain new features in your environment using AOP without introducing risk to other users and without depending on another person.

After trying this on some examples I felt as if my inner Superman had been unleashed and I had gained a new superpower.

Unleash your superpower too, with AOP.

Axel Scherer
Incisive Product Expert Team
Twitter, @axelscherer