Rahul Deokar Blog

DAC 2010 – A “Coming Out” Party For 3D-IC Design

RahulD — Mon, 28 Jun 2010 22:51:00 GMT

Overall, the 2010 Anaheim DAC was livelier than the years before. Customer and vendor faces were not long and serious, but more purposeful and forward-looking. The recent M&A activity also brought in some rays of sunshine. The EDA360 vision for the entire industry resonated with a wide gamut of system companies, IDM's, ASIC/IP vendors and foundries. And, the hottest topic this year definitely was 3D-IC (Stacked Die). Most folks talk about the Denali party, but DAC #47 was indeed a "coming out" party for 3D-IC design, and three events stood out.

The first one was "Hogan's Heroes: What Nightmares will 22nm Bring?" This panel had participants from Qualcomm, Xilinx and D2S, and was chaired by Jim Hogan, Vista Ventures. They discussed and debated how the limits of lithography will impose new rules for designers, and discussed the industry impact. They agreed that the biggest factor they would lose sleep over at 22/20nm is "cost"...not performance, power, time-to-market but "cost." They also pointed out that costs of double-patterning (which is a must at 22/20nm) are orders of magnitude higher than traditional methodologies up until 32/28nm. And, that makes alternative solutions like 3D-IC viable alternatives to achieve the next scale of SoC integration, without having to weather the risks of migrating to advanced process nodes.

The second event was a GSA (Global Semiconductor Association) Birds-of-a-Feather event on 3D/TSV (through-silicon via) with an overwhelming 125+ attendees. Herb Reiter and his team brought together representativies from major foundries, IDMs, EDA/IP vendors, design services and other industry organizations to accelerate 3D design. The open forum and discussion were definitely a right step in that direction to not only ensure good tools for cost-effective 3D designs, but also to minimize risk and shorten time-to-profit for the companies that design and manufacture 3D ICs.

The importance of extending today's 2D tools to handle 3D design was realized, given widespread market acceptance and usageof 3D ICs. Only then will IC and system designers be able to cost-effectively and efficiently integrate multiple 2D SoCs into 3D systems. In addition, in the GSA market survey of semiconductor companies that asked about EDA vendors with 3D/TSV support, it was satisfying to see Cadence (38%) leading the pack (Mentor is 25%, Synopsys is 18%).

The third event was a panel entitled "3D Stacked Die: Now or the Future?" with speakers from TSMC, Samsung, IMEC and Qualcomm. The good news is that all the panelist companies have already moved beyond traditional 2D design techniques and are utilizing key advantages of the third dimension. These companies might be in different stages of the adoption/deployment curve, but all of them consistently and clearly see a path to fully take advantage of 3D IC design.

Also, the speakers highlighted that the first wave of 3D devices would be hitting the market this year. Actual production designs with real silicon, and in real consumer products! This first batch would primarily have memory on one die and the rest of the SoC on another die. This makes sense since embedded memory takes a large portion of the design, thus growing die-size and decreasing yield. Embedded memory also consumes more power and limits bandwidth, as compared to stacking memory on top of the logic dies.

All in all, the refeshing take-away was that the industry has clearly answered for itself the question: "Is 3D design now or the future?"

The answer is an emphatic "Now." 3D design is certainly happening now and at a rapid pace. And, companies not considering 3D IC design face the risk of missing the boat and being left behind.

Rahul Deokar

EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

RahulD — Fri, 16 Apr 2010 15:00:00 GMT

Every April the leading edge of the leading edge of semiconductor industry meet at the Electronic Design Process (EDP) Symposium to address design problems that make design more difficult than it should be. This was my first visit and chance to rub shoulders with the industry's gurus and to discuss the arc and future of EDA tools and the EDA industry.

The nice thing about the EDP symposium (often referred to as the "secret DAC") is that it favors open discussions around presented papers. It is a sound mix of academic and industrial research and experiences and the goal is to foresee what the coming design problems might be and propose either solutions or alternatives. This year, the programme included a number of interesting topics including parallelism/cloud-computing for EDA, high level design/ESL, and 3D ICs.

I had the privilege to present on 3D IC design - particularly the latest work/trends around Through-Silicon Vias (TSV). For those of you that are new to this area, here's an interesting article that helps understand the foundational elements: http://www.cadence.com/Community/blogs/di/archive/2010/03/29/My-DATE-With-3DIC-Technology.aspx. The beauty and promise of this new technology is that it can inject a fresh breath of air into the semiconductor industry and give life to a whole new world of consumer end-applications. It can provide a huge paradigm shift to what can be achieved in design performance, power, and form factor.

The inconvenient truth is that the semiconductor industry is at crossroads. The cost of doing design in the traditional 2D methodology is getting exhorbitant. For instance, designing at 32/28nm incurs 3-4X the cost of design at 45nm (spanning fabrication costs, design costs, process and mask costs). Additional manufacturing effects like lithography, chemical-mechanical polishing, stress, and double-patterning are rendering the move to advanced process nodes exceedingly difficult. To make matters worse, we get hit with a double-whammy since the time-to-production on advanced process nodes has increased significantly, and that takes its toll on the profit margins for the industry.

And, this is where the new 3D/TSV solution shows promise to be the panacea to the industry's ailments. The biggest benefit it offers is the flexibility of heterogeneous integration. Designers no longer need to move the entire System-on-Chip (SoC) to the latest process node, thus eliminating a lot of the risks, costs and time-to-market delays. Design companies can choose to keep their analog, full-custom and memory IP at the older, safer process nodes while they move the aggressive CPU/GPU/digital logic to advanced process nodes. Essentially, designers now get the best-of-both-worlds by mitigating the cost, complexity, risk, and development time. And the end-result is smaller and faster and lower-power.

Thomas Williams from Future Tech and Sungkyu Lim from Georgia Tech also talked about 3D/TSV in their presentations. An interesting way of looking at the cost savings from 3D/TSV is the following: Let's take a traditional methodology for an SOC chip on a signle die with dimensions (L x L). The footprint/area of this device would be L² and the corner-to-corner distance would be 2L. Now consider this chip to be implemented in 3D as a stack of 4 dies with each die dimensions of (L/4 x L/4). The footprint/area of this device would be L²/4 (one fourth of the original). The corner-to-corner distance would be much smaller to the original as well (L + h, where h is the height of the stack). And this reduced area and corner-to-corner wire-length is what effectively translates to significant benefits in performance and power for the 3D/TSV methodology.

In the real world, I see several semiconductor companies are now taping out real production chips. Some of them are also using "Silicon Interposers" which are silicon platforms with TSVs and enable different dies to be connected. It looks like the light at the end of the tunnel is real, and not just a false hope. While this technology and approach might not be for everybody (as was righly debated at the EDP symposium), it is certainly is a differentiating strategy for the select few semiconductor vendors who have embarked on this 3D/TSV path.

Have you looked at this 3D/TSV technology? What's your take on it?

-Rahul Deokar

ST Microelectronics – A Fountain-head of Design Innovations

RahulD — Thu, 22 Jan 2009 21:59:00 GMT

In my last blog, I asked all of you to send me your design innovations. Thanks for your over-whelming response…and keep the emails coming in. And what better way to start the New Year than to talk about ST Microelectronics and its innovations!

I’m pretty darn sure that most you have heard about the company. But for those of you that haven’t, ST Microelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. The company is at the forefront of System-on-Chip (SoC) technology with a rare combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partnerships, and innovative products.

Here are a few of the recent design innovations that have flowed out of the ST Microelectronics fountain-head:

STDP3100 - World’s first single-chip DisplayPort-to-VGA converter aids in the rapid transition to DisplayPort as the next-generation display interconnect standard targeted for cable adapters, notebook motherboards, and docking stations( http://www.st.com/stonline/stappl/cms/press/news/year2009/p2358.htm)

STA339BWS - World’s first single-chip audio power amplification with advanced DSP processing features such as MultiBand DRC targets next-generation flat-panel TVs and other small form-factor sound systems (http://www.st.com/stonline/stappl/cms/press/news/year2009/p2359.htm)

STi7141 - World's first single-chip device with support for high-definition TV, and sophisticated DVR (Digital Video Recorder) targets Innovative High-End Cable TV Services with Single-Chip Set-Top-Box IC Combining High-Definition and Interactive Capabilities (http://www.st.com/stonline/stappl/cms/press/news/year2009/p2356.htm)

Frankly, it’s a great pleasure for Cadence to be working in close collaboration with such a world-class design company and helping introduce such tremendous design innovations. Here’s a recent announcement about how ST Microelectronics used the Cadence Encounter Digital Implementation System on 40- and 32-Nanometer flows (http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=012109_st).

And for further insights into the in-depth capabilities of the new Encounter Digital Implementation System, you can check out a recently published interview: http://www.ciol.com/Semicon/SemiSpeak/Interviews/Cadences-Encounter-to-take-on-Synopsys-Galaxy/16109114916/0/

Cheers to a new and hopeful 2009…as we tackle together advanced design challenges with new innovations. And yes, keep sending me your design innovations.

-Rahul

It’s the Season of Giving – Send Me Your Design Innovations!

RahulD — Fri, 19 Dec 2008 19:17:00 GMT

In the last blog, I wrote about innovating your way out of recession with new designs that address new challenges/requirements in new ways…and how the new Encounter Digital Implementation System can help. To further assist you on that front, we are setting up an "Encounter Office Hours" with Bob Dwyer. Bring your Encounter questions to a "live blog" on Friday January 9th at 9:00 am EST. More details to follow.

Now, let's learn how we can make innovation work for you. Despite the enduring myth of the lone genius, innovation does not take place in isolation. Truly productive invention requires the meeting of minds from myriad perspectives, even if the innovators themselves don’t always realize it. Keith Sawyer, a researcher at Washington University in St. Louis, calls this “group genius”.

And, to trigger that innovation process, I am seeking your involvement…as a group. I want to recognize semiconductor design technologies, applications, and products that have been unique and beneficial to the industry...recognize our history…so it can further spark off upcoming innovations.

But, I can’t do it alone…I need your help! I want to hear from all of you…your design achievements in the semiconductor design world. Remember nothing is too small or too silly…just send it my way:

From achievements on the end chips (fastest, smallest, largest, coolest) to
Achievement in fab innovations (CMOS, SOI, High-K metal Gate etc.) to
Achievements in circuit style innovations (Dynamic Logic, Pulsed Latch, etc.) to
Any other whacky, crazy achievements

Well, I need to signoff for the year…as I relax over the holidays and spend time with the family…and help my 3-year old innovate with play-dough.

I wish you all the happiness this season can bring. May it follow you throughout the coming Year 2009!

Cheers,

Rahul

Innovate Your Way Out of Recession With the New Encounter!

RahulD — Wed, 03 Dec 2008 14:15:00 GMT

It's official! The U.S. economy has been in a recession for the past year.

And, the global credit crunch and economic recession has pulled the semiconductor industry down to the point of entering its eleventh recession.

"I'm sorry it's happening," said US President George W. Bush, referring to the global financial crisis. In fact we are all sorry but we can’t be moping around, can we? As the ex-Intel chief executive, Craig Barrett, argued "Regardless of what happens, the only way to get out of a recession is with new products. Collectively, we need to invest and bring new technology into the market."

Indeed, companies must design to innovate their way out of recession. And to help you do just that, we are launching the innovative Encounter Digital Implementation System - a next generation high-performance, high-capacity RTL-GDSII design closure solution for advanced node, ultra large-scale, ultra performance/power design flows. Encounter Digital Implementation System offers the Industry’s first end-to-end parallel-processing solution that enables all steps of the design flow to be multi-CPU enabled - from floorplanning, placement, routing, extraction to timing and signal integrity signoff, resulting in the fastest (high velocity) path to best quality of silicon. You can read more about Encounter Digital Implementation System at http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=120308_edi

Encounter Digital Implementation System can help you tackle the worst of your challenges on leading-edge 45- and 32-nanometer designs – with 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1GHz, ultra-low power budgets, and large amounts of mixed-signal content. It has been developed working in close collaboration with over 20 customer partners who have extensively used, validated and now, deployed it. You can read more about customer comments and feedback at http://www.cadence.com/cadence/newsroom/features/pages/feature.aspx?xml=edi

I invite you to experience and explore all aspects of the new Encounter Digital Implementation System, and in the process become a specialist in the latest requirements and techniques to address complex flat and hierarchical design closure, advanced signoff, low power, mixed-signal, and advanced node design. Of course, to keep it exciting, we’ve got great prizes you can win along the way. Find out more at http://www.cadence.com/products/di/encounter/pages/default.aspx

Remember, a recession can actually provide you an opportunity to break away from the pack. So, how can you overcome the paralysis in a recessionary environment? How can you create success while others sit on the sidelines, waiting it out?

Innovate your way out of the recession …with the new Encounter Digital Implementation System!

Need for dynamic IR drop analysis at floor and power planning stages?

rahuld — Mon, 08 Sep 2008 14:00:00 GMT

Here is a question for all the power grid designers out there: Do you see the need to do quick early dynamic rail analysis during floor and power planning stages of our design? With introduction of the Cadence Encounter Power System today, Cadence First Encounter and SoC Encounter users will have access to the Encounter Power System signoff engines during floor or power planning design stages at no additional cost.

This analysis, called Early Rail Analysis (ERA), allows correct-by-construction power grid design. Designers can quickly draw current regions, leverage the Encounter Power System power engine if needed, use fast extraction and virtual connectivity to quickly analyze optimal location for their IOs, blocks and power grid mesh.

The consistency of the engines during ERA, optimization and signoff shortens design cycles and avoids last minute signoff surprises ERA currently allows only static power and IR drop analysis, but a few customers have asked us for ability to do dynamic ERA as well.

This would allow study of the grid at floor and power planning stages using block current signature and capacitance as inputs. I am very curious to know what other designers think about this feature.

Do you see a significant use for it?

Statistical Timing Analysis - Has its time arrived?

RahulD — Mon, 21 Jul 2008 18:57:00 GMT

At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. STA compensates for this variability by requiring aggressive guard bands and by using multiple corners or scenarios to reflect different manufacturing conditions.

However, this old fashioned deterministic STA still remains popular amongst mainstream designers and for good reasons:

Fast runtime - linear in circuit size (for the basic algorithm).
Conservative results - inherent pessimism built-in.
Simple libraries (typically delay and output slope as a function of input slope and output load).
Easy extension to incremental operation for use in optimization.

On the other hand, while STA has been very successful, it still has a number of limitations, which are getting magnified at lower process nodes:

Aggressive guard-banding minimizes/eliminates all advantages of moving to a lower process node.
Needs many corners to handle all possible cases and might still miss silicon failures. As the number of analysis runs increases, it makes design convergence exceedingly difficult while straining resources, increasing costs, and negatively impacting schedule.
Cannot easily handle within-die correlation, especially if spatial correlation is included.
If there are significant random variations, then in order to be conservative at all times, it is too pessimistic to result in competitive end-products.
Changes to address various correlation problems, such as CPPR (Common Path Pessimism Removal) make the basic algorithm slower than linear time, or non-incremental, or both.

Statistical STA (SSTA) attacks these limitations more or less directly. First, SSTA uses sensitivities to find correlations among delays. Then it uses these correlations when computing how to add statistical distributions of delays. SSTA makes it possible to break through the barriers of corner analysis and holistically model the many factors affecting process variation in a single analysis run. It enables designers to effectively model process and environmental variation, it obviates the need for multiple corners, and it removes much of the inherent pessimism. SSTA allows for reduced guard-banding, which results in decreased area, decreased power consumption, and improved chip performance.

However, some mainstream designers still prefer to sit on the fence and and wait for early adopters to employ SSTA. A number of criticisms are leveled at SSTA:

It's too complex, especially with realistic (non-Gaussian) distributions.
It's hard to couple to an optimization flow or algorithm.
It's hard to get the data the algorithm needs.

I would love to hear what you think about SSTA. Feel free to share your experiences and thoughts on traditional STA, process variation/corners and SSTA. And in upcoming blogs, we can explore how SSTA is becoming more of a reality. How the past limitations are being addressed and how it is becoming a useful weapon in the designer's arsenal. Until then...

Signing Off,

-RahulD