https://community.cadence.com/searchen-USTelligent Community 11en-usnoSearch resultshttps://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59460/extract-the-list-of-devices-used-in-the-layoutSun, 26 May 2024 07:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59460Vishesh Gupta/cadence_technology_forums/f/custom-ic-design/59460/extract-the-list-of-devices-used-in-the-layout0 Hi, I submitted a layout design for the tapeout. The company wants to confirm that they are using the correct flow and therefore want to extract the list of devices (pcell names) used in my design. Can someone help me how could it be done? Thanks and Regards, Vishesh https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398403#1398403Sun, 26 May 2024 07:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398403Vishesh Gupta/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398403#1398403 Thanks a lot Frank for the suggestion. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398402#1398402Sun, 26 May 2024 07:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398402Vishesh Gupta/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398402#1398402 Thanks a lot Andrew for helping. Regards, Vishesh https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/59459/error-orprobe-3133-when-measuring-slew-rate-of-max44284h-in-pspiceSun, 26 May 2024 06:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59459WillChen072/cadence_technology_forums/pcb-design/f/pspice/59459/error-orprobe-3133-when-measuring-slew-rate-of-max44284h-in-pspice0 I am currently testing the slew rate of the MAX44284H current-sense amplifier using PSPICE. When I use the "Evaluate Measurement" function to measure the falling edge slew rate (SlewRate_Fall(1)), I encounter the following error message: ERROR(ORPROBE-3133): Measurement not evaluated due to Measurement search failure 1 How can I resolve this error to correctly measure the falling edge slew rate of the MAX44284H using the slewrate_Fall(1) function in the "Evaluate Measurement" tool? Are there any other settings or methods that could help solve this problem?Thank you for your assistance! https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59439/how-do-i-get-a-click-event-on-schematic-in-my-orcal-tcl-code/1398401#1398401Sat, 25 May 2024 12:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398401Jadystone/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59439/how-do-i-get-a-click-event-on-schematic-in-my-orcal-tcl-code/1398401#1398401 If I can get the sch window handle, it will work. I think the bind code should be: bind $psch_window {handleClick} Probem is how can I get the $psch_window. Current my temporary solution is replacing " vwait clicked" with update after 1000 That can let me to get a click position on sch page. But it must click the sch window within a second. Otherwise It could get a false position that I don't want. https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398400#1398400Sat, 25 May 2024 08:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398400srish09/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398400#1398400 You can try updating the reference designators through de-hdl console commands and change editor. Check this article: Article (20493540) Title: How to update multiple part references in Concept HDL design at once URL: support.cadence.com/.../ArticleAttachmentPortal https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59435/re-run-monte-carlo-failures-for-two-step-trim-simulations/1398397#1398397Fri, 24 May 2024 21:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398397TempViator/cadence_technology_forums/f/custom-ic-design/59435/re-run-monte-carlo-failures-for-two-step-trim-simulations/1398397#1398397 After some experimenting, the issue here boils down to a Normal vs. Troubleshooting run and how calcVal passes information. For the bulk of operating sims, I use the calcVal function in a way that passes data assuming that the trimming and post-trimming tests occur in the same run and sequentially: calcVal("Trim_VBG_best" "VBG_Trim" ?cornerName "Trim" ?defaultVal 0) But what I really need is for calcVal to pull info from the successful VBG_Trim test and pass it to the Troubleshooting rerun of the next test. The only way I see to do that is to separate the rimming run into a stand-alone simulation that writes its data, and then set up the calcVal reference to an already-completed test results, perhaps like this: calcVal("Trim_VBG_best" "VBG_Trim" ?cornerName "Trim" ?historyName "VBG_Trim_Only" ?defaultVal 0) where VBG_Trim_Only is the name of a stand-alone sim that only trims, but does not run post-trim sims. I have not yet searched for it, but I think there is some detail to making sure the Monte Carlo run sequence is the same for two separate simulations...this is necessary to make sure the trims correlate to the right post-trim sims. Is there a simpler way to make the Troubleshooting reruns pick up the calcVal info? And am I missing a step in getting this to work, as described above? Thanks for any useful replies! https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398396#1398396Fri, 24 May 2024 18:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398396Son/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398396#1398396 Thanks rg13 for your responding. My current schematic has the Ref Des "J605". How can I add "09" into this Ref Des after "J" and before "605" J605 => J09605 I can do manually but I'd add "09" for entire schematic. Thanks, Son https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/59457/ability-to-simulate-audio-wav-filesFri, 24 May 2024 17:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59457AyushD/cadence_technology_forums/pcb-design/f/pspice/59457/ability-to-simulate-audio-wav-files0 Audio simulation can be helpful for acoustic analysis in medical hearing aids, audio tuning in audio amplifier, etc. Are you finding it difficult to simulate .WAV audio files? From 23.1 ISR 4 onwards PSpice A/D has been introduced with ability to support audio simulation. You can use this amazing feature and simulate audio input files used in circuit design and generate electronic/digital audio as output by using the WAVESRC component in PSpice. You need to place the WAVESRC component from Component Explorer window and add the following properties. Channel: Information of the channel Path of audio file (.WAV format) to be imported. Explore this feature and let us know how you are using it in your projects. Team DesignTech Cadence Design Systems https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59456/is-there-is-a-method-to-compress-the-pcb-symbol-file-sizeFri, 24 May 2024 17:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59456gvellet/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59456/is-there-is-a-method-to-compress-the-pcb-symbol-file-size0 Hi, I have designed a complex PCB symbol, then I mapped a step model. Unfortunately the step model was large (24MB) and it resulted in the symbol file of about 6MB. Recently I found another STEP model which is much smaller. I thought lets update the symbol with this new model, it will make the symbol file size much smaller. Unfortunately, the symbol file size remained almost the same. it seems that the space taken by the previous step model is not freed up. I looked in all the menus of Orcad pcb editor but I could not find any function to clean the symbol file size. I made a test by deleting all pins, shapes, step, and lines. I kept only the refdes and saved the symbol but still the filesize is a large 5MB. It seems that I have to redesign the symbol from scratch if I want a smaller file size. Anyone has a suggestion? Thanks https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59453/resolving-drc-errors-for-blind-vias-on-bga-pads-in-allegro/1398395#1398395Fri, 24 May 2024 15:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398395avant/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59453/resolving-drc-errors-for-blind-vias-on-bga-pads-in-allegro/1398395#1398395 Can you set "pad-to-pad connect" to allow via on pin? You could use a physical constraint region to allow it in a specific area only. https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398394#1398394Fri, 24 May 2024 14:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398394rg13/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398394#1398394 You can achieve it by defining the REFDES_PATTERN for your design. In this case you can define refdes_pattern as follows: “($PHYS_DES_PREFIX)(09)[0-9](1)” For more details on this, you can refer Application Note "Practical Applications of REF_DES_PATTERN" by following link from Cadence online support portal: Article (20416521) Title: Practical Applications of REF DES PATTERN URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050Q0EAI Let me know how it goes. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59450/library-manager---open-terminal-option-on-right-clicking-any-cell-or-views/1398393#1398393Fri, 24 May 2024 14:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398393firebolt3/cadence_technology_forums/f/custom-ic-design/59450/library-manager---open-terminal-option-on-right-clicking-any-cell-or-views/1398393#1398393 My admin has enabled failsafe for all applications including virtuoso which gets auto-killed after certain period of time. This leaves lock files. Also, can we add option like fix lock file under right click? I have seen coth state option in one of old project. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398392#1398392Fri, 24 May 2024 14:43:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398392Mabr86/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398392#1398392 Ok, thank you for your quick response. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398391#1398391Fri, 24 May 2024 14:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398391AurelBuche/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398391#1398391 Then no, there is no trivial way to just define the `greet' procedure. That is why it is advised to write SKILL files that only define procedures (except for what you call the "main" program) So they can be loaded and their procedures can be called individually In your case, you could write a function that parses the SKILL expressions inside a given file (usually this is done using `lineread') and only evaluate the S-expressions starting with `defun' or `procedure' but I would advise you not to do so as this is very unusual. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398390#1398390Fri, 24 May 2024 14:32:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398390Mabr86/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398390#1398390 For example... Content of the sub-program: printf("test") procedure(greet() printf("Happy Birthday") );end procedure ... Now, in the main program I want to call the sub program above. But just the procedure "greet()" should be executed, not the "printf(test")". https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398389#1398389Fri, 24 May 2024 14:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398389AurelBuche/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398389#1398389 Hi, Your question is so vague... are you even talking about SKILL? An example of what you have and what you want to achieve would be welcome. Let's assume what you call the main program is Virtuoso and that you want to call a specific SKILL function. If you have a file like ~/skill/example.il which contains : (defun example_procedure () (info "calling `example_procedure'") ) Then yes, you can load this file in Virtuoso and then call `example_procedure'. CIW> (load (simplifyFilename "~/skill/example.il")) -> t CIW> (example_procedure) calling `example_procedure' -> nil If your file is not defining functions but running code directly, this can be very dangerous, as shown in the following example : The file ~/skill/example.il could contain (deleteFile ...) And when loading them you might erase files. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-programFri, 24 May 2024 14:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59455Mabr86/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program4 Is it possible to only execute a specific procedure of a sub-program when opening this sub-program from the main program? https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59443/exporting-variants-lst-through-tcl-or-automation/1398388#1398388Fri, 24 May 2024 13:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398388PatEscher/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59443/exporting-variants-lst-through-tcl-or-automation/1398388#1398388 Hello Vishwajeet, unfortunately this brings up the UI which requires a user input. I am looking for a full automation, so without User Input. is there a possibility to control the UI also through an xml file, like when switching to the variant view (even if controlling the UI is not really a good practice :) https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59443/exporting-variants-lst-through-tcl-or-automation/1398387#1398387Fri, 24 May 2024 13:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398387Vishwajeet Singh/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59443/exporting-variants-lst-through-tcl-or-automation/1398387#1398387 Try using following steps: 1. Enable Journaling and Display Commands from Extended Preferences > Command Shell. 2. Now, select and right click on the design file in the project manager and open Part Manager. 3. Copy MenuCommand number from the command window and replace it in the below code in place of 14604 > set lSession $::DboSession_s_pDboSession DboSession -this $lSession set lNullObj NULL set lDesign [$lSession GetActiveDesign] if { $lDesign != $lNullObj} { MenuCommand "14604" Menu "Tools::Export Variant List" return } 4. Run the TCL script in the command window and Hit Export it will create variants.lst file. Hope this helps!