https://community.cadence.com/search?q=*%3A*&category=blog&users=36232&sort=date%20desc&Redirected=trueen-USTelligent Community 12https://community.cadence.com/cadence_blogs_8/b/di/posts/cadence-learning-and-support-installation-licensing-help-also-available-via-chatbotFri, 05 Apr 2024 12:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1361974MJ Cad/cadence_blogs_8/b/di/posts/cadence-learning-and-support-installation-licensing-help-also-available-via-chatbot0In recent years, the requirements and performance goals for designers have become more complex and even more demanding. Therefore, the time spent searching for a solution should be minimized as much as possible. The Cadence Learning and Support Portal provides 24/7 technical support to quickly answer your design-related questions and thus solve problems. We are constantly working to improve the user-friendliness and efficiency of our Online Support Portal and are therefore pleased to introduce you to some features that you may not have known before. You can now get help on i nstallation and licensing issues via a Chatbot that is available on various screens. You can also create cases via this Chatbot. Getting Started with Cadence Chatbot Everyone with a Cadence Learning and Support Account can use the Chatbot. You just need to login with your credentials, and you will see the Chatbot symbol in the bottom-left corner of your screen. If you’re a new user of Cadence products, just follow a simple registration process and get started today— all you need is a company email address and a host id or reference key in order to sign up. Click on this icon and then click on “yes” for any further immediate help! Please choose the respective product from the pull-down menu and click "Submit." (The example below uses Innovus ). Next, you can enter your question (see example below) and click on the arrow. The current Innovus User Guide will show up, and you may find the right solution already there. If not, click “No” when the “Was this helpful” question comes. You will get several other solution proposals matching the keywords in your question. If you do not find the right solution here, you have several choices – amongst others, you can open a case directly from Chatbot. Good to Know Our free Online Training Course Library ensures you’ll get the training you need at times that are convenient for you. Online training is delivered over the web - letting you proceed at your own pace - anytime, anywhere. Our Cadence Training Bytes Library is full of hundreds of troubleshooting videos, covering a multitude of topics, and is always open. If you want to make sure you are always the first to know about anything new in training, then you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters. Related Blogs and Videos Come Join Us and Learn from the Cadence Training Offerings Do you want to Flaunt your Expertise? Grab the Digital Badge Today! Cadence Wins Prestigious Support Experience award at SX Live 2023 Getting Started with Cadence Learning and Support System (Video)https://community.cadence.com/cadence_blogs_8/b/di/posts/new-courses-section-in-content-notification-emailFri, 29 Mar 2024 18:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1361950MJ Cad/cadence_blogs_8/b/di/posts/new-courses-section-in-content-notification-email0As you may already know, you can get notified via Cadence Learning and Support website of recently published content and new or updated releases of Cadence Software. Go to My Support > My Account & Preferences > Notification Preferences— here, you can easily select the products you would like to receive regular updates. We are constantly working to improve the user-friendliness and efficiency of our Support Portal and are therefore pleased to introduce you to some features that you may not have known before. Today, we would like to introduce you to the “ New Courses ” section on this page. In the New Courses section in the content notification email, go to My Support > My Account & Preferences > Notification Preferences to set up notifications for new courses: And click on “Notification Preferences”: You might already have chosen your “preferred products,” and you can edit your choice anytime: In Step 2, you can choose your preferred email format: In Step 3, you can now select—amongst others—if you would like to receive updates concerning the courses matching the “preferred products” you have chosen before: Everyone with a Cadence Learning and Support Account can receive regular updates about New Courses and changes within Courses. If you’re a New User of Cadence products, follow a simple registration process and get started today—all you need is a company email address and a host id or reference key to sign up. Never miss a new training or a training update—let´s take this opportunity to introduce you to some new trainings: Genus Synthesis Solution with Stylus Common UI Advanced Synthesis with Genus Stylus Common UI Tempus Signoff Timing Analysis and Closure with Stylus Common UI Good to Know Our free Online Training Course Library ensures you’ll get the training you need at times that are convenient for you. Online Training is delivered over the web - letting you proceed at your own pace - anytime, anywhere. Our Cadence Training Bytes Library is full of hundreds of troubleshooting videos covering a multitude of topics and is always open. Related Blogs and Videos Come Join Us and Learn from the Cadence Training Offerings Do you want to Flaunt your Expertise? Grab the Digital Badge Today! Cadence Wins Prestigious Support Experience Award at SX Live 2023 Getting Started with Cadence Learning and Support System (Video)https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/digital-design-the-year-that-was-new-training-releases-blogs-and-digital-badges-in-2022Mon, 06 Mar 2023 08:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1360256MJ Cad/cadence_blogs_8/b/cadence-support/posts/digital-design-the-year-that-was-new-training-releases-blogs-and-digital-badges-in-20220Another year has gone by, and we have evolved back into the new and old “normals,” partially moving back to the office and Live Trainings using the hybrid working to improve efficiency and sustainability for our customers as best as possible. We thought it would be a good idea to take a look back at our blogs and other exciting news around Digital Design and Signoff in 2022. Most Viewed Blogs The following are the most viewed blogs in 2022: RTL-to-GDSII Flow: I Am Not a Tool But Can Help You Implement Your Entire Design! By P Saisrinivas Floorplanning Frustrations Got You Down? Help Is on the Way! By Vinita Nelson Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI? By Neha Joshi Other News from 2022 We conducted many webinars throughout the year. If you have missed any of these, you can find recordings on the Webinars page . These can also be accessed by searching Cadence Learning and Support Portal with the “webinar” keyword. Most Viewed RAKs Following are the most viewed RAKs in 2022: Tempus ECO RAK by Ayush Srivastava and Marc Heyberger Stylus Flowkit RAK by Benoit Carpentier and Jason Dlugosch Genus/Modus: PMBIST Deep Dive RAK by Patrick, Joyce Kraley, and Ke Zhang New Training Released in 2022 Cadence Cerebrus Intelligent Chip Explorer Training ; also available online . The Cadence® Cerebrus ™ Intelligent Chip Explorer is a revolutionary and machine-learning-driven automated approach to chip design flow optimization. Block engineers specify design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet these power, performance, and area (PPA) goals in a completely automated way. By adopting Cadence Cerebrus, engineers can concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s evermore powerful electronic systems. You can find related training bytes on Cadence Learning and Support Portal and search with “Cerebrus” as a keyword. Here’s a blog with an interesting case study: What's Behind the 5% Die-Area Shrink and 12% Power Saving by MediaTek? Genus Low-Power Synthesis Flow with IEEE 1801 Training ; also available online and with Badge Exam . You can also get further information in this blog . Newly Created Digital Badges Newly Released Training Versions Voltus Power Grid Analysis and Signoff with Stylus Common UI v22.1 (online) Tempus Signoff Timing Analysis and Closure with Stylus Common UI v22.1 (online) Innovus Block Implementation with Stylus Common UI v22.1 (online) The Training Bytes blog series helped promote some of our training bytes, webinars, and scheduled dates for our "Blended" and "Live" trainings. The series also popularized our digital badges . For further information about our trainings, see the Training page and get a complete training overview in our learning map . We hope that our blog series helped you address your tasks faster and with ease. If you have any suggestions or desired topics on which you want us to blog, do let us know! You can also reach out to us at Cadence Training for information on courses, schedules, online trainings, or live on-site trainings.https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/how-to-generate-sdc-constraints-for-dft-constructs-in-genus-synthesis-solutionTue, 05 Jul 2022 21:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1357584MJ Cad/cadence_blogs_8/b/cadence-support/posts/how-to-generate-sdc-constraints-for-dft-constructs-in-genus-synthesis-solution0Is the generation of SDC Constraints for DFT Constructs in Genus Synthesis Solution a topic you are not yet familiar with? If you are inserting Fullscan or any other advanced DFT logic like OPCG, Boundary Scan, PMBIST, Compression, LBIST, and IEEE 1500, worry no more about the DFT-related SDCs extraction. Cadence has you covered with the simple methodology to automatically generate SDC constraints for any DFT construct. The solution that Genus offers requires only three main steps in order to generate DFT SDCs for three base timing modes: the shift mode that holds constraints for timing the DFT shift operation of one or more testmodes, the capture mode that holds constraints for timing the DFT capture operation of one or more testmodes, and of course, the non-DFT mode that is the mode holding the constraints for timing the design when the DFT logic is disabled. All you simply need to do is import the functional SDCs if present, set the relevant root attribute that controls the generation of DFT SDCs to the correct value, and finally, export the generated DFT constraints for the different timing modes by using the relevant command. If all this sounds interesting, use the following material and find out everything you need to know about the DFT SDC methodology in order to master the generation of SDC constraints for any DFT construct you wish to insert into your design. How to Generate SDC Constraints for DFT Constructs in Genus Synthesis Solution?(Video) Refer to Generating SDC Constraints for DFT Constructs chapter of Genus Design for Test Guide For more videos on other topics do refer to the whole video library at the support portal. Note: Enroll in the corresponding training at the Cadence Support for lab instructions and a downloadable design. Genus Synthesis Solution with Stylus Common UI v21.1 (Online) We also offer this class as instructor-led "Blended Training" . Reach out to us at Cadence Training for more information. *if you still don´t have access to the Cadence Support Portal, you can register with your Email address and Cadence Host ID. Grab your course today!! To stay up to date with the latest news and information about Cadence training and webinars, subscribe to Cadence Training emails. You can become Cadence Certified once you complete the course (s) and share your knowledge and certifications on social media channels. Go straight to the course exam at the Learning and Support Portal. Related Resources Training Bytes (Videos) How to Create Domain Interface on Macro Pins in IEEE 1801?(Video) IEEE 1801 Recommendations For Genus Synthesis Solution?(Video) How to View Timing Report Path in Genus Synthesis Solution GUI?(Video) Blogs Do you want to Flaunt your Expertise? Grab the Digital Badge Today! Come Join Us and Learn from the Cadence Training Offerings Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want to Resolve It? Do You Know DFT Violations Can Be Debugged Using Genus GUI? Excited to Explore? What's Inside the GUI-Based Timing Report in Genus? Want to Explore? Low-Power Implementation Training Videos Is your Compression Technique Unified? Wanna Explore? Online Courses Genus Synthesis Solution with Stylus Common UI v21.1 (Online)https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/what-is-ieee-1500-wrapper-insertion-flow-in-genus-synthesis-solutionFri, 25 Mar 2022 10:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1356306MJ Cad/cadence_blogs_8/b/cadence-support/posts/what-is-ieee-1500-wrapper-insertion-flow-in-genus-synthesis-solution0Are you searching for a scalable standard architecture for enabling test reuse and integration for embedded cores and associated circuitry? Are you looking for a standard that addresses testing strategies for the digital aspects of core designs within a System-on-Chip (SoC)? If the answer is yes, Cadence has you covered with our IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution. The IEEE 1500 standard provides a standard interface to create an isolation boundary between a core to be tested and the logic external to the core. The isolation boundary consists of wrapper cells which are inserted for each functional input and output port on the core. Genus-DFT builds the Wrapper Boundary Registers (WBRs) and the logic consisting of the 1500 controller for the serial and parallel interface protocols. Per the 1500 standard, the wrapper serial ports are mandatory while the wrapper parallel ports are optional. Two main different wrapper cell types are supported, and the 1500 wrapper architecture can operate in three types of modes. If all of the above sounds interesting, follow us with the material below to find out the details of the IEEE 1500 standard and how you can easily and effortlessly insert this Core-Wrapper logic into your synthesis flow with Genus Synthesis Solution. For more insight on this topic, refer to the following videos: IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution (Video) What Is IEEE 1500 Wrapper? (Video) And find more videos in our whole video library at the support portal Note: Enroll in the corresponding training at the Cadence Support for lab instructions and a downloadable design . Online Training: Test Synthesis with Genus Stylus Common UI vGenus21.1 We also offer this class as instructor-led "Blended Training." Please reach out to us at Cadence Training for more information. *If you still don´t have access to the Cadence Support Portal you can register with your Email address and Cadence Host ID. Grab your course today! To stay up to date with the latest news and information about Cadence training and webinars, subscribe to Cadence Training emails. You can become Cadence Certified once you complete the course (s) and share your knowledge and certifications on social media channels. Go straight to the course exam in our Learning and Support portal . Related Resources Training Bytes (Videos) How to Insert IEEE 1500 Wrapper Cell in Genus Synthesis Solution? (Video) What Is IEEE Wrapper?(Video) IEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution (Video) Blogs Do you want to Flaunt your Expertise? Grab the Digital Badge Today! Come Join Us and Learn from the Cadence Training Offerings Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want to Resolve It? Do You Know DFT Violations Can Be Debugged Using Genus GUI? Excited to Explore? What's Inside the GUI-Based Timing Report in Genus? Want to Explore? Low-Power Implementation Training Videos Online Courses Genus Synthesis Solution with Stylus Common UI v21.1 (Online) Low-Power Synthesis Flow with Genus Stylus Common UI vN20.1 (Online) Advanced Synthesis with Genus Stylus Common UI v21.1 (Online)https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/webinar-invitation-enhance-your-design-power-with-joulesFri, 11 Feb 2022 08:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1355187MJ Cad/cadence_blogs_8/b/cadence-support/posts/webinar-invitation-enhance-your-design-power-with-joules0Want to take a tour of this powerful power estimation tool and gear up so you understand the Joules flow? What is this Webinar About? Join Cadence Training and Sr Principal Education Application Engineer Neha Joshi for this free technical training Webinar. Built on a multi-threaded frame-based architecture, the Cadence ® Joules ™ RTL Power Solution delivers 20X faster time-based RTL power analysis than other methods. The Joules RTL Power Solution incorporates rapid prototyping technology from the Cadence Genus ™ Synthesis Solution that can analyze designs of up to 20 million instances overnight with an accuracy within 15% of signoff. The Joules RTL Power Solution lets you close the power analysis gap by delivering time-based RTL power analysis with system-level runtimes and capacity—and high-quality gate and wire estimates based on production implementation technology. The Joules Solution integrates seamlessly with the Cadence Palladium ® emulation platform, Genus Synthesis Solution, Innovus ™ Implementation System, and Stratus ™ High-Level Synthesis (HLS) platform. In addition, the Joules RTL Power Solution GUI (Graphical User Interface) helps you analyze/debug the power estimation/results using several GUI capabilities. What will the Webinar Cover? In this webinar, you will learn: How to set up and run RTL power flow with Joules Graphical User Interface (GUI) features of Joules How Genus integrates with Joules and much more When is the Webinar? Date and Time Tuesday, March 8 07:00 PST / 10:00 EST / 15:00 GMT / 16:00 CET / 17:00 IST/ 20:30 IST (India) How to Register To register for the webinar: Click REGISTER . Sign in with your Cadence Support account (email ID and password). Select Enroll . You will receive a confirmation email containing all login details after a successful registration. If you don’t have a Cadence Support account, go to Registration Help or Register Now and fill in the requested information. For questions and inquiries, or issues with registration, reach out to us: Europe, Middle East, and Africa: eur_training@cadence.com USA: Lena Robledo India: Preeti P Gowda China: Cathy Li Japan: Yuji Shimazaki What’s Next? If you find this Webinar useful and want to delve deeper into copper shapes, enroll for the Joules Power Calculator v20.1 (online) training course, which includes lab instructions and a downloadable design. Want to stay up to date on webinars and courses? Subscribe to Cadence Training emails. Hungry for Training? Choose the right Cadence Training Menu for you. To view our complete training offerings, visit the Cadence Training website Looking for Top10 most popular Joules References? What are the different Joules flows? Understanding power computation in Joules Joules: Joules RAK for Beginners (CUI) Joules RTLStim2Gate Flow Ideal Power Analysis: A methodology to Identify, Debug and Fix wasted Power & measure Power Efficiency Joules power_hdl Flow Logic Gating Exploration in Joules Understand Joules Power Reports ODC (Observability Don’t Care)-based Sequential Clock Gating Exploration in Joules. Joules fast mapping: Difference between power_hdl and power_map commands That's all for now! -Mukeshhttps://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/empower-your-power-with-joules-power-calculatorThu, 18 Nov 2021 07:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353993MJ Cad/cadence_blogs_8/b/cadence-support/posts/empower-your-power-with-joules-power-calculator0Are you interested in learning low power concepts? Are you looking for solutions to power challenges? Are you searching for the most efficient way to implement RTL power analysis and optimization for your design? If the answer is yes, Cadence has you covered with our RTL power analysis product, Joules RTL Power Solution . The Cadence Joules RTL Power Solution is an RTL power analysis product that provides a unified engine to compute gate-level power and estimate power for RTL. Joules delivers 20X faster time-based RTL power analysis and can analyze multi-million instance designs overnight, with impressive accuracy within 15% of signoff power. It performs efficiency and wasted toggle power analysis and can identify hotspots and power bugs in a design. Moreover, it integrates seamlessly with numerous other Cadence platforms, so compatibility & correlation issues are eliminated! So, whether you are a design engineer doing RTL power analysis and optimization, or you simply want to expand your knowledge in this area, refer to Joules Product Page to find all related content in one place. Additionally, don’t miss your chance to participate in our Joules Power Calculator v20.1 Training . By completing the course, you will gain invaluable experience in running RTL Power Flow with Joules, estimating and analyzing power with various flows and reports, debugging possible power issues, and much more! On top of that, a Digital Badge is also available for this course to make sure your skills get noticed! Please find a preview in this video: Do You Have Access to the Cadence Support Portal? If not, follow the steps below to create your account. On the Cadence Learning and Support portal, select Register Now and provide the requested information on the Registration page. You will need an email address and host ID to sign up. If you need help with registration, contact support@cadence.com . Please reach out to us at Cadence Training if you would like to have an instructor-led session of the Training . To stay up to date with the latest news and information about Cadence training and webinars, subscribe to Cadence Training emails. Related Resources Rapid Adoption Kits (RAK) Joules RAK for Beginners (CUI) Logic Gating Exploration in Joules Joules power hdl Flow Training Bytes (Videos) How to do Activity Management? What is Stimulus? DB-Based Flow for RTLStim2Gate in Joules Blogs Glitch?? Do Not Let It Impact Your Design Power!! Do you want to Flaunt your Expertise? Grab the Digital Badge Today! Come Join Us and Learn from the Cadence Training Offerings Are You Wondering What Logic Synthesis is and How to Deal with its Complex Process? Relax! Online Courses Joules Power Calculator v20.1 Training Joules Power Calculator v20.1 (Badge Exam)https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/are-you-wondering-what-logic-synthesis-is-and-how-to-deal-with-its-complex-process-relaxTue, 19 Oct 2021 11:10:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1353905MJ Cad/cadence_blogs_8/b/cadence-support/posts/are-you-wondering-what-logic-synthesis-is-and-how-to-deal-with-its-complex-process-relax0Are you a beginner in the synthesis world? Are you looking for the basic concept of logic synthesis and a solution to address the design synthesis? Relax! We can help you sail through it smoothly! Let's first start with the basic concept. Have you ever wondered why you need to do design optimization instead of simply using the gate-level netlist? Because the goal of design optimization is to have the best combination of minimizing the area and power of your design while maximizing the performance. There are various stages of design development, starting with RTL until it reaches the final tape out. Once you have functionally verified RTL, it's time to optimize/synthesize the design so that you pass on the optimized netlist to the place and route team. Take a tour of the below video to explore more details about the logic synthesis concept: What is Logic Synthesis Do you also want to differentiate between good and bad synthesis? It all depends upon what your final requirement is. Are you looking for optimizing area or timing, or power? In today's world, we need everything! Isn't it? And that makes the design synthesis process challenging and complex. Do you want to quickly produce accurate functional models with high predictability in reports regarding the manufactured device's final PPA (Power-Performance-Area) values? If the answer to these questions is yes, it's time to introduce yourself to our tool for synthesis , Genus Synthesis Solution. The ultimate goal of the Cadence ® Genus ™ Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design and the highest quality of results (QoR) in the final implementation. All you need to do is provide the RTL code in HDL (Hardware Description Language), the timing libraries in Liberty format, and the timing constraints of the design as inputs for the Logic Synthesis. And Genus will produce a gate-level netlist in HDL as an output quickly and efficiently, following the different stages of synthesis. The main stages of synthesis with Genus Synthesis Solution are: Generic synthesis Technology mapping Incremental optimization. Are you interested in deep diving into further details of these synthesis stages? Find the answers to your queries with the help of the video: What Happens During Various Stages of Synthesis But this is not the end of the story! Genus Synthesis Solution has faster synthesis turnaround times and scales linearly beyond 10M instances. It further supports advanced features to address power optimization (Joules), Physical Synthesis (iSpatial), Scan Insertion/DFT (Modus), etc. It interfaces well with several tools like Innovus Implementation System, Conformal Equivalence Checker, Conformal Low Power, Tempus Timing Signoff Solution, etc. Excited to explore the advanced features of Genus? Refer to the whole video library at the support portal: http://support.cadence.com/TrainingBytes/Genus Not only this, there are several Genus customer training that focusses on specific topics in-depth learning: Genus Synthesis Solution with Stylus Common UI (cadence.com) Advanced Synthesis with Genus Stylus Common UI (cadence.com) Low-Power Synthesis Flow with Genus Stylus Common UI (cadence.com) Test Synthesis with Genus Stylus Common UI (cadence.com) Grab your course today! Note: Please enroll in the corresponding training at the support portal for lab instructions and a downloadable design. Do You Have Access to the Cadence Support Portal? If not, follow the steps below to create your account. On the Cadence Support portal, select Register Now and provide the requested information on the Registration page. You will need an email address and host ID to sign up. If you need help with registration, contact support@cadence.com . Do you have questions about courses, schedules, online, public, blended, or onsite training? Then reach out to us at Cadence Training . To stay up to date with the latest news and information about Cadence training and webinars, subscribe to Cadence Training emails. Related Resources : Blogs Come Join Us and Learn from the Cadence Training Offerings Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want to Resolve It? Do You Know DFT Violations Can Be Debugged Using Genus GUI? Excited to Explore? What's Inside the GUI-Based Timing Report in Genus? Want to Explore? Low-Power Implementation Training Videos Online Courses Genus Synthesis Solution with Stylus Common UI Advanced Synthesis with Genus Stylus Common UI Product Page https://support.cadence.com/genushttps://community.cadence.com/cadence_blogs_8/b/di/posts/understanding-clock-gating-report-and-cellsFri, 19 Feb 2021 13:37:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1348200MJ Cad/cadence_blogs_8/b/di/posts/understanding-clock-gating-report-and-cells0Hi everyone, Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating? Clock Gating is a technique that enables inactive clocked elements to have gating logic automatically inserted. Even though data is loaded into registers very infrequently in most designs, the clock signal continues to toggle at every clock cycle. Often, the clock signal also drives a large capacitive load, making clock signals a major source of dynamic power dissipation. Gating a group of flip-flops that are enabled by the same control signal reduces unnecessary clock toggles. This helps reduce the power dissipation since power is not dissipated during the idle period when the register is shut off by the gating function. Power is saved in the gated-clock circuitry and the logic on the enable circuitry in the original design is removed. If you indeed seek the best techniques to reduce the power consumption of your design, but all that extra information in the report files seems daunting and hard to interpret, relax! Cadence has you covered with the Training Byte, “Understanding Clock Gating Report and Cells”. This training byte will guide you through the commands and attributes you need to extract the right information from the Clock Gating Report such as: Total number of clock gating instances Different types of integrated clock gating cells (ICGC) How to check whether an instance is a clock gate and what type of ICGC it is Further, it will show you how to do analysis in GUI mode of Genus Synthesis Solution to trace back the fanin cone of the flops clock pin to find about the clock gating instances. Understanding Clock Gating Report and Cells Enhance the Genus Synthesis Solution experience with more videos: Genus Synthesis Solution: Video Library . Note: For lab instructions and a downloadable design, enroll in the corresponding trainings like Genus Synthesis Solution v19.1 (Online) or join our Instructor led session (currently planned as Blended Training ). You could earn Cadence Certification after finishing this course, and promote your expertise on social media channels like LinkedIn and Twitter. The above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning & Support Portal . Don´t have an account right now? On the Learning & Support portal, go to Registration Help, select Register Now and complete the requested information. To sign up, you will need an email address and hostID. If you need help with registration, contact support@cadence.com . Do you have questions about courses, schedules, online, public, blended, or onsite training? Reach out to us at Cadence Training . To stay up to date with the latest news and information about Cadence training and webinars, subscribe to Cadence Training emails. Mukesh Jaiswal On behalf of the Cadence Learning and Support team Related Posts: Do You Know Multibit Cells Could Help You Reduce Clock-Tree Power and Alleviate Wiring Congestion in the Clock Path? Innovus Implementation System: What Is Stylus UI? Exploring Genus-Joules Integration is just a click away!! Are You Struggling to Meet the Timing for Your Design? Stop Worrying! Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution! Use the Industry’s Leading Digital Implementation Flow from inside Virtuoso with a Package Sized and Priced Perfect for Your Next Mixed Signal Project!https://community.cadence.com/cadence_blogs_8/b/di/posts/do-you-know-multibit-cells-could-help-you-reduce-clock-tree-power-and-alleviate-wiring-congestion-in-the-clock-path-154232919Thu, 17 Dec 2020 23:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1346070MJ Cad/cadence_blogs_8/b/di/posts/do-you-know-multibit-cells-could-help-you-reduce-clock-tree-power-and-alleviate-wiring-congestion-in-the-clock-path-1542329190Hi everyone, Searching for yet another method to improve the QoR of your design? What about taking advantage of the improvements in area and power that the Multibit Cell Inferencing (MBCI) flow provides? Merging to multibit cells refers to the merging of the individual register bits from the same or different bus into multibit cell instances. That way, a single clock pin can be used to trigger all register bits in the multibit cell. Hence, the clock-tree synthesis becomes easier, since both the number of clock nets to be routed and the number of register endpoints to be considered when balancing the clock-tree are reduced. As a result, for a similar external clock pin capacitance, the cell clock port drives internally more than one DFF, reducing the number of sinks for the clock tree. This means fewer clock tree elements, which leads to a reduction of the clock-tree power and alleviation of the wiring congestion in the clock path. Read through this article to get answers to your questions like: What is multibit merging? Why is it needed? How to locate multibit libcells? How is a multibit cell defined in the library? How to control the default multibit merging behavior of Genus? If this idea sounds appealing but all that extra information in the report files seems daunting and hard to interpret, relax! Cadence has you covered with the Training Byte about “How to Analyze the Multibit Cell Report in Genus Synthesis Solution”. This Training Byte will guide you through the settings you need to get all the important information from the report, like the number of the merged instances, the percentage of the multibit conversion, and even the reasons why certain single bit cells are not merged into multibit. Furthermore, it will answer questions regarding how the cells get merged, what should be the actual target for MBCI (Multi Bit Cell Inference), and how this will affect the place and route later. So, follow us with the material below and make the most out of the Multibit Cell Report in Genus Synthesis Solution in the most convenient way! Enhance the Genus Synthesis Solution experience with more videos: Genus Synthesis Solution: Video Library . Note: For lab instructions and a downloadable design please enroll in the corresponding trainings like Genus Synthesis Solution v19.1 (Online) . The above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning & Support Portal . Don´t have an account right now? On the Learning and Support portal go to Registration Help, select Register Now and complete the requested information. You will need an email address and hostID in order to sign up. If you need help with registration, contact support@cadence.com . All classes can also be delivered as Instructor-led Training and – important for the current situation - also as Blended Training . Do you have questions about courses, schedules, online, public, blended or onsite training? Then reach out to us at Cadence Training . Become Cadence Certified Cadence Training Services now offers digital badges for this training course. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding these digital badges to your email signature or any social media platform, such as Facebook or LinkedIn. Get Cadence Certified . Please find further information here . To stay up to date with the latest news and information about Cadence training and webinars subscribe to Cadence Training emails. Mukesh Jaiswal Sr. Knowledge Manager (Digital and Signoff) On behalf of the Cadence Learning and Support team Related Posts: Innovus Implementation System: What Is Stylus UI? Exploring Genus-Joules Integration is just a click away!! Are You Struggling to Meet the Timing for Your Design? Stop Worrying! Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution! Use the Industry’s Leading Digital Implementation Flow from inside Virtuoso with a Package Sized and Priced Perfect for Your Next Mixed Signal Project!https://community.cadence.com/cadence_blogs_8/b/di/posts/use-the-industry-s-leading-digital-implementation-flow-from-inside-virtuoso-with-a-package-sized-and-priced-perfect-for-your-next-mixed-signal-projectMon, 31 Aug 2020 15:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1344811MJ Cad/cadence_blogs_8/b/di/posts/use-the-industry-s-leading-digital-implementation-flow-from-inside-virtuoso-with-a-package-sized-and-priced-perfect-for-your-next-mixed-signal-project0Hi Everyone, Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too high? If the answer is yes, do not worry; Cadence has you covered with the Virtuoso Digital Implementation package! Virtuoso Digital Implementation is basically a package based on our Innovus digital implementation platform, which allows you to design digital circuits from RTL to final GDSII output. With Virtuoso Digital Implementation you get access to both Genus Synthesis Solution and Innovus Implementation System, with a single instance-limited license that can be run directly from the Virtuoso cockpit. This approach makes it easier for mixed-signal designers to come up to speed with using the full-function digital tools and design concepts in a familiar guided environment. An instance-limited version of the Cadence digital implementation flow means that you can utilize the Virtuoso Digital Implementation license for blocks or designs with a cap on the number placeable components that work for the majority of mixed-signal users. Does your design exceed that limit ? You can stack two Virtuoso Digital Implementation licenses together to double the number of instances. Going even bigger than that ? The instance limit can be tripled using the VDI-XL Block option! Beyond that size, you’ll want to move to the full-sized digital tool variants and take advantage of their superior capacity and multi-threading capabilities. So regardless if you are in the context of a small digital block in mixed-signal design, or in the context of running a small digital block that will be integrated into a larger design, Virtuoso Digital Implementation licenses can provide a useful alternative to full-blown Genus and Innovus licenses. Virtuoso Digital Implementation is extremely favorable for design teams that work on mixed-signal projects with big analog and small digital parts, for instance, small microcontrollers of analog sensors or SPIs for state-of-the-art PLLs. Last but not least, with the Virtuoso Digital Test and Virtuoso Digital Signoff licenses you can expand the Virtuoso Digital Implementation concept to DFT and Signoff tools, in other words, you can use Modus, Tempus and Voltus at reduced prices with the same instance threshold. Want to learn more? In this series of videos, you will learn the basics of synthesis and digital implementation using the Virtuoso Digital Implementation software. You will explore floorplanning, placement, power planning, clock-tree synthesis, timing optimization, and detail routing. As always, you'll need an active support.cadence.com account to view the videos. Please find additional corresponding instructional Training videos and instructions on the Cadence Learning and Support System . Note: For lab instructions and a downloadable design please enroll in the corresponding course on learning.cadence.com. To stay up to date with the latest news and information about Cadence training and webinars subscribe to Cadence Training emails. Do you have questions about courses, schedules, online, public or live onsite training? Then reach out to us at Cadence Training . Related Rapid Adoption Kit Virtuoso Digital Implementation (VDI) Discovery Kit 17.12 - Stylus Based RAK Related Posts: Are You Struggling to Meet the Timing for Your Design? Stop Worrying! Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution! Innovus Implementation System: What Is Stylus UI? Exploring Genus-Joules Integration is just a click away!! Take a Cadence Masterclass and Get a Badgehttps://community.cadence.com/cadence_blogs_8/b/di/posts/are-you-struggling-to-meet-the-timing-for-your-design-stop-worryingWed, 26 Feb 2020 17:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1342314MJ Cad/cadence_blogs_8/b/di/posts/are-you-struggling-to-meet-the-timing-for-your-design-stop-worrying0We know your designs are complex and so is timing analysis. We cannot change the design but we have made the timing analysis process easier for you. Timing closure is one of the most critical components of a digital design. To be able to meet timing at the later stages of design signoff, it is imperative to consider timing analysis within the synthesis stage itself. We at Cadence have taken this into account and developed integrated engines to enable timing analysis in the early stages of synthesis. Here is the step-by-step process for timing analysis, debugging, and optimization during the design creation synthesis stage using the Genus Synthesis Solution. Stages of Timing Analysis Checklist to Perform Timing Analysis Timing constraints: Improper constraints can lead to a bad starting point during global mapping and a bad result in the end. So, start with proper timing constraints. Pre-synthesis diagnosis: Generate pre-synthesis timing reports first for analysis by checking the timing intent. Logic levels: Identify the logic levels of different paths in the design. Abnormally large cell/transition delay: Large delays in a cell can indicate the problem with the wire-load model, operating conditions, or technology library. Check the log file when the library and constraints are read. Input-to-output path: Check for the input and output timing delays. And this is not the end of the timing story, for you may have many other questions such as: What happens at each checklist stage? How does the tool analyze the report? Can I do further debug using a graphical user interface (GUI)? What about commands to be used? How do I optimize MMMC and non-MMMC designs? To explore more about these common questions that might arise while doing timing analysis, refer to the latest RAK on https://support.cadence.com [Cadence login required]. RAK Title: Genus Quick Start Guide : Timing Analysis Direct Link: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009bdlKEAQ&pageName=ArticleContent Related Resources: Enhance the Genus Synthesis experience with videos: Genus Synthesis Solution: Video Libraryhttps://community.cadence.com/cadence_blogs_8/b/di/posts/cosliteWed, 28 Aug 2019 09:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1341952MJ Cad/cadence_blogs_8/b/di/posts/coslite0As designs become complex and performance targets increase, time shrinks. Designers need to minimize time setting up design flows or trying to find workaround for many issues that might occur during tape out. The Cadence Online Support portal ensures 24x7 technical assistance to quickly address your technical issues and queries. In our continuous effort to improve the usability of the Online Support portal and efficiency of its usage, we are introducing access to the relevant content from the tool interface (starting with 19.11 releases of Innovus, Tempus, and Voltus). This feature can now be easily accessed by running the tool in the GUI mode through the Help pull-down menu. Follow these steps to access the online content from the tool interface: 1. Invoke Digital IC tool (Innovus, Voltus or Tempus) in the GUI mode starting 19.11 release. 2. From the GUI, select Help > Documentation Library as shown below: The Cadence Help form opens as shown below: 3. Type the search keyword in the Global Resources search field. The search will be performed only for the tool invoked. 4. A new tab, Online Resources , is created to display search results. Search results are displayed under different categories: Application Notes, Product Manuals, Rapid Adoption Kits, Troubleshooting Info, Videos, and Whats new. By default, four most relevant documents are displayed under each category. You can use the button to navigate to the previous / next page. For more details and FAQs, click here . We hope you will enjoy using the curated search results to troubleshoot your issues quickly and seamlessly. -Mukesh Jaiswal Sr. Knowledge Manager (Digital and Sign-off Solutions)https://community.cadence.com/cadence_blogs_8/b/di/posts/what-s-in-it-for-me-in-innovus-18-10-releaseTue, 16 Oct 2018 20:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1341286MJ Cad/cadence_blogs_8/b/di/posts/what-s-in-it-for-me-in-innovus-18-10-release0At advanced nodes, there’s always a deep conflict between power, performance, and area (PPA) and design turnaround time (TAT). You already know Innovus Implementation System very smartly delivers PPA advantage and accelerates digital design TAT through various features, including its full-flow massively parallel architecture. Innovus 18.10 release takes all these benefits even further. In this blog, I will start with sharing some key highlights of 18.1 release and eventually share pointers of several technical content to learn and leverage the new release capabilities. Some of the key highlights are listed below: This easily translates to some key benefits for our customers: TAT: Native speedup for Optimization engines Up to 3x speedup for core CTS More multi-thread parallelization PPA: SOCV aware placement in addition to optimization Global Sizing for efficient timing closure Full flow improved data and clock power, including timing and power-driven routing Usability: Enhanced clock H-Tree capabilities New Graphical metrics reporting 3D layout GUI, Stylus Common UI Production, Design data sanity checking Advanced node features and support: Digital and Sign-off 18.1 release page captures variety of content available for several products viz. Genus, Modus, Conformal, Innovus, Tempus, Voltus etc. that you could leverage to complete your full digital design flow. This not only has various update trainings explaining new features, but also posses multiple key learning content like RAKs, Videos, etc., pertaining to 18.1 release. Click here to access 18.1 release Page. If click to the link does not work, use direct URL: https://support.cadence.com/dsg181 on your browser window to access release page. Contact Us You can use 'like' and 'feedback' button on this page to share your experiences or send questions, feedbacks directly to ask_km@cadence.com . To receive related information, directly in your mailbox, type your email ID in the Subscriptions field at the top of the page and click SUBSCRIBE NOW. ~ Mukesh Jaiswalhttps://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/product-page-all-product-related-information-and-knowledge-content-at-one-placeSat, 30 Sep 2017 17:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1340453MJ Cad/cadence_blogs_8/b/cadence-support/posts/product-page-all-product-related-information-and-knowledge-content-at-one-place0In the past, some of you have expressed the desire to have all the information and content specific to a product at one place. You said it, we did it! Now, all you need is choose a product of your choice after logging in at https://support.cadence.com . With this feature, you can now visit a specific product page to learn everything you need to know about installation, licensing, new features, product manuals, and other knowledge artifacts. Use this “one stop shop" page to get all you need to install and use a product or tool. The following example shows the product selection for ‘Conformal Equivalence Checker’: Once the product of choice is selected, below is the screen that would get displayed: Features and Benefits: Most Popular – Provides access to content that has been helpful to a large customer community New Troubleshooting Info – Displays the latest set of published articles for the product of your choice Forums and Blogs – Gives insight into hot topics being discussed in forums Choose a release – Provides flexibility to select a release of your choice (the entire page gets rebuilt) Related Links – Helps collate all the knowledge artifacts associated with the selected product Related Products – Provides flexibility to switch to other product pages By default, you will find a product page for all products. For some products, you may find a more advanced page as well. For example, the following product page for Tempus displays a more advanced page with added classifications to information and content specific to it. You will notice a perfect blend of information pertaining to a product for new as well as more advanced users. Watch this space https://community.cadence.com/cadence_blogs_8/b/cadence-support for more help to use Cadence Support site effectively and productively. Don’t hesitate to contact ask_km@cadence.com for questions, suggestions, or feedback. ~ Mukesh Jaiswalhttps://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/what-to-expect-from-each-collateral-on-cadence-support-portal-and-how-to-access-themTue, 25 Jul 2017 16:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1340328MJ Cad/cadence_blogs_8/b/cadence-support/posts/what-to-expect-from-each-collateral-on-cadence-support-portal-and-how-to-access-them0Undoubtedly, the most important component of any online portal is CONTENT and its Ease of Accessibility . In the digital world, content is a mix of text, graphic, video, and so on. This blog covers different types of collateral available on Cadence Support Portal and how to differentiate and easily access them via ‘Search’ and ‘Navigation’ attempts. The Support portal categorizes these different types of collateral as ‘Document Types’. Basis of these document types are content format, their technical coverage, delivery channel, and so on. Accessing Various Document Types through ‘Search’ You will be able to see all the available document types when you do a keyword search on Cadence Support Portal (See the following snapshot): Accessing Various Document Types through ‘Navigation’ You can find the popular ‘Document Types’ available as ‘icons’ for quick access on the home page. This is basically a page that you get when you log in on https://support.cadence.com . You can navigate to different ‘Document Types’ through the ‘Resources’ menu as shown below: Some of the ‘Document Types’ can be accessed through the ‘Self Learning’ menu as shown below: Document Types Definitions 1. Application Notes An application Note provides more specific details on using a specific application or flow. These documents offer expert analysis, design ideas, reference designs, and tutorials. They have greater details like purpose, introduction, implementation, example scripts, results, recommendation and summary/conclusion and hence, have a broader scope. To navigate, go to https://support.cadence.com > Resources > Application Notes . 2. Error Messages This type of content suggests extended help about an error message with the possible causes and solutions, along with examples to resolve it. To navigate, go to https://support.cadence.com > Resources > Error Messages 3. Product Manuals All product documentation, user guides and reference guides written in standard style by the technical publication team are classified as Product Manuals. To navigate, go to https://support.cadence.com > Resources > Product Manuals . 4. Rapid Adoption Kits (RAK) This is a self-packaged content, which contains a design testcase database along with Lab instruction document and/or Overview presentation. Primary goal of this document type is to provide a hands-on experience with the software on a specific design flow or feature. To navigate, go to https://support.cadence.com > Resources > Rapid Adoption Kits . you can also access it via htps://support.cadence.com > Self Learning > Rapid Adoption Kits . 5. Scripts This document type is meant to categorize a script or AE-Ware like Tcl/Dbget/SKILL Procedures PLI/VPI Programs, or UNIX/Perl Scripts to help you achieve a specific task. To navigate, go to https://support.cadence.com > Resources > Scripts . 6. Troubleshooting Information The troubleshooting information is content that describes or isolates symptoms of undesired or unexpected behavior, failure or a crash from Cadence products. These are mostly short articles that list causes and possible solution to help you take corrective action to prevent further similar failures. To navigate, go to https://support.cadence.com > Resources > Troubleshooting Information . 7. Video Library Videos are a unique content format or medium to demonstrate a new tool feature, a process of a design flow, steps in a Graphical User Interface (GUI) tool, sequence of images, and so on, which otherwise is difficult to explain through the text. To navigate, go to https://support.cadence.com > Resources > Video Library . You can also access it via https://support.cadence.com > Self Learning > Training Bytes (Videos) . 8. Installation and Licensing These documents are meant to help fix issues pertaining to the tool installation, licenses, and machine configurations. To navigate, go to https://support.cadence.com > Resources > Installation, Licensing and Configuration . 9. What’s New These documents explain new tool capabilities and introductory features. They are normally a part of most Cadence product releases, Update Trainings, and Technical Roll Outs (TROs). To navigate, go to https://support.cadence.com > Self Learning > What’s New . Keep watching this space for more to help you use Cadence Support site effectiely, and be more productive. Don’t hesitate to contact ask_km@cadence.com for questions, suggestions, or feedback you may have. ~ Mukesh Jaiswalhttps://community.cadence.com/cadence_blogs_8/b/di/posts/new-content-for-digital-users-on-http-support-cadence-comMon, 14 Apr 2014 16:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1333087MJ Cad/cadence_blogs_8/b/di/posts/new-content-for-digital-users-on-http-support-cadence-com0Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through https://support.cadence.com/ Rapid Adoption Kits: Static Timing Analysis using Tempus (Signoff Timing Analysis) 13.2 With the help of this RAK (rapid adoption kit) you will learn how to perform static timing analysis on a dual-tone multi-frequency (DTMF) design using Cadence Tempus Timing Signoff Solution in each of the four modes shown below: Tempus STA Single Mode Single Corner SMSC Tempus STA Distributed Multi-Mode Multi-Corner DMMMC Tempus STA Concurrent Multi-Mode Multi-Corner CMMMC Tempus DSTA Distributed STA on multiple clients Tempus DSTA You will be able to: • Understand how to set up and run each of the Tempus Timing Signoff Solution methods • Report and analyze static timing results • Be confident on how to start your new design and choose the methods that are best for you Timing Signoff Optimization (TSO) using TEMPUS 13.2 & EDI System 13.2 In this RAK, you will learn how to perform ECOs (engineering change orders) for solving hold, setup, and DRV timing violations on a dual-tone multi-frequency (DTMF) design using Tempus Timing Signoff Solution and Cadence Encounter Digital Implementation System. First section of this will cover Tempus TSO fixing on a block-level design and the subsequent will cover hierarchical chip finishing using Tempus TSO. This will help to: • Explain how to investigate timing in an signoff STA environment • Understand and explain the timing ECO methodology • Understand and perform all the steps required before starting the ECO process • Perform hold, setup, and DRV timing fixes through ECOs • Report and analyze ECO results • Implement the ECOs in Encounter Digital Implementation System • Verify final signoff STA • Assemble a hierarchical design in Tempus Timing Signoff Solution for STA and ECO fixing • Perform hierarchically aware chip finishing with timing ECOs • Optimize timing in replicated modules (master/clone) Videos : Demo on Implementing Hierarchical Design Using EDI System This knowledge resource is meant for beginners, new users of EDI System, or users new to the digital implementation design flow. This will help users to learn steps needed in specifying the partitions, creating power and ground rings, running placement and trial/route, assigning partition pins, deriving timing budgets, committing the partitions, pushing into the partitions, and, finally, saving the partitions. How to create and use ILM (Interface Logic Model) in EDI system This video showcases steps required in creating the ILMs of a partitioned block, implementation of created ILMs at the top level, and checking of interface logic at the top level of the specified ILM and viewing path, penetrating into the block up to interface logic of the path. Hope you find these knowledge resources useful. Happy Learning! Mukesh Jaiswalhttps://community.cadence.com/cadence_blogs_8/b/di/posts/more-than-10-things-i-learned-by-browsing-cadence-online-support-http-support-cadence-comThu, 14 Nov 2013 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1328753MJ Cad/cadence_blogs_8/b/di/posts/more-than-10-things-i-learned-by-browsing-cadence-online-support-http-support-cadence-com1I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These are packages that include a detailed instructional document and a lab database. You can browse all the available materials at https://support.cadence.com/ . Rapid Adoption Kits (RAKs) - The purpose of RAKs is to demonstrate how users can use Cadence tools in their design flows to improve productivity and to maximize the benefits of their tools. Here are a few important RAKs and appnotes that were published recently on the support portal ( https://support.cadence.com/ ) which might be of interest to many of us! 1. RAK - Prototyping Foundation Flat Flow EDI 13.2 This content helps us learn gigascale prototyping with FlexModels and presents a prototyping usage model. FlexModels enable gigascale design exploration using the Encounter Digital Implementation (EDI) System. 2. RAK - Introduction to EDI System 13.2 & Block Implementation Flow This RAK can be extremely helpful for beginners who intend to learn the EDI System. RAK includes EDI command and graphical user interface (GUI), how to set up the EDI system, and how to implement the flat flow that can be used for chip or block Implementation 3. RAK - Basic Floorplanning in EDI System 13.2 This knowledge piece helps us learn how to specify the floorplan, move and edit placement constraints, create placement and routing blockages, create power and ground rings and stripes, and power routing 4. RAK - Power and Rail Analysis Using Encounter Power System (EPS) 13.1 This material provides information on to know how to do library characterization, analyze VCD files for windows of high signal activity, do static and dynamic power analysis, analyze current/power plots, perform what-if analysis & analyze various rail analysis plots 5. Appnote - Time Budgeting for Very Large, Timing Critical Hierarchical Design Using ART Methodology Time budgeting for very large timing-critical designs using virtual optimization is not accurate enough. With design sizes growing to over 300 million instances, obtaining accurate time budgets with better accuracy for timing critical design is becoming a necessity for many design teams. This document crisply describes how to obtain accurate time budgets using Active-Logic Reduction Technology (ART) to reduce run-time and memory footprint on timing critical designs. This should help the user achieve accurate timing budgets. 6. Appnote - Constraint Implementation and Validation in Interoperability Flow The key benefit designers derive by using a mixed signal Interoperability flow and OpenAccess (OA) database is the seamless transfer and implementation of various routing constraints from analog to digital designs. Starting from Encounter Digital Implementation (EDI) 13.2 and Virtuoso 616, it is not only simple to create these constraints, but it is also easy to import or export them from one environment to another. Once the design is implemented using these constraints, you can use the Physical Verification System-Constraint Validation (PVS-CV) utility to validate whether these constraints are implemented correctly. 7. Appnote - Context Aware Placement in EDI System This document is targeted to users who want to apply context constraint for cells with Encounter Digital Implementation System (EDI System). It will introduce how to define edge types and the requested spacing rules, how to assign the specified edge types to cells, and how to spread cells with specific edge types to satisfy the spacing rules. It includes recommendations for a successful chip implementation. 8. Appnote - How to Detect and Fix Isolated Cut Via Violations This content is meant for users and designers needing to locate and fix isolated cut violations in their designs, and CAD engineers wishing to implement such a flow using the Encounter Digital Implementation (EDI) system. This document provides some background to the problem, and a methodology for resolving violations by inserting multi-cut vias. 9. Appnote - Current Mode Virtual Attacker Modeling small attackers accurately and efficiently is an important factor in the accuracy of noise and noise-on-delay analysis. This application note explains how the current mode virtual attacker is formed and used. 10. Appnote - End Cap Cells Usage in Encounter Digital Implementation (EDI) System Flow If you want to insert end caps into the design with Encounter Digital Implementation System, this content should help you achieve your goal. It will introduce you to various end cap insertion and verification methodologies recommendations from Cadence for a successful chip implementation. 11. Appnote - Path Exception Priority Rules This document describes the path exception priority rules which are followed by Encounter Timing System (ETS) / Encounter Digital Implementation (EDI) System for finding effective path exception for a path, among the multiple path exceptions specified for that path. Path exception priority rules are explained (in descending order) as per path exception command type and various command options. Happy Learning !! Mukesh Jaiswalhttps://community.cadence.com/cadence_blogs_8/b/di/posts/quick-reference-top-things-to-know-on-power-optimization-using-edi-systemTue, 12 Feb 2013 13:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1319713MJ Cad/cadence_blogs_8/b/di/posts/quick-reference-top-things-to-know-on-power-optimization-using-edi-system3Everyone knows that the increasing speed and complexity of today's designs implies a significant increase in power consumption, which demands better optimization of your design for power. I am sure lot of us must be scratching our heads over how to achieve this, knowing that manual power optimization would be hopelessly slow and all too likely to contain errors. Here are 8 Top Things you need to know to optimize your design for power using the Encounter Digital Implementation (EDI) System. Given the importance of power usage of ICs at lower and lower technology nodes, it is necessary to optimize power at various stages in the flow. This blog post will focus on methods that can be used to reach an optimal solution using the EDI System in an automated and clearly defined fashion. It will give clear and concise details on what features are available within optimization, and how to use them to best reach the power goals of the design. Please read through all of the information below before making a decision on the right approach or strategy to take. It is highly dependent on the priority of low power and what timing, runtime, area and signoff criteria were decided upon in your design. With the aid of some or all of the techniques described in this blog it is possible to, depending on the design, vastly reduce both the leakage and dynamic power consumed by the design. Quick Reference - Top Things to Know about Power Optimization All of the following items discussed here in brief are covered in greater detail in Low Power Optimization in EDI System appnote posted on https://support.cadence.com/ This is a one stop quick reference and not a substitute for reading the full document. 1) VT partition uses various heuristics to gather the cells into a particular partition. Depending on how the cells get placed in a particular bucket, the design leakage can vary a lot. The first thing is to ensure that the leakage power view is correctly specified using the " set_power_analysis_mode -view " command. The " reportVtInstCount -leakage " command is a useful check to see how the cells and libraries are partitioned. Always ensure correct partitioning of cells. 2) In several designs, manually controlling certain leakage libraries in the flow might give much better results than the automated partitioning of cells. If the VT partitioning is not satisfactory, or the optimization flow is found to use more LVT cells than targeted, selectively turn off cells of certain libraries particularly in initial part of the flow i.e. preRoute flow. The user should selectively set the LVT libraries to "don't use" and run preCts/postCts optimization. Depending on final timing QOR, another incremental optimization with LVT cells enabled may be needed. 3) Depending on the importance of leakage/dynamic power in the flow, the leakage/dynamic power flow effort can be set to high or low. setOptMode -leakagePowerEffort {low|high} setOptMode -dynamicPowerEffort {low|high} If timing is the first concern, but having somewhat better leakage/dynamic power is desired, then select low. If leakage/dynamic power is of utmost importance, use high. 4) PostRoute Optimization typically works with all LVT cells enabled. In case of large discrepancy between preRoute and postRoute timings or if SI timing is much worse than base timing, postRoute optimization may overuse LVT cells. So it may be worthwhile experimenting with a two pass optimization, once with LVT cells disabled, and then with LVT cells enabled. 5) In order to do quick PostRoute timing optimization to clean up final violations without doing physical updates, use the following: setOptMode -allowOnlyCellSwapping true optDesign -postRoute This will only do cell swapping to improve timing, without doing physical updates. This is specifically for timing optimization and will worsen leakage. 6) Leakage flows typically have a larger area footprint than non-leakage flows. This is because EDI trades area with power, as it uses more HVT cells to fix timing to reduce leakage. This sometimes necessitates reclaiming any extra area during postRoute Opt to get better convergence in timing. EDI has an option to turn on area reclaim postRoute which is hold aware also and will not degrade hold timing. setOptMode -postRouteAreaReclaim holdAndSetupAware 7) Running standalone Leakage Optimization to do extra leakage reclamation: optLeakagePower This may be needed if some of the settings have changed or if leakage flows are not being used. 8) PreRoute Optimization works with an extra DRC Margin of 0.2 in the flow. On some designs it is known to result in extra optimization causing more runtime and worse leakage. The option below is used to reset this extra margin in DRV fixing: setOptMode -drcMargin -0.2 Remember to reset this margin for postRoute optimization to 0, as postRoute doesn't work with this extra margin of 0.2. Note that the extra drcMargin is sometimes useful in reducing the SI effects, so by removing the extra margin, more effort may be needed to fix SI later in the flow. I hope these tips help you achieve your power goals of your designs! -Mukesh Jaiswalhttps://community.cadence.com/cadence_blogs_8/b/di/posts/spice-correlation-made-easy-by-etsMon, 10 Dec 2012 14:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1317460MJ Cad/cadence_blogs_8/b/di/posts/spice-correlation-made-easy-by-ets2Hello, and welcome to my first blog! As an application engineer in customer support, I have received quite a few queries on how to do SPICE correlation of timing numbers. This blog is intended to help users understand the flow/methodology for doing SPICE correlation of static timing analysis (STA) timing results using Encounter Timing System (ETS). As we know, users do correlation of the critical paths in timing analysis with path simulation, using SPICE to gain the signoff confidence of their design. ETS offers built-in critical path simulation for base delay and signal integrity (SI) correlation with SPICE. This blog describes the flow/methodology available in ETS at a higher level to perform path simulations with SPICE and correlate them with base delay timing. SPICE Deck Generation The ‘create_spice_deck’ command is available in ETS to generate the SPICE trace for a path. The SPICE deck generated by ‘create_spice_deck’ includes: - All nets in the path and their instance connections - Standard cell gate information for the instances and their port connections - initial conditions and voltage sources - Measure statements for slew and delay measurements - RC parasitic network information Various options of create_spice_deck command can be used to specify the path(s) of interest and other information required for SPICE deck. For details on supported options to this command, visit ETS documentation Examples for SPICE deck generation command 1) The following command without any options will generate a SPICE for worst path as seen by timing analysis create_spice_deck 2) The following command creates a SPICE deck for specified path with predriver waveform as input PWL and side path loading of 1 stage, and includes the path of specified SPICE subcircuit and model file in SPICE deck. create_spice_deck -report_timing {-retime path_slew_propagation -net -from_rise inst_flop1/q -though inst_buf/a -though inst_buf/y -to inst_flop2/d} -input_waveform predriver -subckt_file SPICE_subckt.sp -model_file models.sp -power {vdd vddw} -ground {vss vssw} -side_path_level 1 -outdir ETS_SPICE 3) The following command creates a SPICE deck and simulates it using the Spectre TM simulator specified. create_spice_deck -run_path_simulation -Spectre /tools/Spectre Running Path Simulation and Results Extraction Path simulation can be done in two ways: 1) Spectre™ path simulator available in ETS installation ( create_spice_deck -run_path_simulation ) can be used to run path simulation 2) SPICE deck can be generated in user-specified directory, and stand-alone (outside of ETS environment) path simulation can be run using Spectre™ or any simulator that understands SPICE syntax. Spectre™ path simulator in ETS create_spice_deck -run_path_simulation option can be used to do on the fly path simulation in ETS. Note: For running simulation using -run_path_simulation, it is highly recommended to specify SPICE subckt and model file using -subckt_file and -model_file options respectively. If they are not specified, design must have cdB files loaded and software will get this in-formation from cdB file. However, it is mandatory to specify subckt and model files if AAE is being used. Besides writing a few files in the directory (specified using - outdir option) it also reports a table of timing (as shown in below example) with slew/delay/arrival column from report_timing and path simulation for correlation comparison. It will report two separate tables for launch and capture paths if report_timing –path_type full_clock is used. Stand-alone Path Simulation If create_spice_deck command is run without –run_path_simulation option, it will save the SPICE deck of the path (path_1_setup.sp) specified path in the specified directory (specified using –outdir option). By default, it will save the SPICE deck in ets_pathsim directory. The user can run standalone path simulation using Spectre™ or any other simulator which understands SPICE syntax on the SPICE deck (path_1_setup.sp) saved by ETS. Upon successful completion of path simulation, path_1_setup.measure file will be generated which can be used to extract results. Below is an example snippet of path_1_setup.measure file, which shows slew and delay measurement of two stages. Slew/delay statements in spice deck have ‘slew’ and ‘delay’ words to identify the slew and delay numbers for the respective stages in timing path. This file can be easily post-processed to extract simulation results. For example, the sum of all ‘delay’ stages will give path delay of the total path. So, using any of two methods explained above you can easily correlate your design results using this ETS feature. There is an excellent appnote written on this topic which not only explains the correlation flow and methodology in detail, but at same time showcases an example SPICE deck with reasonable descriptions of various important constructs. It also cleanly covers various debugging techniques that can be used to resolve the correlation issues encountered, if any. Click to visit the appnote Base delay SPICE correlation In ETS Cadence Online Support website https://support.cadence.com/ is your 24/7 partner for getting help and resolving issues related to Cadence software. If you are signed up for e-mail notifications, you've likely to notice new solutions, Application Notes (Technical Papers), Videos, Manuals, etc. Hope you find this information useful. Thanks -Mukesh