Karolina Summers Blog

Re: Nanoroute stops at Placement blockage

Kari — Wed, 24 Apr 2013 15:08:54 GMT

Well, at least now we know the net CAN be connected, so that's good. Try using nanoroute for selected nets only, and just select ONE of these nets. Maybe the messasges will give more info about why it can't route.

Re: Nanoroute stops at Placement blockage

Kari — Tue, 23 Apr 2013 14:06:51 GMT

also, check out this blog entry for wire editing:

http://www.cadence.com/Community/blogs/di/archive/2010/01/21/encounter-screencast-editing-wires-more-quickly-with-bindkeys.aspx

Re: Nanoroute stops at Placement blockage

Kari — Tue, 23 Apr 2013 14:01:13 GMT

It sounds like your IO LEFs don't have physical pins defined. If you zoom in to the I/O cell, do you see pin shapes? You already said you checked the LEF...

To try routing a net by hand, see the "Editing Wires" chapter in the User Guide.

Are those nets considered "SPECIAL" nets? (If you output a DEF, do you find these nets in the NETS section, or the SPECIALNETS section?)

Try these things and see what happens next - hard to debug from a distance, but hopefully we can get to the bottom of it.

Re: Nanoroute stops at Placement blockage

Kari — Mon, 22 Apr 2013 13:56:49 GMT

The placement blockage won't block routing. Something else is going on here. Can you turn on the routing grids to make sure they cover the area between the core and I/O? (they're called Pref Track, you can check layer by layer). If those look good, can you complete one of these routes by hand? Trying that may show error markers or something that leads you to the cause. Are the nets in question marked SPECIAL, or do they have a skip_routing attribute on them?

Re: Specify the metal Layers in SOC encounter

Kari — Wed, 03 Apr 2013 14:28:51 GMT

Try streaming out with units 1000 - then see if the measurements in EDI and Virtuoso match.

Re: how max_sink_trans value is going to affect the timing of my design

Kari — Fri, 29 Mar 2013 16:07:32 GMT

i believe the default_max_transition will cover any pin that doesn't have a tighter constraint.

for your second question, i'm not a timing expert, but you can look in the .lib tables and see how a transition in the range of what you specify to CTS would affect the delay vs. the max transistion. i'm not sure if i understand your question though.

Re: How to assign VIA to a net name?

Kari — Thu, 28 Mar 2013 23:28:45 GMT

No problem! It's kind of funny how the question can apply to both tools. :-) Sorry I didn't catch it sooner....

Re: How to assign VIA to a net name?

Kari — Thu, 28 Mar 2013 21:49:03 GMT

I had trouble splitting the whole thread out - please check the PCB Design forum and make sure your question looks ok there. If not, please re-post there. Thanks!

Re: How to assign VIA to a net name?

Kari — Thu, 28 Mar 2013 21:45:35 GMT

EDI is not for PCB layout. It's for IC floorplanning/place&route/timing-closure/etc... I'll move your question to the PCB forum.

Re: How to assign VIA to a net name?

Kari — Thu, 28 Mar 2013 21:10:17 GMT

Well, that solves the problem. You are using a tool other than EDI (Encounter Digital Implementation) System. I don't know what tool that is. We may need to send your question to a different forum. :-)