Naveen Konchada Blog

Customer Support Recommended - Instance and Occurrence Modes of Design Annotation using OrCAD Capture

Naveen — Thu, 02 May 2013 13:51:00 GMT

Assigning reference designators for the schematic instances is a very vital part of the entire PCB flow. This can sometimes become very cumbersome, and in some cases users allocate a major portion of their time and effort to get the assignments correct and optimized.

Annotation is the automated process of assigning reference designators in Allegro Design Entry CIS, also known as OrCAD Capture. The following AppNote clarifies the fundamentals of the Instance and occurrence modes of annotation in a Capture based design. It explains various aspects of annotation and simplifies the concept behind Instance and Occurrence modes.

What are Instance and Occurrence Modes?

These two modes essentially determine how a design is annotated. The Annotate dialog, as shown in Fig.2, provides the option to annotate a design in Instance or Occurrence modes. The recommended mode of annotation is determined based on the conditions specified in the following table:

Table.1 - Recommended annotation modes

Fig.2 - Annotate Dialog Box

Property Editor

The property editor for any part in a Capture design has a white column and one or more yellow columns. The white column is the instance column and yellow columns are occurrence columns.

Flat and Simple Hierarchical Design

With the above explanation, we can deduce that no part contains duplicate occurrence in a flat or simple hierarchical design. The property editor contains one white and one yellow column for every part and both contain the same value for all the properties. By default, the yellow column is hidden for an INSTANCE mode design. You can click the plus sign to expand the yellow column.

Fig. 3 - Property Editor of a Part in a Flat/Simple-Hierarchical Design

For Complex Designs

The property editor includes a yellow column for each occurrence of a part. If a design contains 3 duplicate hierarchical blocks, for all the parts within that hierarchical block, the property editor will contain one white and three yellow columns.

The Part Reference of parts in yellow columns (at the Occurrence level) must be unique after correct annotation of the design.

Fig.4 - Property Editor of a Part in a Complex Hierarchical Design

In Fig.4, observe that capacitors have four occurrences in the design. C1 has four occurrences, C1, C5, C9 and C13.

Annotation

Annotation is the automated process of assigning reference designators to all the parts placed in the design. Under ideal conditions, annotation must be done as shown in Table1.
However, you can select the desired radio button in Fig.2 for any type of design. So, let's understand what exactly happens when the INSTANCE or OCCURRENCE radio buttons are selected.

Instance Mode

When a design is annotated in the Instance mode, the part reference is assigned/modified in the white column, representing the instance mode, of the property editor.
As a flat or simple hierarchical design is expected to have the same values in the white and yellow columns, this is the preferred mode of annotation for a flat or simple hierarchical design.

Occurrence Mode

When a design is annotated in the Occurrence mode:

Mostly, the part reference is assigned/modified in the yellow column representing the Occurrence mode of the property editor.
At times, the Occurrence value for a property may be picked from the Instance column. Such columns appear striped. In Fig 4a, L1 is striped because it is being picked from instance columns while L3 is not striped because it has been assigned at the occurrence level. (See Fig 5)

Fig 5 - Occurrence mode annotation

Note: As a part will have more than one occurrence in a complex hierarchical design, it is essential that all these occurrences have a unique reference designator in the design. For this, the yellow columns for the parts must have unique reference designator. Therefore, for a complex hierarchical design, the preferred mode of annotation is Occurrence. This ensures that each occurrence gets a unique reference designator.

Controlled Annotation

You can also perform controlled annotation in a multi-page design or a design which contains hierarchical blocks. You can specify the range of reference designator under a hierarchical block or a page. To do this, use the Refdes control required option in the Annotate dialog. Selecting this option gives an additional control to specify range for reference designators as per the hierarchical block or schematic pages.

Fig 6 - options for controlled annotation

For hierarchical designs, you can define a range for each hierarchical block. For flat designs, you can define a range for schematic pages.

Exception in Design Annotation Modes

Sometimes it can be seen that for a flat or simple hierarchical design, the preferred annotation mode is Occurrence. This is the case when any property value has been manually modified in the yellow column (occurrence level). Even adding a space in a property value at the occurrence level will make the preferred mode change from occurrence to instance. In such cases, the preferred mode can be changed using the Accessories > Transfer Occ. Prop. to Instance > Push Occ. Prop into Instance command. Sometimes it can be seen that for a flat or simple hierarchical design, the preferred annotation mode is Occurrence. This is the case when any property value has been manually modified in the yellow column (occurrence level). Even adding a space in a property value at the occurrence level will make the preferred mode change from occurrence to instance. In such cases, the preferred mode can be changed using the Accessories > Transfer Occ. Prop. to Instance > Push Occ. Prop into Instance command.

This will transfer all the yellow column property values (occurrence level properties) to white column (Instance), making both the same and switching the design back to the Instance mode.

Refer the following AppNote for the detailed understanding of these modes in the Capture - Allegro PCB Editor flow.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com/).

Naveen Konchada
Cadence Customer Support

Customer Support Recommended – Regulation Loop Design Using Allegro AMS Simulator (PSpice)

Naveen — Wed, 20 Mar 2013 17:47:00 GMT

Feedback regulation loops are widely used by power electronic designers. It is one of the most important and sensitive parts of a power supply circuit. An incorrect feedback loop design may cause oscillations in the circuit, and also increase the output voltage droops. In order to achieve a stable and tight regulation in the output, it is important to have a correct feedback loop.

To test a feedback loop, generally engineers use trial and error methods with the hardware. This takes a lot of time and labor. Moreover, it is expensive because components and/or PCB boards can be damaged. AMS Simulator (also known as PSpice) can be used by designers to test their loop designs without using any physical hardware circuits, and in the process save a lot of time and cost that goes into fine-tuning the design.

You can get a copy of a sample regulation loop circuit created in PSpice along with the simulation results:

To download the Database (Created with Allegro Design Entry Capture) Click Here
To view the Datasheet Click Here

To demonstrate a regulation loop and compensator circuit, an example circuit is designed with the MAX8566 component and is available in the Cadence PSpice library.

There are two sections: Open loop design and closed loop design.

Open loop design

You can create an open loop design using the Cadence AMS Simulator (PSpice) tool. Using the component MAX8566 available in the Cadence PSpice library, and the datasheet for MAX8566, you can implement an open loop design as per the following figure:

In the open loop design there is no feedback. So the output will increase or decrease with the variation of input voltage. The output voltage is not controlled -- hence V(out) increases as the input voltage increases. The goal is to get a constant 1.9 Volts at the output with a variation of input from 2.3 Volts to 3.6 Volts.

The figure below shows the output voltage waveform when the input supply is at 2.3 Volts, and V(out) = 1.9 Volts

The figure below shows the output voltage waveform when the input supply is at 3.6 Volts, and V(out) = 2.94 Volts

So, the output voltage V(out) increases from 1.9V to 2.94V when the supply voltage increases from 2.3V to 3.6V.

Closed loop design

From the datasheet of MAX8566, Pin 2 is the error amplifier output and Pin 32 is the feedback input.
Pin 25, REFIN, has the reference voltage, which is compared with feedback voltage (FB) to control the pulse width.

From the output filter the corner frequency of the circuit can be calculated as follows:

fcorner=1/(2*Π*√L1*C1)
Since C1 = 33μF, L1 = 200μH, fcorner ~= 2.0 KHz

The filter gives two poles at 2.0 KHz. These two poles produce a phase shift of 180° that makes the output oscillatory. Hence two zeros have to be introduced to cancel the complex poles at the corner frequency and another pole at the origin. This gives a single slope (-20dB/decade) crossing at the ‘0'dB axis, which makes the loop stable. The pole at origin also decides the bandwidth of the converter.

Following the above discussion compensator circuit should have Pole at ω = 0 Hz and Zero at ω = 2 KHz, 2 KHz

Considering all practical conditions, it is advised to choose the Zero location at 1/10th of the calculated value.

For this design, Zeros can be considered at 200Hz. If the transfer function of the following circuit is derived, you can see that there are two zeros at fz1 and fz2 with one pole at fp where

fz1 = 1/(2*Π*R37*C10)= 200Hz
fz2 = 1/(2*Π*R32*C3)=200Hz
fp = 0Hz

After doing all the above changes, the design is ready for closed loop simulation. If simulation is run, following results appear in the PSpice probe window.

The voltage at OUT is constant V(out) = 1.9 Volt.The user can vary the input supply from 2.3 Volt to 3.6 Volt. The output voltage will be constant at 1.9 Volt. There is no oscillation at output voltage and it is stable.

Refer to the complete AppNote for a detailed procedure about each of the steps involved in the process.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Customer Support Recommended – Pin Swapping in Allegro Design Entry CIS and PCB Editor

Naveen — Wed, 09 Jan 2013 17:00:00 GMT

Placement and routing have always been an integral part of printed circuit board design. The productivity of the product is often (if not always) achieved best if the PCB has a proper placement of the components and effective routing to support the placement. With the increased complexity of the designs and smaller board sizes, routing of signals has become more challenging. Designers are always looking for ways to ease routing complexity and hence reduce the turnaround time.

Due to various critical routing situations like differential pairs, bus routings, and critical nets, PCB designers may seek the possibility of pin/net swapping at different levels and at different stages of the design flow. In the Cadence PCB flow, there are fast and easy ways to perform pin swapping, gate swapping and package swapping, all of which help designers ease the routing on the board and synchronize the changes with the schematic. This blog post describes the swapping techniques used in the Cadence PCB Flow using Allegro Design Entry CIS (DECIS) as front-end and Allegro PCB Editor as back-end software.

At a broad level there are 2 steps required to do the swapping:

1. Preparing the schematic and library for pin swapping.

2. Perform the required swapping on the PCB Board file.

Preparing the schematic & library for pin swapping

Specify the swap properties on the pins of the component to be enabled for swapping.

Fig 1. Package properties dialog box showing PinGroup assignment.

Specify a unique number in the PinGroup column for specific pins you want to swap within the gate/function. Only pins with the same value of PinGroup can only be swapped. For example, if all input pins are allowed to be swapped, specify a value of 1 to all input pins and 2 to all output pins for the PinGroup property, as shown in Fig 2.

If you are working with a split part (multi-section part) and wish to swap the pins across slots/sections, you need to have a property called SWAP_INFO specified on each of the sections as shown in the below picture:

Fig 2. User Properties dialog box at Library level

As per the above example, you are allowed to swap the pins across all 4 sections. If you want to restrict the pin swapping across some sections only, the value of SWAP_INFO should be changed accordingly. For e.g.: SWAP_INFO = (S1+S2),(S3+S4) will allow pin swapping between section 1 (S1) & section 2 (S2) and not with the other 2 sections (i.e. S3 and S4). Similarly, Pins between section 3 (S3) & section 4 (S4) can only be swapped within the 2 sections.

NOTE: Pins with the same pin group property can only be swapped among themselves.

Generate the Allegro netlist by choosing Tools > Create Netlist > PCB Editor (tab) from OrCAD Capture

Fig 3. Create Netlist Dialog Box

Create the board automatically by checking the option "Create or Update PCB Editor Board (NETREV)" from the above UI.

Note: If you do not generate the board file during netlist creation, you could import the schematic logic to Allegro PCB Editor using the option File > Import > Logic command from within the PCB Editor.

Pin Swapping in Allegro PCB Editor

Once the schematic netlist is imported in Allegro PCB Editor board file, place the components on the board file and notice the unrouted connections.
To swap the pins on the board file, select Place > Swap > Pins

Fig 4. Pin Swap command in PCB Editor

a. Select the pin on the footprint that needs to be swapped.

b. PCB Editor highlights the other available pins that can be swapped with the selected pin (from step #a). If no pins are highlighted, read the command window at the bottom for an appropriate message.

c. Select the pin from the highlighted group. Right Click > Done, to complete the swap operation.

Fig 5. All swappable pins are highlighted in PCB Editor

Refer to the complete AppNote for a detailed procedure about each of the steps involved in the process and also to learn more about the following:

BackAnnotate the swapping information (updated netlist) to the schematic and get the schematic in sync with the board file.
Some important aspects of the gate/function swap and component swaps.
Generating a swap report.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Customer Support Recommended – Working with PADS to Allegro PCB Editor Translator

Naveen — Tue, 09 Oct 2012 14:00:00 GMT

A recently published AppNote on converting a PADS ASCII file to Allegro PCB Editor has eased the life of many users by providing a step-by-step methodology and appropriate debugging techniques. It also covers various scenarios where Allegro PCB Editor generates errors or warnings during the translation, and explains how to debug errors and obtain a neat board file (.BRD) to be used in Allegro PCB Editor.

The PADS translator can be launched from File > Import > CAD Translators > PADS, from within Allegro PCB Editor. This translator converts the PADS database files (.asc) into Allegro PCB Editor board database files (.brd). It is assumed that the PADS database being translated is completely placed and routed.

Prerequisites for running the translator

PADS ASCII file. (.asc)

PADS Layout creates an ASCII database version file (.asc), which contains all information about decal, part type, part, signal (logical connectivity), route (physical connectivity), and graphics.The component mapping from PADS ASCII file to Allegro prototypes is as per the table given below:

Options file (.ini)

This is the PADS to Allegro PCB Editor Layer mapping file. The accuracy of the translated Allegro PCB Editor .brd file depends on the accuracy of the Copper layer mapping in the layer mapping file (Options File). The default pads_in.ini file is located at <Cadence_Install_Folder>/tools/pcb/bin location. It is advised to have a copy of the default pads_in.ini file in the work area and modify it accordingly.

Steps involved in the translation

1. Create a PADS ASCII file from the PADS job file (.pcb).

2. Create an options file and map the PADS and Allegro PCB Editor layers.

3. Execute the translator.

4. If there are any errors, the translation fails. Open the pads_in.log file to view the errors.

5. Correct the errors either in the .asc or .ini files. At times you may need to recreate the .asc file.

6. Re-run the translator.

7. Open the translated .brd file and review all aspects (pad geometries, symbol geometries, stackup, shapes, and so on) of the design for completeness and correctness.

Note that the translator does not guarantee 100% translation of everything. You need to edit the design that can be maintained completely within Allegro PCB Editor.

The pads_in application reads the input file and determines the number of etch/conductor layers it uses. If all required program arguments are not specified, the translation Options dialog box appears as follows:

The window above allows the users to modify the pads_in.ini file before translation begins.

Avoid editing the default pads_in.ini file located at <Cadence_Install_Folder>/tools/pcb/bin, instead, make a copy of the pads_in.ini file in the working folder and modify the same.

The PADS to Allegro Layer Mapping fields defines the element-layer mapping. The list box contains all the PADS objects (Lines, Copper, Text, Decals, Pads and Vias) and the name of the class and subclass to be mapped with in Allegro PCB Editor. Although the default mapping is done according to the pads (.asc) file, users can map the class / subclass name if needed. Each element appears once for each PADS layer, for a total of 31 entries per element.

All 2D lines on PADS layer 0 are mapped to the BOARD/SUBSTRATE GEOMETRY class and the subclass ALL, which is not pre-defined. Lines on PADS layer 1 map to the ETCH/CONDUCTOR class and the subclass TOP/SURFACE and so on. The translator presets all-necessary ETCH/CONDUCTOR class mappings by default, even if a previous translation created the options file. This is also true during batch translations.

Files Generated during translation

The following files are generated in the output directory after translation is complete:

Most of these are temporary files generated for use by the translator. They remain in the output directory only for reference. The key file is the Allegro PCB Editor board (.brd) file, which is the output from the translation.

Refer to the complete AppNote for a detailed procedure about each of the steps involved in the translation and about the known problems and solutions.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Customer Support Recommended – Appnote on Implementing the Force-Sense Kelvin Connection

Naveen — Thu, 23 Aug 2012 14:01:00 GMT

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin connection) is a common requirement in the PCB design. The separate force (F) and sense (S) connection at the load eliminates any errors resulting from voltage drops in the force lead. The Kelvin Sense connection is routed by separating the sensing signals (S) from the lines, and delivering the power to the load (F). This type of connection prevents noise related problems in a closed loop system because it allows for more accurate measurement of the sense voltage at the load.

Consider the following figure:

A long resistive PCB trace is still used to drive the input of a high resolution Analog-Digital Converter (ADC), with low input impedance. In this case, however, the voltage drop in the signal lead does not give rise to an error, as feedback is taken directly from the input pin of the ADC and returned to the driving source. This scheme allows full accuracy to be achieved in the signal presented to the ADC, despite any voltage drop across the signal trace.

The requirement is to implement this at the schematic created using Allegro Design Entry HDL (DEHDL) to drive the PCB board created using Allegro PCB Editor so that both Force and Sense signals can be identified and constrained independently, and still allowed to be physically shorted in layout.

Flow Overview

This flow is based on a special logical symbol, which is created and saved in a library. The force sense library symbol(s) has shorting schemes defined within the symbol definition, which allows the engineer to seamlessly define the nets to be force sense. When placed in a schematic, the shorting scheme will short at least two sense lines to a force line. While packaging the schematic, separate nets are generated for the Sense and Force lines which are passed on to the PCB board file. As shown in the image below, four sense lines are connected to a force line using the library symbol. Inside PCB Editor, a symbol gets placed, and defines the location of the short for force and sense signals.

The pins of the schematic symbol will have a unique property called PIN_SHORT whose value consists of the logical pin names. While packaging the schematic (running File > Export Physical), based on the <project>.CPM directive, the Packager-XL(PXL) acknowledges the PIN_SHORT property value and creates a NET_SHORT property with the value containing the physical net names connected to the logical pin names.

When you look at the PCB Editor DRA symbol for the footprint, you will see that the pins with different pad stacks are placed at the same location.

Constraint Assignment

This flow allows for individual net constraints to be assigned and used in the front to back flow. As an example, Max Propagation Delay and trace width can be defined.

Refer the following AppNote for the detailed procedure used to implement the Force-Sense (Kelvin) connection using Allegro Design Entry HDL (DEHDL) & Allegro PCB Editor.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Cadence Customer Support

Customer Support Recommended - Appnote on Increasing Performance in Allegro PCB Editor

Naveen — Mon, 16 Jul 2012 16:00:00 GMT

While working on very large scale Printed Circuit Board (PCB) files that contain a huge stack-up along with thousands of footprints and numerous shapes, the performance of the Allegro PCB Editor plays an important role in getting the board built in time. Below are example statistics for a large scale PCB:

Apart from upgrading the platform hardware to have more RAM, multi-core processor, or a better graphics adapter, there are several capabilities you can leverage in the Allegro PCB Editor that will help improve the overall performance.

Have you ever wondered how the Performance Advisor can improve the overall performance of Allegro PCB Editor when working on large board files?

Performance Advisor will analyze a design for possible performance issues and generate a report that provides solutions and recommendations to better manage your PCB design. It is an important check when working on large designs.The report generated would consist of objects responsible for performance degradation like constraints in the design that are not being used, constraint regions defined but with no values, or overlapping shapes.

To access Performance Advisor, select Tools > Database Check from the Allegro PCB Editor. This launches the DBDoctor utility. Performance Advisor is a new utility added in DBDoctor GUI and is available from SPB 16.3 release.

In SPB 16.2, you will need to select Setup > User Preferences > Early_adopter and then select Performance Advisor to enable this function within DBDoctor.

If you are working with large scale designs and/or would like to improve the overall performance of the tool, the following Application Note should be helpful. This Application Note will cover other areas which, when tweaked appropriately, will improve the overall performance of the PCB Designs in Allegro PCB Editor.

Please click here to access the Appnote

Note: The above Appnote can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (COS) .

The Cadence SPB Customer Support Team