Amit Dua Blog

Re: Simulation problem: unwanted zero-width glitch

adua — Tue, 25 Aug 2009 04:56:44 GMT

Hi,

You need to turn off "-event" switch when you are opening the shm waveform database. The default behavior is not to record these glitches (that you want), and it happens only when you specify "-event" option of 'database' tcl command.

The following is copy-paste from NCVLOG product documentation (<ius_inst_dir>/doc/ncvlog/ncvlog.pdf ) on "-event" option of database

database Command Modifiers and Options
-event

Dumps all value changes to the database.

By default, when probing to an SHM database, the simulator discards multiple value changes for an object during one simulation time and dumps only the final value at the end of that simulation time. Use -event if you want to dump all value changes to the SHM database. You can then use the SimVision waveform viewer to expand a single moment of simulation time to show the sequence of value changes that occurred at that time.

Tech Tip: Viewing The Combined Help for IES-XL

adua — Fri, 20 Feb 2009 16:00:00 GMT

IES-XL is comprised of IUS, Incisive Verification Kits with Methodology, Specman, and Enterprise Manager in Desktop Mode.

One of very common query from Incisive Simulator users is the need to view the help of all the IES-XL components together, in a same help browser. The good news is that it is very simple to achieve !!! So, I thought of sharing it here.

Viewing the combined help for IES-XL product: As long as your IES-XL installation is a standard one (meaning that the IES-XL components are installed in the standard hierarchy), you can view the Help for all these components together in one Help browser by starting the Help with the following command:

%cdnshelp Specman-install-path/doc/ieslib.lbr

You can use a relative or absolute path. The full path for the ieslib.lbr file is:

% cdnshelp IES-XL-installdir/SPMN82/doc/ieslib.lbr

(If your IES-XL hierarchy is non-standard, you can edit the ieslib.lbr file to correct the paths in it.)

The combined Help lets you view, navigate between, and search across all of the help for all of IES-XL in one browser.HELP.JPG Simple!!

The following picture shows the IES-XL combined help in tree view:

rgds,

-Amit.

Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator

adua — Wed, 28 Jan 2009 14:00:00 GMT

While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message:

Error! integer overflow
File: ./test.vhd, line = 13, pos = 11
Scope: :$PROCESS_000
Time: 10 FS + 0
./test.vhd:13 i := i - 1;

Incisive is probably the only simulator to report such error condition. The only other popular VHDL simulator was not able to catch/report this condition, when I last faced it. So a user who is not using Incisive Simulator will not be able to know that his design has VHDL integer variables that overflow, which is usually not the real intent.

Ideally, the VHDL code should be fixed this overflow problem, but in many cases the value (integer overflow) of VHDL integer variables is don't care up to certain simulation time or state of simulation. For such cases, the users simply want to ignore this check in Incisive simulator as well.

How to Ignore "Integer Overflow" in Incisive Simulator

The NCVHDL engine in Incisive Enterprise Simulator also allows flexibility to continue running the simulation even when it detects an integer overflow by setting a pre-defined tcl variable - "intovf_severity_level".

The default value of this variable is ERROR, i.e. stop the simulation at integer overflow. The other values of intovf_severity_level are WARNING and IGNORE.

The value of the intovf_severity_level variable can be changed in Simvision GUI. Select Simulation -> Show Variables menu. Select the intovf_severity_level variable and the value associated with this variable. Change the value to IGNORE (or WARNING). The console window echoes the command.

The easiest way to achieve in batch or regression mode is to add "set intovf_severity_level IGNORE" command in a Tcl input file, before the simulation "run" command.

Re: long simulation time problem

adua — Thu, 18 Dec 2008 04:55:34 GMT

In the absence of specific details, the general performance suggestions are:

- Look at the command line switches that can speed up the simulator. For example - -access, -linedebug switches should not be used for batch simulations.

- Profile the simulation run (of about 10-15minutes). This can be done by simply adding "-profile" option to ncsim or irun. It generates ncprof.out and look at the areas where the actual time is being spend.

If you can share more information about the environment (languages involved, any PLIs, RTL or gate level etc), and the profiler output (ncprof.out), then we can help you with more performance suggestions specific to your case. Thanks.

rgds,

Amit.

Re: error when passing a string to ncutils

adua — Thu, 18 Dec 2008 04:42:43 GMT

The argument of $nc_mirror can be string or a register. Now, when it is a string, it should be the hierarchical path of the object. When it is a register then it has to be the 'actual' register. Here you are trying to pass a register whose value is expected to be treated as a string.

So, you need to either declare a string as already suggested in this thread.

Or the other simpler way is to avoid the path_name completely. I mean, instead of first filling a path_name variable with the actual hierarchical path, pass the hierarchical path directly as string in nc_mirror argument. Please see the example below that shows this (It works with IUS6.11 version and don't need any string SV datatype).

//1.v file

module tb_top ();

parameter [1023:0] chip_name="tb_top.I_0.";

reg [1023:0] path_name; wire signal;

io I_O ();

//assign path_name = {chip_name,"module1.module2.signal"};

initial begin

path_name = {chip_name,"module1.module2.signal"};

$nc_mirror("signal","tb_top.I_O.module1.module2.signal","verbose"); //This works.

//$nc_mirror("signal",path_name,"verbose"); //reg to be treated as holding string value. This WOn't work.

end

endmodule

module io;

m1 module1 ();

endmodule

module m1;

m2 module2 ();

endmodule

module m2;

wire signal;

reg r;

assign signal = r;

initial begin

#10 r = 1'b1;

#10 r = 1'b0;

#10 r = 1'b1;

end

endmodule

//end 1.v

Now, Run as follows: (6.1 is fine)

> irun 1.v -access +r

Video Demo: “irun” – The Way to run Simulations!

adua — Wed, 17 Dec 2008 16:30:00 GMT

The irun utility provides a use-model to run simulations with Incisive Simulator in a simple and consistent manner. The main benefit of irun is that it can simulate the multi-language design & verification environments in a single step by simply specifying all input source files and options on a single command line!!

The following demonstration shows the use-model with real examples:

If the video fails to embed please click here.

irun now supports all simulation languages, such as Verilog, VHDL, SystemVerilog, Verilog AMS, VHDL AMS, and even files written in general programming languages like C/C++.

Incisive users can get the complete information about irun in the product documentation available at: http://sourcelink.cadence.com/docs/files/Release_Info/Docs/irun/irun8.2/irunTOC.html.

Looking for comments:

Do you now prefer running Incisive simulations with irun?

Is it convenient over the existing use-model of other simulators?

If you are not yet on irun, then I hope it was a useful introduction that has encouraged you to use Incisive for simulations using irun!!

Re: FSDB dump using IUS6.2-p1

adua — Fri, 24 Oct 2008 11:20:27 GMT

Novas fsdb dump can be generated with IUS simulator by plugging the Novas PLI with ncsim.

The details are available in novas installation. However, IUS simulator supports a native format (SHM) that you may want to use & analyse in Simvision debug & analysis environment.

rgds,

Amit.

Re: How to Compile System Verilog

adua — Fri, 24 Oct 2008 09:56:23 GMT

Use irun to compile & simulate in a single step any/all hdl/hvl supported by Incisive platform.

irun is a smart utility that can compile the file based on the default extension.

Check the irun documentation in <ius_inst_dir>/doc/irun/irun.pdf

rgds,

Amit

Re: Directed vs Random Testing

adua — Fri, 24 Oct 2008 09:48:21 GMT

Hi Mike,

Interesting topic. I agree with your thought that random & contraint random is an advanced & better way to do verification closure specially with metric driven verification based on coverage, but directed is not dead.

However, I would like to add another aspect here. Verification is mostly done with both random and directed, and what is more common depends on the 'stage' of verification i.e. how stable is your DUV is expected to be. Typically verification is mostly started with directed testing (specific basic flow is working like device boot or reaching the initialization stage). So all the basic functions are verified using manual directed testing. Then in the middle stage of verification, it is mostly random testing where you use generate random or interesting scenarios using constraint randomization. Finally in the end the users again do directed testing to test 'corner case' situations that are specific to the device.

Overall, I would roughly put directed-random-directed as the order of sequence of predominate way of verification.

-Amit.

Re: How to mirror VHDL signal in verilog Top Test bench

adua — Fri, 24 Oct 2008 06:57:28 GMT

Venkat,

The problem in your case is that the path specified in your nc_mirror is not correct. You need to get the correct path.

The most likely cause seems to be that the vhdl top path starts with a ":" So instead of the top level entity/architecture, you replace it with ":"

Moreover, there are a few easy ways to find out the correct path with the help of tool:

a) Open the Simvision design browser (ncsim -gui or irun -gui) and drill down to the signal and then see its correct path from Right click menu "Describe" option. You can get the correct pathname which is printed in the console window.

b) On the ncsim tcl prompt (ncsim -tcl or irun -tcl), confirm the path by doing "describe <objectname>" to confirm the path.

c) Use the tcl find command to find the path name of object.

I hope it helps.

rgds,

Amit.