Bringing Static Analysis Methods to Mixed Signal Designs

RajendraPratap — Fri, 26 Aug 2011 16:00:00 GMT

Accurate static analysis and complete coverage of the functional space remain very challenging for mixed-signal designs. The functional verification of mixed -signal designs has never been completely possible.

It is very common to use behavioral models of analog/mixed-signal blocks during the full chip functional verification stage, and to use .lib timing models during the physical implementation stage. There are multiple issues and challenges with this approach:

Creating a .lib timing model of a complex analog/mixed-signal block is sometimes very difficult or impossible due to the complexity of the block.
Using approximate/estimated numbers in a quick timing model leads to a lot of guard-banding, and acts as a hindrance in achieving the most optimized design.
Having multiple views of the analog/mixed-signal block (such as design specification, behavioral model, .lib model, design schematic, physical layout, physical abstract view, etc.) might lead to erroneous designs, because all the different views are never verified against each other.

To create a more accurate .lib timing model of a complex analog/mixed-signal block, the Encounter Digital Implementation system can generate a Full Timing Model (FTM). These models enable a more accurate static timing analysis (STA) of timing paths that cross analog and digital boundaries.

An FTM contains the complete netlist and the parasitics of the analog/mixed-signal block, which helps the designer get a "glass box" view of the block. This not only breaks the complexity of creating the .lib timing model for complex analog/mixed-signal blocks, but also opens the door to using STA methods for verifying the design.

Full Timing Model (FTM) of complex analog/mixed-signal block

The creation of FTM models becomes much easier in an OpenAccess-based physical implementation environment, where full custom analog design is visible in the digital implementation space and vice versa. The connectivity-driven layout implementation flow in Virtuoso, and the capability to understand and visualize complete design in the Encounter Digital Implementation System, enables the designers to use STA on a complete chip with a full view of signals crossing the analog and digital boundaries.

Due to the abstracted single-level view of the physical design in the digital implementation environment, designers can overcome the capacity limitation imposed by the full custom environment and make use of many other statistical and static analysis tools which are far faster than SPICE or mixed-SPICE time domain simulations.

For example, one of the most useful capabilities of the digital environment is signal integrity (SI) analysis, which uses the worst case "all aggressors" method where all the nets in the design are analyzed one by one, while assuming that the rest of all the nets in the design are aggressors. Aggressors are eliminated based on the coupling capacitance that each of them have with the victim net. This method of SI analysis is very useful for analyzing top chip-level nets in the design, including long nets that sometimes run from one corner of the chip to the other, such as busses. SI also helps analyze the transition time and signal delays on long nets.

Rajendra Pratap

Mixed-Signal Physical Design Implementation Made Easy

RajendraPratap — Thu, 16 Jun 2011 17:00:00 GMT

Getting a complex mixed-signal design assembled and completely analyzed for mask design is a huge challenge today. The IPs are complex and too many decisions need to be made to meet design budgets. All this is not possible with anything less than a fully automated, front-to-back mixed-signal design solution.

On top of mixed-signal complexity, battery operated wireless and hand-held mobile applications are extremely sensitive to power. Digital EDA tools bring the full force of the digital low power solution to mixed-signal designs. I can say that all the designs today are mixed-signal designs, and that mixed-signal implementation remains one of the biggest design challenges. A typical chip design today is a complete system with millions of gates that make up large numbers of DSPs, memories and processors, all of which must interface with the real world through displays, antennas, sensors and multiple communication channels. This requires integration of analog and digital content, without compromising performance or size, and on a technology scale that dramatically increases vulnerability to process and electrical variation.

Challenges to mixed-signal designs are real and are increasing. With process technologies moving to 32nm and below, the cost of design re-spins increases exponentially. Over 60 percent of design re-spins at 32nm and below are due to mixed-signal functionality, resulting in an additional cost and a delay in product rollout.

Designers require new implementation methodologies that will help solve these potential problems. Currently, the majority of mixed-signal chip implementation planning is done by hand, which is a slow and laborious process that can lead to design errors and numerous iterations. During final assembly, the completed blocks are also placed and routed manually without the aid of DRC automation. Big analog designs with digital blocks traditionally start with schematic design, and then iterate through the floorplanning steps by manually placing the blocks according to design architecture, and assigning pins for blocks that could be analog as well as digital. Additionally, in the beginning of the design cycle, designers just have the top-chip floorplan and do not have much insight into the design implementation details.

Analog-on-Top (AoT) and Digital-on-Top (DoT) are block-based methodologies sufficient for many designs when functionality can be contained within the blocks with few analog-digital interfaces that are critical for design performance. With OpenAccess as an integrated design database, many of those lossy format related design data translations can be avoided, and designers can use both analog and digital implementation platforms for achieving fast and more accurate results. Complete design analysis also becomes much more manageable and comprehensive with a full chip view including analog and digital blocks together within both physical implementation platforms.

Faster digital analysis methods such as static timing analysis, signal integrity analysis, and IR drop can be applied on mixed signal designs. One can get best of both full custom analog implementation environment in Virtuoso IC 6.1 and digital implementation in the Encounter Digital Implementation platform. Both IC 6.1 and Encounter Digital Implementation 9.1 read and write the OpenAccess database. I invite further discussions to challenge, discuss and debate some of the possibilities that are opened by OpenAccess as an integrated design database.

Rajendra Pratap

Rajendra Pratap Blog

Bringing Static Analysis Methods to Mixed Signal Designs

Mixed-Signal Physical Design Implementation Made Easy