Neil Hand Blog

Martin Lund on the Future of IP (Video Interview)

Neil Hand — Wed, 13 Jun 2012 22:33:00 GMT

As SoC complexity continues to rise, more IP is being utilized, and the quality and completness expected from IP is increasing rapidly. The IP industry needs to change to meet these new expectations, or risk becomming part of the problem they are actually trying to solve.

Martin Lund, Senior Vice President at Cadence, was recently interviewed at DAC2012 by EE Times’ Brian Fuller. Martin laid out a vision for commercial IP, describing requirements for integration, test benches, certification environments, integrity models, and test chips to deliver high quality, reliable IP that will truly reduce costs and improve time to volume.

Check out the interview here: http://video.eetimes.com/playlist-video/dac-2012/1653470487001/eetimes-live-stream-dac-2012-martin-lund/1675544149001

Neil Hand

New Memory Technologies, New Possibilities

Neil Hand — Mon, 11 Apr 2011 15:30:00 GMT

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will impact everything from the user experience to the applications that are possible. There is nothing quite so sad as a shiny new gadget that falls short because of poor memory performance (something easily avoided with the right IP), or trying to install a new app only to have to decide what you must delete to make room for it.

It’s been a busy few weeks for the IP team with the announcement of support for two new memory technologies – DDR4 and Wide I/O.

With Wide I/O and DDR4 offering significantly improvements for the device classes they target for, it’s exciting to contemplate how design teams will leverage them to deliver on the next wave of devices. So whether it’s a high performance gaming desktop, a sleek new tablet, or enterprise equipment that interests you, new memory technologies will play a key role.

Learn more about Cadence Design IP for Memory and Storage.

Neil Hand

Effectively communicating Low-Power and Power-Efficient Design knowledge

Neil Hand — Wed, 03 Sep 2008 15:21:00 GMT

For those of you interested in the Power space I recently had an article published on the Power Management DesignLine Europe website that talks about the challenges of capturing and communicating expertise and best practices throughout an organization (both large and small).

The article talks about the ideas behind creating a design kit focused on power, and while not directly talking about Cadence Low Power Kit it does capture the experiences we had in creating this Kit as a way to better communicate our own Low Power knowledge with our customers. The idea is to create executable methodologies, backed by foundational IP, and concrete examples - as an extension to traditional methodology documentation.

I would be interested in any feedback that you may have on the article and the idea of the design kit. Also don't forget that if there is a topic related to Low-Power (LP) or Power-Efficient (PE) design that you would like to see covered either in the blog - or in a wider forum please let me know.

The article can be found by clicking here.

Customer Experiences With Low-Power Design

Neil Hand — Mon, 14 Jul 2008 01:24:00 GMT

Hello and welcome to the new Cadence community site, and my first blog post. You will see me here from time to time posting on topics and trends in the Power Efficient Design and Low Power Design area -- and most importantly, how we as a community can play a bigger part in ensuring your success.

If you have any topics you would like to see me cover, please feel free to leave a comment or send me a private message.

For my first post, and keeping with the theme of working as a community to help ensure success, I wanted to highlight a recently produced online guidebook published by the Power Forward Initiative (PFI) that highlights user experiences in Low-Power Design -- "A Practical Guide to Low-Power Design" (available at http://www.powerforward.org/lp_guide/).

Our team recently sat down with Dr. Chi-Ping Hsu, Cadence Corporate Vice President, Chief Strategist, Product and Technology, to learn more. Dr. Chi-Ping Hsu is the originator and leader of the Power Forward Initiative.

What is the low power guide?

Dr. Chi-Ping: The new guide is a compendium of the world’s leading advanced low power design techniques enabled using Common Power Format (CPF) methodology and tool flow. It includes real life design experience from many PFI member companies leveraging and validating the advanced CPF-enabled methodology. The guide embodies the collective intellectual work and experience of the best engineers in the electronics industry. Our goal in developing this living, Web-based book is to share PFI’s experience with the world’s design community and accelerate low power design adoption among the vast majority of the industry who are interested in making the world greener. Cadence is very committed to sharing low power expertise—the company spearheaded and led the electronics industry with the automation of a holistic low power design solution in 2005.

Who will benefit most from the guide?

Dr. Chi-Ping: This is a must read for any design team who is beginning to adopt advanced power management design techniques.

How can the low power guide help chip designers?

Dr. Chi-Ping: The guide provides an overview of available low power techniques and how they can be applied in the design, verification and implementation of integrated circuits. Most importantly, examples of real design projects are included to help illustrate how the methodology has already been applied successfully on real silicon.

Why did the Power Forward Initiative develop this guide?

Dr. Chi-Ping: The 28 members of the Power Forward Initiative have been working to enable rapid deployment of a design automation solution that comprehends power at every stage of the design process. They have accumulated precious low power design experiences through extensive design and silicon validations. We have also developed an ecosystem that supports a working power intent standard and methodology. This guide could help accelerate the user adoption of low power design techniques across the industry.

How does the low power guide relate to the Common Power Format and the Low Power design?

Dr. Chi-Ping: The guide embodies low power design methodology that can be automated holistically across the design flow by using CPF to capture the designer’s low power intent early in the design process and apply it throughout the design, verification, implementation and signoff stages of design.

How can designers get a copy of the low power guide?

Dr. Chi-Ping: The guide is free and available for download from the Power Forward Web site, www.powerforward.org.

What are the future plans for CPF?

Dr. Chi-Ping: CPF is a methodology with automated tools and flow rather than a format itself. It will continue to evolve as design methodology continues to advance. We will continue to work on the low power guide to capture the latest development and experience. This is one of the reasons the PFI advisory team chose to produce the guide electronically as opposed to printing it. We want to make sure the guide continues to grow and deliver state-of-the-art value to its readers. As for CPF standardization, you may have heard of Cadence’s recent contribution of extensions to CPF1.0 standard in respond to Si2’s Low Power Coalition roadmap and request for contribution. The extensions are intended to address the growing user need for low power IP reuse methodology where IP (soft or hard) can be developed and validated, independent of target environment, and then be reused and configured at the SoC level without the need for re-writing power specs as captured in CPF.

Dr. Chi-Ping Hsu is Corporate Vice President, Chief Strategist, Product & Technology at Cadence. He was formerly President and COO of Get2Chip, before the company merged with Cadence Design Systems in April 2003. Prior to Get2Chip, Chi-Ping was Executive Staff of Technology and Products at Avant! for seven years. Prior to Avant!, Chi-Ping held senior management positions in engineering and marketing at Hughes, Cadence, and Pie/Quickturn. Dr. Hsu holds a Ph.D. degree in EECS from University of California, Berkeley, and a BSEE degree from National Taiwan University.

About Power Forward Initiative: The Power Forward Initiative, which has more than 25 member companies, is an industry initiative sponsored by Cadence with the goal of enabling the design and production of more power-efficient electronic devices. The Advisory Group consists of representative companies across the design chain from microprocessors to IP to foundries and semiconductor companies and includes four EDA companies including Cadence.