https://community.cadence.com/searchen-USTelligent Community 11en-usnoSearch resultshttps://community.cadence.com/cadence_technology_forums/f/rf-design/59462/error-in-cds_srr-line-20Sun, 26 May 2024 17:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59462sepideh/cadence_technology_forums/f/rf-design/59462/error-in-cds_srr-line-200 Hi, In the MATLAB, I am using cds_srr and cds_innersrr commands. Although I set the path to the spectre root, I face this error: One or more output arguments not assigned during call to "cds_innersrr". Error in cds_srr (line 20) sig = cds_innersrr(dirname, dataset, signame, verbose); Error in techsweep_spectre_run (line 64) struct_n = cds_srr(c.outfile, c.sweep, params_n{1}); I would highly appreciate it if you could help me. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-45/1398409#1398409Sun, 26 May 2024 17:02:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398409ramdev/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-45/1398409#1398409 ; Function to check if the object is a metal layer procedure(dblsMetal (obj) let((layerName) layerName = obj~>layerName ; Adjust the metal layer names as per your environment member(layerName '("METAL1" "METAL2" "METAL3" "METAL4" "METAL5" "METAL6")) ) ) ; Function to determine the appropriate via type based on layer names procedure(getViaType(layer1 layer2) let((viaType) cond ( ((equal layer1 "METAL1") && (equal layer2 "METAL2")) (viaType = "VIA12") ((equal layer1 "METAL2") && (equal layer2 "METAL1")) (viaType = "VIA12") ((equal layer1 "METAL2") && (equal layer2 "METAL3")) (viaType = "VIA23") ((equal layer1 "METAL3") && (equal layer2 "METAL2")) (viaType = "VIA23") ((equal layer1 "METAL3") && (equal layer2 "METAL4")) (viaType = "VIA34") ((equal layer1 "METAL4") && (equal layer2 "METAL3")) (viaType = "VIA34") ((equal layer1 "METAL4") && (equal layer2 "METAL5")) (viaType = "VIA45") ((equal layer1 "METAL5") && (equal layer2 "METAL4")) (viaType = "VIA45") ((equal layer1 "METAL5") && (equal layer2 "METAL6")) (viaType = "VIA56") ((equal layer1 "METAL6") && (equal layer2 "METAL5")) (viaType = "VIA56") (t (error "Unsupported layer combination for via creation.")) ) viaType ) ) ; Main function to connect metals procedure(connectMetals() let((selection metals sameNetLayer1 sameNetLayer2 viaType startPoint endPoint) ; Get the selected objects using geGetSelSet for partial selection selection = geGetSelSet() unless (selection error("No objects selected.") ) ; Filter selected metals metals = setof(obj selection dblsMetal(obj)) ; Debug message to print the metals found printf("Metals selected: %L\n" metals) ; Check if two metals are selected unless (length(metals) == 2 error("Please select exactly two metal shapes.") ) ; Check if metals are on the same net sameNetLayer1 = car(metals) sameNetLayer2 = cadr(metals) unless (sameNetLayer1~>net == sameNetLayer2~>net error("Selected metals are not on the same net.") ) ; Get the starting and ending points for creating the path startPoint = list((sameNetLayer1~>bBox~>llx + sameNetLayer1~>bBox~>urx) / 2 (sameNetLayer1~>bBox~>lly + sameNetLayer1~>bBox~>ury) / 2) endPoint = list((sameNetLayer2~>bBox~>llx + sameNetLayer2~>bBox~>urx) / 2 (sameNetLayer2~>bBox~>lly + sameNetLayer2~>bBox~>ury) / 2) ; Check if metals are on the same or different layers if (sameNetLayer1~>layerName == sameNetLayer2~>layerName) then ; Connect metals directly printf("Connecting metals directly without via.\n") dbCreatePath(sameNetLayer1~>cellView sameNetLayer1~>layerName sameNetLayer1~>purpose startPoint endPoint) else ; Determine the via type viaType = getViaType(sameNetLayer1~>layerName sameNetLayer2~>layerName) ; Debug message to print the via type printf("Connecting metals with via type: %s\n" viaType) ; Create a via to connect different layers dbCreateVia(sameNetLayer1~>cellView viaType startPoint) ) ; Ensure the Layout window is active and the function is loaded when (hiGetCurrentWindow()~>type == "layout" hiSetBindKey("Layout" "Ctrl c" "connectMetals()") printf("Bindkey for 'connectMetals' is set to Ctrl+c\n") ) ) ) https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-45/1398408#1398408Sun, 26 May 2024 16:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398408ramdev/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-45/1398408#1398408 Yes andrew i used image to copy it. I couldn’t copy. I will try to update same code. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-45/1398407#1398407Sun, 26 May 2024 15:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398407Andrew Beckett/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-45/1398407#1398407 Given that this code is full of errors - spaces in the wrong place, missing parentheses, misspelt function names, debugging it is going to be pretty much impossible. Did you copy and paste it from an image of the code (using some kind of optical character recognition?), because there are so many problems with it that I'd hate to try to guess where the problem is. Andrew https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59460/extract-the-list-of-devices-used-in-the-layout/1398406#1398406Sun, 26 May 2024 15:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398406Andrew Beckett/cadence_technology_forums/f/custom-ic-design/59460/extract-the-list-of-devices-used-in-the-layout/1398406#1398406 Vishesh, The simplest way (without needing to write any SKILL code) would be to use either the UNIX "fastTree" command (if you run without any arguments it will tell you how to use it) or in the CIW Tools→Print Hierarchy Tree. You could take the output file from this and then process the result to find all the cellViews from your PDK. For example: fastTree -lib ether -cell top -view layout awk '$1=="gpdk090" { print $1,$2,$3 }' top.layout.tree | sort -u outputs the hierarchy from ether/top/layout and then processes it to find all the cellViews from gpdk090 - here's the output: gpdk090 nmos1v layout gpdk090 nmos2v layout gpdk090 nmoscap2v layout gpdk090 nmoscap2v3 layout gpdk090 pmos1v layout gpdk090 pmos2v layout gpdk090 pmoscap2v layout gpdk090 resm2 layout gpdk090 resm3 layout gpdk090 resnsppoly layout gpdk090 vpnp5 layout Regards, Andrew https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-45Sun, 26 May 2024 14:20:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59461ramdev/cadence_technology_forums/f/custom-ic-skill/59461/get-getq-first-arg-must-be-either-symbol-list-defstruct-or-user-type---67-453 I’m trying to connect a same nets with different metal layers to connect together with a via, when I trying to execute a code it runs. But when I trying to use that it shows this error in ciw window. get/getq: first arg must be either symbol, list, defstruct or user type - 67.45 here is the code ; Function to check if the object is a metal layer procedure(dblsMetal(obj) let((layerName) layerName = obj~ > layerName ; Adjust the metal layer names as per your environment member(layer Name '(METAL1" "METAL2" "METAL3" "METAL4" "METAL5" "METAL")) ) ) ; Function to determine the appropriate via type based on layer names procedure(getViaType(layer1 layer2) let(via Type) cond( (equal layer1 "METAL1") && (equal layer2 "METAL2")) (via Type = "VIA12") (equal layer1 "METAL2" && (equal layer2 "METAL1")) (viaType = "VIA12") (equal layer1 "METAL2") && (equal layer2 "METAL3")) (viaType = "VIA23") (equal layer 1 "METAL3") && (equal layer2 "METAL2")) (via Type = "VIA23") (equal layer 1 "METAL3") && (equal layer2 "METAL4") (via Type = "VIA34") (equal layer1 "METAL4") && (equal layer2 "METAL3")) (viaType = "VIA34") ((equal layer 1 "METAL4") && (equal layer2 "METALS")) (viaType = "VIA45") (equal layer 1 "METAL5") && (equal layer2 "METAL")) (viaType = "VIA56") (equal layer 1 "METAL") && (equal layer2 "METALS")) (via Type = "VIA56") (t error"Unsupported layer combination for via creation.")) ) viaType ) ) ; Main function to connect metals procedure(connectMetals let((selection metals sameNetLayer sameNetLayer2 via Type startPoint endPoint) ; Get the selected objects using geGetSelSet for partial selection selection = geGetSelSetO unless(selection error ("No objects selected.") ) ; Filter selected metals metals = setof(obj selection dbIsMetal(obj)) ; Debug message to print the metals found printf("Metals selected: %L\n" metals) ; Check if two metals are selected unless(length(metals) = = 2 error("Please select exactly two metal shapes.") ; Check if metals are on the same net sameNetLayer = car(metals) sameNetLayer2 = cadr(metals) unless(sameNetLayer ~>net == sameNetLayer2~>net error("Selected metals are not on the same net.") ) ; Get the starting and ending points for creating the path startPoint = list((sameNetLayer1~>bBox~>IIx + sameNetLayer~>bBox~>urx) / 2 (sameNetLayer1~>bBox~>Ily + sameNetLayer1~>bBox~>ury) / 2) endPoint = list((sameNetLayer2~>bBox~>lIx + sameNetLayer2~>bBox~>urx) / 2 (sameNetLayer2~>bBox~>Ily + sameNetLayer2~>bBox~>ury) / 2) ; Check if metals are on the same or different layers if(sameNetLayer1~>layerName = = sameNetLayer2~> layerName then ; Connect metals directly printi( Connecting metals directly without via. In') dCreatePath(sameNetLayer1 ~ > cellView sameNetLayer1 ~ > layerName sameNetLayer1 ~ > purpose startPoint endPoint ; Determine the via type via Type = getVia Type(sameNetLayer1~> layerName sameNetLayer2~> layerName) ; Debug message to print the via type printf("Connecting metals with via type: %5\n" via Type) ; Create a via to connect different layers dbCreateVia(sameNetLayer1~> cellView viaType startPoint) ) ) ) ; Ensure the Layout window is active and the function is loaded when(hiGetCurrentWindow0 ~>type == "layout" hiSetBindKey("Layout" "CtrI c" "connectMetals") printf("Bindkey for 'connectMetals' is set to Ctri+ c\n*)) https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59460/extract-the-list-of-devices-used-in-the-layoutSun, 26 May 2024 07:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59460Vishesh Gupta/cadence_technology_forums/f/custom-ic-design/59460/extract-the-list-of-devices-used-in-the-layout1 Hi, I submitted a layout design for the tapeout. The company wants to confirm that they are using the correct flow and therefore want to extract the list of devices (pcell names) used in my design. Can someone help me how could it be done? Thanks and Regards, Vishesh https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398403#1398403Sun, 26 May 2024 07:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398403Vishesh Gupta/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398403#1398403 Thanks a lot Frank for the suggestion. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398402#1398402Sun, 26 May 2024 07:49:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398402Vishesh Gupta/cadence_technology_forums/f/custom-ic-design/58643/inherited-terminal/1398402#1398402 Thanks a lot Andrew for helping. Regards, Vishesh https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/59459/error-orprobe-3133-when-measuring-slew-rate-of-max44284h-in-pspiceSun, 26 May 2024 06:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59459WillChen072/cadence_technology_forums/pcb-design/f/pspice/59459/error-orprobe-3133-when-measuring-slew-rate-of-max44284h-in-pspice0 I am currently testing the slew rate of the MAX44284H current-sense amplifier using PSPICE. When I use the "Evaluate Measurement" function to measure the falling edge slew rate (SlewRate_Fall(1)), I encounter the following error message: ERROR(ORPROBE-3133): Measurement not evaluated due to Measurement search failure 1 How can I resolve this error to correctly measure the falling edge slew rate of the MAX44284H using the slewrate_Fall(1) function in the "Evaluate Measurement" tool? Are there any other settings or methods that could help solve this problem?Thank you for your assistance! https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59439/how-do-i-get-a-click-event-on-schematic-in-my-orcal-tcl-code/1398401#1398401Sat, 25 May 2024 12:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398401Jadystone/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59439/how-do-i-get-a-click-event-on-schematic-in-my-orcal-tcl-code/1398401#1398401 If I can get the sch window handle, it will work. I think the bind code should be: bind $psch_window {handleClick} Probem is how can I get the $psch_window. Current my temporary solution is replacing " vwait clicked" with update after 1000 That can let me to get a click position on sch page. But it must click the sch window within a second. Otherwise It could get a false position that I don't want. https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398400#1398400Sat, 25 May 2024 08:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398400srish09/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398400#1398400 You can try updating the reference designators through de-hdl console commands and change editor. Check this article: Article (20493540) Title: How to update multiple part references in Concept HDL design at once URL: support.cadence.com/.../ArticleAttachmentPortal https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59435/re-run-monte-carlo-failures-for-two-step-trim-simulations/1398397#1398397Fri, 24 May 2024 21:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398397TempViator/cadence_technology_forums/f/custom-ic-design/59435/re-run-monte-carlo-failures-for-two-step-trim-simulations/1398397#1398397 After some experimenting, the issue here boils down to a Normal vs. Troubleshooting run and how calcVal passes information. For the bulk of operating sims, I use the calcVal function in a way that passes data assuming that the trimming and post-trimming tests occur in the same run and sequentially: calcVal("Trim_VBG_best" "VBG_Trim" ?cornerName "Trim" ?defaultVal 0) But what I really need is for calcVal to pull info from the successful VBG_Trim test and pass it to the Troubleshooting rerun of the next test. The only way I see to do that is to separate the rimming run into a stand-alone simulation that writes its data, and then set up the calcVal reference to an already-completed test results, perhaps like this: calcVal("Trim_VBG_best" "VBG_Trim" ?cornerName "Trim" ?historyName "VBG_Trim_Only" ?defaultVal 0) where VBG_Trim_Only is the name of a stand-alone sim that only trims, but does not run post-trim sims. I have not yet searched for it, but I think there is some detail to making sure the Monte Carlo run sequence is the same for two separate simulations...this is necessary to make sure the trims correlate to the right post-trim sims. Is there a simpler way to make the Troubleshooting reruns pick up the calcVal info? And am I missing a step in getting this to work, as described above? Thanks for any useful replies! https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398396#1398396Fri, 24 May 2024 18:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398396Son/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398396#1398396 Thanks rg13 for your responding. My current schematic has the Ref Des "J605". How can I add "09" into this Ref Des after "J" and before "605" J605 => J09605 I can do manually but I'd add "09" for entire schematic. Thanks, Son https://community.cadence.com/cadence_technology_forums/pcb-design/f/pspice/59457/ability-to-simulate-audio-wav-filesFri, 24 May 2024 17:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59457AyushD/cadence_technology_forums/pcb-design/f/pspice/59457/ability-to-simulate-audio-wav-files0 Audio simulation can be helpful for acoustic analysis in medical hearing aids, audio tuning in audio amplifier, etc. Are you finding it difficult to simulate .WAV audio files? From 23.1 ISR 4 onwards PSpice A/D has been introduced with ability to support audio simulation. You can use this amazing feature and simulate audio input files used in circuit design and generate electronic/digital audio as output by using the WAVESRC component in PSpice. You need to place the WAVESRC component from Component Explorer window and add the following properties. Channel: Information of the channel Path of audio file (.WAV format) to be imported. Explore this feature and let us know how you are using it in your projects. Team DesignTech Cadence Design Systems https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59456/is-there-is-a-method-to-compress-the-pcb-symbol-file-sizeFri, 24 May 2024 17:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59456gvellet/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59456/is-there-is-a-method-to-compress-the-pcb-symbol-file-size0 Hi, I have designed a complex PCB symbol, then I mapped a step model. Unfortunately the step model was large (24MB) and it resulted in the symbol file of about 6MB. Recently I found another STEP model which is much smaller. I thought lets update the symbol with this new model, it will make the symbol file size much smaller. Unfortunately, the symbol file size remained almost the same. it seems that the space taken by the previous step model is not freed up. I looked in all the menus of Orcad pcb editor but I could not find any function to clean the symbol file size. I made a test by deleting all pins, shapes, step, and lines. I kept only the refdes and saved the symbol but still the filesize is a large 5MB. It seems that I have to redesign the symbol from scratch if I want a smaller file size. Anyone has a suggestion? Thanks https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59453/resolving-drc-errors-for-blind-vias-on-bga-pads-in-allegro/1398395#1398395Fri, 24 May 2024 15:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398395avant/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59453/resolving-drc-errors-for-blind-vias-on-bga-pads-in-allegro/1398395#1398395 Can you set "pad-to-pad connect" to allow via on pin? You could use a physical constraint region to allow it in a specific area only. https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398394#1398394Fri, 24 May 2024 14:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398394rg13/cadence_technology_forums/pcb-design/f/design-entry-hdl/59445/add-prefix-into-the-current-schematic/1398394#1398394 You can achieve it by defining the REFDES_PATTERN for your design. In this case you can define refdes_pattern as follows: “($PHYS_DES_PREFIX)(09)[0-9](1)” For more details on this, you can refer Application Note "Practical Applications of REF_DES_PATTERN" by following link from Cadence online support portal: Article (20416521) Title: Practical Applications of REF DES PATTERN URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050Q0EAI Let me know how it goes. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59450/library-manager---open-terminal-option-on-right-clicking-any-cell-or-views/1398393#1398393Fri, 24 May 2024 14:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398393firebolt3/cadence_technology_forums/f/custom-ic-design/59450/library-manager---open-terminal-option-on-right-clicking-any-cell-or-views/1398393#1398393 My admin has enabled failsafe for all applications including virtuoso which gets auto-killed after certain period of time. This leaves lock files. Also, can we add option like fix lock file under right click? I have seen coth state option in one of old project. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398392#1398392Fri, 24 May 2024 14:43:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398392Mabr86/cadence_technology_forums/f/custom-ic-skill/59455/execute-only-the-procedure-of-a-program/1398392#1398392 Ok, thank you for your quick response.