Wilbur Luo Blog

DAC DFM Coalition - Do You Work On Sunday Afternoons?

wilbur — Wed, 14 Jul 2010 17:15:00 GMT

It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010.

On the panel were:

Luigi Capodieci - GLOBALFOUNDRIES
Rhett Davis - N. Carolina State Univ.
Bob Pack - Grid Simulation Technology, Inc.
Wilbur Luo - Cadence Design Systems, Inc.
Qi-De Qian - IC Scope Research

I took the opportunity to present the challenges and need for tight DFM integration into the design process. The goal is to generate layout that is highly manufacturable while meeting schedule and performance/power/area requirements. This "correct by construction" approach has, up until now, been fairly elusive due to old software architectures and limitations in the performance of the analysis tools.

What has changed? The next generation of digital and custom implementation tools (like Encounter and Virtuoso) are architected for plug-in analysis components. With this type of plug-in, analysis can be performed incrementally with knowledge of design intent and design state. For example, why spend costly CPU cycles to re-check an area that hasn't been changed during an ECO?

On the analysis front, new techniques have been created to speed-up checking (in some cases by several orders of magnitude). An example is pattern matching. Take a look at the presentation from GLOBALFOUNDRIES (by Luigi Capodieci). Through a tight foundry/EDA/design partnership, GLOBALFOUNDRIES and Cadence co-invented a new methodology (DRC+) to identify and fix litho problems that is 100x faster than traditional approaches. At 28nm there is a large increase in data volume and in proximity effects, so without new thinking at this node, it would be impossible to move litho hotspot prevention/detection/correction early into the design process.

Here are the papers presented at the workshop.

Wilbur Luo

Tidbits From TSMC Q209 Earnings Call - 40nm Yield

wilbur — Fri, 07 Aug 2009 13:00:00 GMT

Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield.

Dr. Liu really hits on a key element of DFM - which is design/layout dependency. Simply put, rule-based techniques are insufficient. To maximize yield, you need to augment with model-based techniques to be able to predict and optimize any given design. Think of model-based techniques as a virtual fab where you can analyze your design and predict the silicon behavior - without actually going to silicon.

Given this, the recent DFM checking mandates, the increased focus on variability control in Reference Flow 10... projects need to consider Manufacturability and Variability in their flow and schedules

[Excerpt from Q209 Earnings Call]

Christopher Muse - Barclays Capital

Okay, great. And then I guess last question for Mark Liu, I appreciate your comments on the 40-nanometer yield challenges. I was wondering if you could elaborate on your defect reduction methodology, where the problems lie and how you are resolving them, and what gives you the confidence you can get the yields that you are targeting in September?

Dr. Mark Liu

Okay, in this generation, what we find, what’s important is the design, layout styles because in our products, we do see the design has a -- because a different product has a different yield showing and it ranged quite widely and we find that for those products, the yield is low is mainly because of the design, layout dependence. What we call design for manufacturing. That is in plain English is when the design cannot be completely described by the design rule, we have additional algorithm software to optimize the layout so that it gets the best yield.

Wilbur Luo

The Buzz Around New Business Models

wilbur — Fri, 06 Mar 2009 11:00:00 GMT

The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested in the next generation tools. The same complaints can be heard from the foundries regarding their wafer pricing

Companies have tried royalty-based models before in the past (e.g., $/wafer or even profit sharing). But it hasn't been sticky. Is the industry ready for a new model? I think sharing in the upside and potential downside of a particular design from inception to volume is fair. But it also would mean that EDA companies and foundries would have to participate even earlier (and later) in the product lifecycle - from design spec/marketing through product introduction.

That's a pretty big change that goes beyond just the business model. But maybe at 32nm and below, where designs cost upwards of $75M to bring to market, this type of collaboration and risk/reward model is required and desired

Getting Good Silicon With More Accurate Timing

wilbur — Fri, 09 Jan 2009 17:43:00 GMT

In these difficult economic times, achieving silicon success (functional and meeting specs) within an iteration becomes an even higher priority than before; there might not be a second chance to win that socket or hit that sales window.

To that end, there appears to be a heightened interest in variation-aware methodologies to more accurately predict the electrical characteristics due to manufacturing/process variation. CMP, Litho, and stress effects all play a role in changing the transistor and interconnect characteristics at 90nm, 65nm, and below.

Are you concerned? How much variation would start being a concern for you? 5% in the critical path? 10%? I'd like to hear the risk tradeoff people make.

DFM in Disguise

wilbur — Sun, 13 Jul 2008 06:44:00 GMT

DFM is an overloaded acronym/word. In some design flows, DFM can be found front-and-center and in others, it is just along-for-the-ride. It may be disguised as more rules in a process/rules design manual, or it can be quite explicit in a model-based analysis and optimization flow.

But wait, let's get through some of the formalities... My name is Wilbur and I'm an engineering manager in the front-end DFM space. My focus areas are: interconnect synthesis and optimization, model-based analysis, and pattern analysis.

I'm looking forward to sharing my thoughts and hearing yours about how we're going to add predictability and increase manufacturability in the design process. I also want to collectively ponder how the DFM space will evolve. Stay tuned...