Arthur Schaldenbrand Bloghttps://community.cadence.com/search?q=*%3A*&category=blog&users=2892&sort=date%20descSearch results for '*:*' by user ID 2892en-USZimbra Community 8noSearch results for '*:*' by user ID 2892Subscribe with My Yahoo!Subscribe with NewsGatorSubscribe with My AOLSubscribe with BloglinesSubscribe with NetvibesSubscribe with GoogleSubscribe with PageflakesMeasuring Bipolar Transistor ft with Fixed Base-Collector Voltagehttp://feedproxy.google.com/~r/cadence/community/blogs/2892/~3/5VGqFC0t0AA/measuring-bipolar-transistor-ft-with-fixed-base-collector-voltageTue, 12 Jun 2012 12:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1311527Art3/cadence_blogs_8/b/rf/archive/2012/06/12/measuring-bipolar-transistor-ft-with-fixed-base-collector-voltage2Recently I had a question from reader. He asked a good question: "How do you to measure a bipolar transistor's ft when the base-collector voltage, Vbc, is fixed?" Attached is a modified version of the testbench that allows a user to measure ft with a fixed Vbc. While the aesthetics are not as pleasing as the original testbench, it does the job. The testbench is shown in Figure 1. The base of the bipolar transistor, the DUT, is grounded. The collector of the transistor is connected to a dc source, VBC, which is used to set the base-collector voltage of the transistor. The emitter is connected to a current source that sets the bias current, IE. An additional supply, VBE, is included to assure the base-emitter junction is always forward biased. For these tests, the dummy power supply voltage, VBE, is set to 5V. Figure 1: Ft Testbench modified for fixed Vbc To measure the ft, use the same methodology previously described : 1. Run a dc operating point analysis and save the collector current 2. Run an ac analysis, sweep the frequency beyond the maximum value of ft a. In this case, the ac sweep was from 1Hz to 10GHz b. Save the base and collector currents 3. Use the Virtuoso ViVA waveform calculator to measure the ac beta of the transistor a. The ac beta is ic/ib, where ic and ib are the ac currents 4. Use the Virtuoso ViVA waveform calculator cross() function to measure the ft a. Measure the frequency where the value of the ac beta=1, or 0dB 5. In Virtuoso Analog Design Environment, ADE, setup a parametric plot to sweep the emitter current a. In this case the emitter current was swept from 100nA to 10mA 6. Run Parametric Analysis 7. Plot the collector current and the ft when the analysis completes 8. Use the Y vs Y option to plot the ft vs the collector current Shown below is an example of the ft curves for the NPNupper transistor model used in the rfLib. The ft was measured for current sweeps using different values of Vbc: 0.5V, 1.0V, and 1.5V. As you can see, increasing the base-collector voltage delays the onset of saturation and allows the transistor to achieve higher ft. Figure 2: ft vs Ic for a fixed Vbc Please let me know if this post was useful, if you have any questions, or comments. Art Schaldenbrand<img src="http://feeds.feedburner.com/~r/cadence/community/blogs/2892/~4/5VGqFC0t0AA" height="1" width="1" alt=""/>https://community.cadence.com/cadence_blogs_8/b/rf/archive/2012/06/12/measuring-bipolar-transistor-ft-with-fixed-base-collector-voltageMeasuring Transistor fmaxhttp://feedproxy.google.com/~r/cadence/community/blogs/2892/~3/zLx4YXsViUM/measuring-transistor-fmaxTue, 07 Dec 2010 19:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1246058Art3/cadence_blogs_8/b/rf/archive/2010/12/07/measuring-transistor-fmax3There were several questions about measuring transistor f max in comments posted to my previous Measuring Transistor f t and Simulating MOS Transistor f t blog posts. So in this posting we will look at simulating transistor s-parameters and device characteristics including f max , noise, and distortion. There are two parts to the characterizing a device -- creating the testbench and performing the measurement. First, we will look at creating a testbench to measure transistor s-parameters. While we can't directly use the f t testbench to measure s-parameters, it will serve as the basis for the s-parameter testbench. The current feedback loop from the f t testbench will be used to define the transistor's dc operating point. Then we will add ports to the testbench in order to measure the transistor's s-parameters. The ports define the reference impedance and the port number for s-parameter analysis. The complexity is that we need to isolate the current feedback to stabilize the dc operating point from the ports used for s-parameter analysis. To isolate the dc and the ac signal paths, the dc paths include shorts and the ac paths include capacitors. The corner frequency of LC network is set low enough so that frequency sweeps can be performed from frequencies as low as 1Hz (see Figure 1). Figure 1: f max Testbench Next, let's talk a little bit about how to perform the f max measurement using Virtuoso Analog Design Environment (ADE). We will use Spectre's s-parameter analysis to simulate the transistor's s-parameters and then calculate f max from the s-parameter data. We will calculate the f max from the s-parameters using Mason's Unilateral Power Gain. Let's look at the process step-by-step. 1) First, we will perform s-parameter analysis. We will start by selecting the input and output ports, in this case port1 and port2. Figure 2: Setting Up s-parameter analysis 2) In order to improve the accuracy of the measurement, we will use 100 points/decade instead of the default value, 20 points/decade. Increasing the number of points reduces the interpolation error when we make the f max measurement using the cross() function. 3) ADE can calculate the Unilateral Power Gain from the device's s-parameters. The Maximum Unilateral Power Gain measurement is available from either of the following options: a. From ADE select R esults --> Direct P lot --> Main Form..., then in the sp analysis section choose Gumx Figure 3: S-parameter Direct Plot b. From ADE select T ools --> C alculator..., then select gumx from RF functions 4) In our case, we will use the ViVA Calculator because we want to know the frequency now that the Unilateral Power Gain is 0dB. This measurement can be done using the cross() function. In this case, we have saved Maximum Unilateral Power Gain and the f max measurement, and the cross(dB10(Gumx() 0 1 "falling" nil nil) as outputs in ADE. Figure 4: ADE with f max measurement 5) If you have ever done the measurement in the lab, you probably did not measure the 0dB crossing -- you extrapolated from a higher level to the 0dB crossing due to measurement noise. Simulating f max is different than measuring f max and as a result, when simulating, we can directly measure f max . We do not need to extrapolate to estimate the 0dB crossing as you would in the lab. 6) On the other hand, the accuracy of the f max simulation is affected by how well you model the actual device. For example, using a BSIM4 model with gate resistance, substrate resistance, ... Once the simulation is complete we can begin to measure the f max from the G umx gain plot (see Figure 5). Figure 5: Calculating f max from G umx Using ADE's Parametric Plotting function (see the Measure Twice, Cut Once post for details) we can sweep the operating conditions and see the effect on f max (see Figure 6). Designers can use this information to optimize the speed/performance of their design. Figure 6: f max vs. collector current To review, in this post we have looked at how to simulate the f max of a transistor. This testbench and methodology is based on s-parameter simulation. Any transistor parameter that you might wish to measure using s-parameters can be simulated -- for example, noise figure or IIP3. I hope you found this post useful. Please let me know if you have any questions. Best Regards, Art Schaldenbrand<img src="http://feeds.feedburner.com/~r/cadence/community/blogs/2892/~4/zLx4YXsViUM" height="1" width="1" alt=""/>https://community.cadence.com/cadence_blogs_8/b/rf/archive/2010/12/07/measuring-transistor-fmaxMeasure Twice, Cut Once for Transistor fthttp://feedproxy.google.com/~r/cadence/community/blogs/2892/~3/0dO_jNht70U/measure-twice-cut-onceWed, 06 Oct 2010 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1179380Art3/cadence_blogs_8/b/rf/archive/2010/10/06/measure-twice-cut-once2Recently there was an inquiry about the methodology for performing the f t (transition frequency) versus Ic measurement described in my Measuring Transistor f t blog post from July 2008: By bid75 on September 8, 2010 I am unable to understand how ft vs. Ic plot is generated. How do you do a nested sweep of dc bias current and ac analysis to determine ft at each bias current? Initially, I was just going to fire off a quick response. However, after thinking about the question, it seemed like a topic that needed to be explored in more detail. So you are going to get this appended posting (and a really cool title). In answer to the question, the tool that performs the nested sweep is the parametric analysis in Virtuoso Analog Design Environment -- specifically, it's a feature of ADE-L. I think that parametric analysis is a useful tool and hopefully after reading this posting you will too. In this case, parametric analysis will be used to perform a nested sweep, sweeping the f t measurement across bias current. Remember that the f t measurement includes a frequency sweep. Parametric analysis is also useful for performing a what-if analysis to better understand design trade-offs. To enable parametric analysis in ADE, select T ools --> P arametric Analysis ... and the Parametric Analysis window will open, assuming you are using the Wilson current mirror based testbench. 1) Select the variable to sweep, I CE 2) Select the variable sweep, from X A [1µA] to Y A [10mA] with Z [3] steps / decade Note: You will need to adjust the range based on the device that you are analyzing 3) To run the analysis, click on the green arrow 4) When the simulation is complete plot the results, f t and Ic Note: You will need to change the X-axis variable from the swept variable I CE to collector current, Ic Figure 1: Parametric Analysis Setup Measuring f t is a simple application of parametric analysis. Next, let's look at some other applications. First, we will look at one common challenge designers face as power supply voltages scale down -- understanding the input common mode range of their designs. Different people have different figures of merit for the input common mode range of an operational amplifier. Here we will define the input common-mode range as the input common levels that the dc (maximum) value of the open-loop gain falls by 3dB from the peak value (see figure 2). Parametric analysis makes it easy to visualize the input common-mode range of the amplifier. Not only can we measure the values, we also get a qualitative feel for the how much margin we have before the amplifier fails. Figure 2: Parametric Analysis Results for Input Common-Mode Range Lastly, we will apply parametric analysis to a more complex measurement. Suppose that you would like to understand the limits of the dynamic performance of an A/D Converter-- for example, measure the Effective Resolution Bandwidth, ERBW. The Effective Resolution Bandwidth is the input frequency at which the SINAD at full scale falls by 3dB compared to the SINAD at dc. It is a useful figure of merit to measure the conversion bandwidth of an A/D Converter. Shown in figure 3 is an example of simulating the Effective Resolution Bandwidth of a five bit A/D Converter. By nesting this sweep inside of other sweeps, we can analyze the effect of circuit operating conditions on circuit performance -- for example, the effect of power supply voltage or temperature variations on the bandwidth of an A/D Converter. One comment is that you need to properly parameterize your testbench and the appropriate sweep variable when using parametric analysis. We will save the discussion of how to properly parameterize a testbench for another posting. Figure 3: Flash ADC SINAD as a function of frequency So the summary is that you can use parametric analysis to perform the nested sweep for analyzing f t . However, as we have discussed, there are many other applications of parametric analysis. Hope this posting was useful. As always, please let me know if you have any questions or comments! Best Regards, Art Schaldenbrand<img src="http://feeds.feedburner.com/~r/cadence/community/blogs/2892/~4/0dO_jNht70U" height="1" width="1" alt=""/>https://community.cadence.com/cadence_blogs_8/b/rf/archive/2010/10/06/measure-twice-cut-onceAnalyzing Distortion With Spectre RFhttp://feedproxy.google.com/~r/cadence/community/blogs/2892/~3/zUwUdjN3kOQ/analyzing-distortion-with-spectre-rfFri, 18 Dec 2009 15:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:24074Art3/cadence_blogs_8/b/rf/archive/2009/12/18/analyzing-distortion-with-spectre-rf5Greetings, In the previous appends, we looked at using Shooting Newton Periodic Steady-State analysis to analyze analog circuits. In this append, we will look at using Harmonic Balance Periodic Steady-State, HBPSS, to analyze analog circuits. HBPSS is widely used for RF and microwave circuit design. However, designers often do not realize that it can also be useful for analog circuit design, in particular, when they would like to analyze distortion. As an example, we will simulate the Total Harmonic Distortion, THD, of an amplifier. We will compare and contrast using transient analysis with the Fourier transform and using HBPSS to analyze distortion. The test circuit is a simple Audio Amplifier for headphones built from an LM386 op-amp, shown in Figure 1. Figure 1: LM386 Audio Amplifier Typically, transient analysis with the Fourier transform is used to simulate the THD of an audio amplifier. The challenge with using transient analysis is to optimize the transient analysis simulation configuration for accurate Fourier analysis[1]. Fourier analysis requires that the circuit has reached sinusoidal steady-state, that is, we need to measure the response after the start-up transient of the system has completed settling. Achieving sinusoidal steady-state can require settling for many periods in audio designs because of the large time constants due to the large off-chip capacitors for dc blocking. Of course performing Fourier analysis can alter the spectrum of the amplifier unless designers are careful with their simulation and Fourier analysis setup. To illustrate the limitations of Fourier analysis and the benefit of steady-state analysis for this application, the several simulations were run. In each case the THD was calculated for one period of the fundamental frequency, in this case 1kHz. Four transient simulations were performed with different amounts of delay allowed to settle the start-up transients of the circuit before performing the Fourier analysis. The delay times were: 0 periods of the fundamental frequency, 1 period of the fundamental frequency, 3 periods of the fundamental frequency, and 10 periods of the fundamental frequency. The THD for each simulation condition is shown is Table I. In this case, the simulation is performed using the Spectre's conservative error preset. The conversion from the time domain to the frequency domain was performed using the ViVA Waveform Calculator FFT function and the Spectre Fourier Integral. Table 1: THD Results for Various Simulation Conditions Some observations about the simulation results, As expected, the simulated THD is sensitive to the delay time. The longer the delay time the closer the amplifier is to sinusoidal state and the more accurate the Fourier analysis. After about 10 periods, the amplifier has reached sinusoidal steady-state and the results for the Fourier Integral and FFT are consistent with HB PSS analysis. In this case, the HBPSS analysis was performed based on the dc operating point of the circuit, transient-assisted harmonic balance analysis was not required. For this simple example, the simulation time using harmonic balance PSS analysis is >5x faster than using transient analysis with the Fourier Transform. As circuit become larger and especially for post-layout simulations, we would expect to see that the difference in the transient analysis time and the dc operating point calculation become larger and HBPSS becomes even more effective. Reducing simulation enables designers to analyze THD across process variations, with corner and Monte Carlo analysis, or to optimize THD. One question maybe why didn't we use Shooting Newton for the periodic steady-state analysis? The short answer is that Shooting Newton is not required in this case. Harmonic Balance analysis provides the steady state solution in terms of finite Fourier series and is very effective for simulating distortion. If time domain waveforms were more non-linear, for example, when simulating a Switched Capacitor circuit or a DC-to-DC Converter then Shooting Newton would be appropriate. To help illustrate the need to settle the initial start-up transient, I have plotted the non-periodicity, on of the outputs of the Spectre's Fourier Integral analysis, as a function of settling time, see Figure 2. The non-periodicity measures the difference between the initial value and final value. When the response is in sinusoidal steady-state the non-periodicity will be 0. Figure 2: Effect of Settling Time on Periodicity This approach, using harmonic balance analysis for periodic steady-state analysis to supplement transient analysis with the FFT, can be applied whenever you need to measure the distortion of a linear amplifier. In the next append, we will look at extending this approach to using PSS for distortion analysis of non-linear circuits, for example. Hope you found this append useful, please let me know! Art Schaldenbrand<img src="http://feeds.feedburner.com/~r/cadence/community/blogs/2892/~4/zUwUdjN3kOQ" height="1" width="1" alt=""/>noGreetings, In the previous appends, we looked at using Shooting Newton Periodic Steady-State analysis to analyze analog circuits. In this append, we will look at using Harmonic Balance Periodic Steady-State, HBPSS, to analyze analog circuits. HBPSS is widGreetings, In the previous appends, we looked at using Shooting Newton Periodic Steady-State analysis to analyze analog circuits. In this append, we will look at using Harmonic Balance Periodic Steady-State, HBPSS, to analyze analog circuits. HBPSS is widely used for RF and microwave circuit design. However, designers often do not realize that it can also be useful for analog circuit design, in particular, when they would like to analyze distortion. As an example, we will simulate the Total Harmonic Distortion, THD, of an amplifier. We will compare and contrast using transient analysis with the Fourier transform and using HBPSS to analyze distortion. The test circuit is a simple Audio Amplifier for headphones built from an LM386 op-amp, shown in Figure 1. Figure 1: LM386 Audio Amplifier Typically, transient analysis with the Fourier transform is used to simulate the THD of an audio amplifier. The challenge with using transient analysis is to optimize the transient analysis simulation configuration for accurate Fourier analysis[1]. Fourier analysis requires that the circuit has reached sinusoidal steady-state, that is, we need to measure the response after the start-up transient of the system has completed settling. Achieving sinusoidal steady-state can require settling for many periods in audio designs because of the large time constants due to the large off-chip capacitors for dc blocking. Of course performing Fourier analysis can alter the spectrum of the amplifier unless designers are careful with their simulation and Fourier analysis setup. To illustrate the limitations of Fourier analysis and the benefit of steady-state analysis for this application, the several simulations were run. In each case the THD was calculated for one period of the fundamental frequency, in this case 1kHz. Four transient simulations were performed with different amounts of delay allowed to settle the start-up transients of the circuit before performing the Fourier analysis. The delay times were: 0 periods of the fundamental frequency, 1 period of the fundamental frequency, 3 periods of the fundamental frequency, and 10 periods of the fundamental frequency. The THD for each simulation condition is shown is Table I. In this case, the simulation is performed using the Spectre's conservative error preset. The conversion from the time domain to the frequency domain was performed using the ViVA Waveform Calculator FFT function and the Spectre Fourier Integral. Table 1: THD Results for Various Simulation Conditions Some observations about the simulation results, As expected, the simulated THD is sensitive to the delay time. The longer the delay time the closer the amplifier is to sinusoidal state and the more accurate the Fourier analysis. After about 10 periods, the amplifier has reached sinusoidal steady-state and the results for the Fourier Integral and FFT are consistent with HB PSS analysis. In this case, the HBPSS analysis was performed based on the dc operating point of the circuit, transient-assisted harmonic balance analysis was not required. For this simple example, the simulation time using harmonic balance PSS analysis is >5x faster than using transient analysis with the Fourier Transform. As circuit become larger and especially for post-layout simulations, we would expect to see that the difference in the transient analysis time and the dc operating point calculation become larger and HBPSS becomes even more effective. Reducing simulation enables designers to analyze THD across process variations, with corner and Monte Carlo analysis, or to optimize THD. One question maybe why didn't we use Shooting Newton for the periodic steady-state analysis? The short answer is that Shooting Newton is not required in this case. Harmonic Balance analysis provides the steady state solution in terms of finite Fourier series and is very effective for simulating distortion. If time domain waveforms were more non-linear, for example, when simulatinhttps://community.cadence.com/cadence_blogs_8/b/rf/archive/2009/12/18/analyzing-distortion-with-spectre-rfnonadult