Arthur Schaldenbrand Blog

Measuring Bipolar Transistor ft with Fixed Base-Collector Voltage

Art3 — Tue, 12 Jun 2012 15:54:00 GMT

Recently I had a question from reader. He asked a good question: "How do you to measure a bipolar transistor's ft when the base-collector voltage, Vbc, is fixed?" Attached is a modified version of the testbench that allows a user to measure ft with a fixed Vbc. While the aesthetics are not as pleasing as the original testbench, it does the job.

The testbench is shown in Figure 1. The base of the bipolar transistor, the DUT, is grounded. The collector of the transistor is connected to a dc source, VBC, which is used to set the base-collector voltage of the transistor. The emitter is connected to a current source that sets the bias current, IE. An additional supply, VBE, is included to assure the base-emitter junction is always forward biased. For these tests, the dummy power supply voltage, VBE, is set to 5V.

Figure 1: Ft Testbench modified for fixed Vbc

To measure the ft, use the same methodology previously described:

1. Run a dc operating point analysis and save the collector current

2. Run an ac analysis, sweep the frequency beyond the maximum value of ft

a. In this case, the ac sweep was from 1Hz to 10GHz

b. Save the base and collector currents

3. Use the Virtuoso ViVA waveform calculator to measure the ac beta of the transistor

a. The ac beta is ic/ib, where ic and ib are the ac currents

4. Use the Virtuoso ViVA waveform calculator cross() function to measure the ft

a. Measure the frequency where the value of the ac beta=1, or 0dB

5. In Virtuoso Analog Design Environment, ADE, setup a parametric plot to sweep the emitter current

a. In this case the emitter current was swept from 100nA to 10mA

6. Run Parametric Analysis

7. Plot the collector current and the ft when the analysis completes

8. Use the Y vs Y option to plot the ft vs the collector current

Shown below is an example of the ft curves for the NPNupper transistor model used in the rfLib. The ft was measured for current sweeps using different values of Vbc: 0.5V, 1.0V, and 1.5V. As you can see, increasing the base-collector voltage delays the onset of saturation and allows the transistor to achieve higher ft.

Figure 2: ft vs Ic for a fixed Vbc

Please let me know if this post was useful, if you have any questions, or comments.

Art Schaldenbrand

Measuring Fmax for MOS Transistors

Art3 — Thu, 11 Aug 2011 15:00:00 GMT

The following question has come up in comments: "How do I measure F_max for an MOS transistor?" The measurement methodology -- testbench, analysis, calculator setup, stimulus, etc.-- does not change whether you are measuring bipolar transistors or MOS transistors. On the other hand, the results for MOS transistors often come out looking wrong, or more correctly, non-physical.

Before scratching your head, adjusting your testbench or doing anything else, you need to consider the model that you are using. For review the fmax testbench is shown below. The testbench has two control loops -- a dc control loop that controls the drain current, and an ac loop that for measuring the s-parameters of the transistor. The control loops are isolated using inductors (dc short, ac open) and capacitors (dc open, ac short). You could use analysis-dependent switches in place of the inductors and capacitors if you prefer.

Figure 1: Fmax Testbench

Using this testbench, let's explore some different approaches to modeling a MOS transistor and see what happens. We will look at three different device modeling approaches:

1) Using the standard bsim3v3 model

2) Using the standard bsim3v3 model with RF extensions. The BSIM3v3 model does not account for the extrinsic elements of the MOS transistor that can affect the RF performance of the transistor, for example, the resistance of the gate, the substrate resistance, etc.

3) Use the bsim4 model. The bsim4 model includes the extrinsic components within the model.

We won't discuss the details of device modeling in this blog, if you are interested, you can find more information in the reference[1]. Please note that approach 2 and approach 3 are equivalent methods of implementing the model extensions discussed in the reference.

To compare the models, we will start by simulating the maximum unilateral gain in order to find the F_max, The results are shown in Figure 2 below. Let's look at what the simulation results are telling us about the transistor models. The results for the default bsim3v3 model look non-physical since the maximum unilateral gain has large peaks in the response at frequencies above 10GHz and the response does not roll off until almost 100GHz. However, both the bsim3v3 with RF extensions and the bsim4 model show the results we would expect, the gain is flat at low frequencies and rolls-off at high frequencies.

One additional comment about the simulation results. Due to some PDK limitations, the bsim3v3 models are from a 180nm feature size PDK, while the bsim4 data is from a 45nm feature size PDK. So the simulated F_max is different due to process scaling and not due to differences in the modeling approach. For devices from the same PDK modeled using the two approaches, the F_max should be consistent.

Figure 2: Comparing the Maximum Unilateral Gain

In previous blog posts, we have discussed the good things that simulation allows you to do, that is, perform measurements that you cannot perform in the real world. Idealizing testbench behavior or, more correctly, including exactly the phenomena that the designer specifies, is good when creating testbenches. The simulation will ignore all the higher order phenomena that degrade measurement accuracy.

So, for example, we can measure f_t directly in simulation instead of extracting it from s-parameters as we would have to do if we tried to measure it in the lab. On the other hand, simulation also ignores all the higher order device behavior that designers do not specify. As a result, effects that can degrade design performance are ignored.

The solution is to improve model fidelity, which will also increase model complexity and simulation time. So designers need to make a trade-off between how accurately to model a transistor's characteristics and their objectives when simulating. While an RF designer may want to use RF models, not everybody needs them. For example, if you are designing a Band-Gap Reference, then you probably don't need to use an RF model; you are more interested in modeling the effect of process variation on the circuit.

In summary, simulating the F_max of a MOS transistor is similar to simulating the F_max of a bipolar transistor. As we discussed, you can use the testbench to perform sanity checks on your models to verify that they are appropriate for your application or select the best component from the PDK for your application. You can also use the testbench to optimize the performance for your operating conditions, that is, trade-off gate length and gate width to give the best F_max or Noise Figure for the given bias conditions.

Best Regards,

Art Schaldenbrand

References:

[1] BSIM4v4.7 MOSFET Model User's Manual, Morshed et al., Chapter 9, High Speed/RF Models, page
75-84 http://www-device.eecs.berkeley.edu/~bsim3/BSIM4/BSIM470/BSIM470_Manual.pdf

Measuring Transistor fmax

Art3 — Tue, 07 Dec 2010 22:00:00 GMT

There were several questions about measuring transistor f_max in comments posted to my previous Measuring Transistor f_t and Simulating MOS Transistor f_t blog posts. So in this posting we will look at simulating transistor s-parameters and device characteristics including f_max, noise, and distortion. There are two parts to the characterizing a device -- creating the testbench and performing the measurement.

First, we will look at creating a testbench to measure transistor s-parameters. While we can't directly use the f_t testbench to measure s-parameters, it will serve as the basis for the s-parameter testbench. The current feedback loop from the f_t testbench will be used to define the transistor's dc operating point. Then we will add ports to the testbench in order to measure the transistor's s-parameters. The ports define the reference impedance and the port number for s-parameter analysis. The complexity is that we need to isolate the current feedback to stabilize the dc operating point from the ports used for s-parameter analysis. To isolate the dc and the ac signal paths, the dc paths include shorts and the ac paths include capacitors. The corner frequency of LC network is set low enough so that frequency sweeps can be performed from frequencies as low as 1Hz (see Figure 1).

Figure 1: f_max Testbench

Next, let's talk a little bit about how to perform the f_max measurement using Virtuoso Analog Design Environment (ADE). We will use Spectre's s-parameter analysis to simulate the transistor's s-parameters and then calculate f_max from the s-parameter data. We will calculate the f_max from the s-parameters using Mason's Unilateral Power Gain. Let's look at the process step-by-step.

1) First, we will perform s-parameter analysis. We will start by selecting the input and output ports, in this case port1 and port2.

Figure 2: Setting Up s-parameter analysis

2) In order to improve the accuracy of the measurement, we will use 100 points/decade instead of the default value, 20 points/decade. Increasing the number of points reduces the interpolation error when we make the f_max measurement using the cross() function.

3) ADE can calculate the Unilateral Power Gain from the device's s-parameters. The Maximum Unilateral Power Gain measurement is available from either of the following options:

a. From ADE select Results --> Direct Plot --> Main Form..., then in the sp analysis section choose Gumx

Figure 3: S-parameter Direct Plot

b. From ADE select Tools --> Calculator..., then select gumx from RF functions

4) In our case, we will use the ViVA Calculator because we want to know the frequency now that the Unilateral Power Gain is 0dB. This measurement can be done using the cross() function. In this case, we have saved Maximum Unilateral Power Gain and the f_max measurement, and the cross(dB10(Gumx() 0 1 "falling" nil nil) as outputs in ADE.

Figure 4: ADE with f_max measurement

5) If you have ever done the measurement in the lab, you probably did not measure the 0dB crossing -- you extrapolated from a higher level to the 0dB crossing due to measurement noise. Simulating f_max is different than measuring f_max and as a result, when simulating, we can directly measure f_max. We do not need to extrapolate to estimate the 0dB crossing as you would in the lab.

6) On the other hand, the accuracy of the f_max simulation is affected by how well you model the actual device. For example, using a BSIM4 model with gate resistance, substrate resistance, ...

Once the simulation is complete we can begin to measure the f_max from the G_umx gain plot (see Figure 5).

Figure 5: Calculating f_max from G_umx

Using ADE's Parametric Plotting function (see the Measure Twice, Cut Once post for details) we can sweep the operating conditions and see the effect on f_max (see Figure 6). Designers can use this information to optimize the speed/performance of their design.

Figure 6: f_max vs. collector current

To review, in this post we have looked at how to simulate the f_max of a transistor. This testbench and methodology is based on s-parameter simulation. Any transistor parameter that you might wish to measure using s-parameters can be simulated -- for example, noise figure or IIP3.

I hope you found this post useful. Please let me know if you have any questions.

Best Regards,

Art Schaldenbrand

Measure Twice, Cut Once for Transistor ft

Art3 — Wed, 06 Oct 2010 16:00:00 GMT

Recently there was an inquiry about the methodology for performing the f_t (transition frequency) versus Ic measurement described in my Measuring Transistor f_t blog post from July 2008:

By bid75 on September 8, 2010
I am unable to understand how ft vs. Ic plot is generated. How do you do a nested sweep of dc bias current and ac analysis to determine ft at each bias current?

Initially, I was just going to fire off a quick response. However, after thinking about the question, it seemed like a topic that needed to be explored in more detail. So you are going to get this appended posting (and a really cool title). In answer to the question, the tool that performs the nested sweep is the parametric analysis in Virtuoso Analog Design Environment -- specifically, it's a feature of ADE-L. I think that parametric analysis is a useful tool and hopefully after reading this posting you will too.

In this case, parametric analysis will be used to perform a nested sweep, sweeping the f_t measurement across bias current. Remember that the f_t measurement includes a frequency sweep. Parametric analysis is also useful for performing a what-if analysis to better understand design trade-offs. To enable parametric analysis in ADE, select Tools --> Parametric Analysis ... and the Parametric Analysis window will open, assuming you are using the Wilson current mirror based testbench.

1) Select the variable to sweep, I_CE

2) Select the variable sweep, from X A [1µA] to Y A [10mA] with Z [3] steps / decade
Note: You will need to adjust the range based on the device that you are analyzing

3) To run the analysis, click on the green arrow

4) When the simulation is complete plot the results, f_t and Ic
Note: You will need to change the X-axis variable from the swept variable I_CE to collector current, Ic

Figure 1: Parametric Analysis Setup

Measuring f_t is a simple application of parametric analysis. Next, let's look at some other applications. First, we will look at one common challenge designers face as power supply voltages scale down -- understanding the input common mode range of their designs. Different people have different figures of merit for the input common mode range of an operational amplifier. Here we will define the input common-mode range as the input common levels that the dc (maximum) value of the open-loop gain falls by 3dB from the peak value (see figure 2). Parametric analysis makes it easy to visualize the input common-mode range of the amplifier. Not only can we measure the values, we also get a qualitative feel for the how much margin we have before the amplifier fails.

Figure 2: Parametric Analysis Results for Input Common-Mode Range

Lastly, we will apply parametric analysis to a more complex measurement. Suppose that you would like to understand the limits of the dynamic performance of an A/D Converter-- for example, measure the Effective Resolution Bandwidth, ERBW. The Effective Resolution Bandwidth is the input frequency at which the SINAD at full scale falls by 3dB compared to the SINAD at dc. It is a useful figure of merit to measure the conversion bandwidth of an A/D Converter. Shown in figure 3 is an example of simulating the Effective Resolution Bandwidth of a five bit A/D Converter. By nesting this sweep inside of other sweeps, we can analyze the effect of circuit operating conditions on circuit performance -- for example, the effect of power supply voltage or temperature variations on the bandwidth of an A/D Converter. One comment is that you need to properly parameterize your testbench and the appropriate sweep variable when using parametric analysis. We will save the discussion of how to properly parameterize a testbench for another posting.

Figure 3: Flash ADC SINAD as a function of frequency

So the summary is that you can use parametric analysis to perform the nested sweep for analyzing f_t. However, as we have discussed, there are many other applications of parametric analysis. Hope this posting was useful. As always, please let me know if you have any questions or comments!

Best Regards,

Art Schaldenbrand

Analyzing Distortion With Spectre RF

Art3 — Fri, 18 Dec 2009 18:30:00 GMT

Greetings,

In the previous appends, we looked at using Shooting Newton Periodic Steady-State analysis to analyze analog circuits. In this append, we will look at using Harmonic Balance Periodic Steady-State, HBPSS, to analyze analog circuits. HBPSS is widely used for RF and microwave circuit design. However, designers often do not realize that it can also be useful for analog circuit design, in particular, when they would like to analyze distortion. As an example, we will simulate the Total Harmonic Distortion, THD, of an amplifier. We will compare and contrast using transient analysis with the Fourier transform and using HBPSS to analyze distortion. The test circuit is a simple Audio Amplifier for headphones built from an LM386 op-amp, shown in Figure 1.

Figure 1: LM386 Audio Amplifier

Typically, transient analysis with the Fourier transform is used to simulate the THD of an audio amplifier. The challenge with using transient analysis is to optimize the transient analysis simulation configuration for accurate Fourier analysis[1]. Fourier analysis requires that the circuit has reached sinusoidal steady-state, that is, we need to measure the response after the start-up transient of the system has completed settling. Achieving sinusoidal steady-state can require settling for many periods in audio designs because of the large time constants due to the large off-chip capacitors for dc blocking. Of course performing Fourier analysis can alter the spectrum of the amplifier unless designers are careful with their simulation and Fourier analysis setup.

To illustrate the limitations of Fourier analysis and the benefit of steady-state analysis for this application, the several simulations were run. In each case the THD was calculated for one period of the fundamental frequency, in this case 1kHz. Four transient simulations were performed with different amounts of delay allowed to settle the start-up transients of the circuit before performing the Fourier analysis. The delay times were: 0 periods of the fundamental frequency, 1 period of the fundamental frequency, 3 periods of the fundamental frequency, and 10 periods of the fundamental frequency. The THD for each simulation condition is shown is Table I. In this case, the simulation is performed using the Spectre's conservative error preset. The conversion from the time domain to the frequency domain was performed using the ViVA Waveform Calculator FFT function and the Spectre Fourier Integral.

Table 1: THD Results for Various Simulation Conditions

Some observations about the simulation results,

As expected, the simulated THD is sensitive to the delay time. The longer the delay time the closer the amplifier is to sinusoidal state and the more accurate the Fourier analysis.
After about 10 periods, the amplifier has reached sinusoidal steady-state and the results for the Fourier Integral and FFT are consistent with HB PSS analysis.
In this case, the HBPSS analysis was performed based on the dc operating point of the circuit, transient-assisted harmonic balance analysis was not required.

For this simple example, the simulation time using harmonic balance PSS analysis is >5x faster than using transient analysis with the Fourier Transform. As circuit become larger and especially for post-layout simulations, we would expect to see that the difference in the transient analysis time and the dc operating point calculation become larger and HBPSS becomes even more effective. Reducing simulation enables designers to analyze THD across process variations, with corner and Monte Carlo analysis, or to optimize THD.

One question maybe why didn't we use Shooting Newton for the periodic steady-state analysis? The short answer is that Shooting Newton is not required in this case. Harmonic Balance analysis provides the steady state solution in terms of finite Fourier series and is very effective for simulating distortion. If time domain waveforms were more non-linear, for example, when simulating a Switched Capacitor circuit or a DC-to-DC Converter then Shooting Newton would be appropriate.

To help illustrate the need to settle the initial start-up transient, I have plotted the non-periodicity, on of the outputs of the Spectre's Fourier Integral analysis, as a function of settling time, see Figure 2. The non-periodicity measures the difference between the initial value and final value. When the response is in sinusoidal steady-state the non-periodicity will be 0.

Figure 2: Effect of Settling Time on Periodicity

This approach, using harmonic balance analysis for periodic steady-state analysis to supplement transient analysis with the FFT, can be applied whenever you need to measure the distortion of a linear amplifier. In the next append, we will look at extending this approach to using PSS for distortion analysis of non-linear circuits, for example.

Hope you found this append useful, please let me know!

Art Schaldenbrand

Periodic Steady-State Analysis for DC-to-DC Converters

Art3 — Tue, 30 Jun 2009 14:30:00 GMT

In "Spectre RF by any other name ...", a non-RF application for Spectre RF's periodic steady-state analysis was introduced. An example of using periodic steady-state analysis [PSS] to simulate the dynamic performance: THD and SFDR, of a switched-current Digital-to-Analog Converter [DAC] was presented. In this append, we will look at using periodic steady-state analysis for another non-RF application, switching regulator simulation. Switching regulators are the core of switched-mode power supplies [SMPS] and are interesting because they are used in most power supplies, including the high efficiency power supplies required mobile applications.

Let's begin by considering a simple switching regulator design, a buck-down converter for converting from 12V to 5V, shown in Figure 1. The design is a voltage-mode, continuous conduction mode switching regulator. The control block: reference voltage generator, error amplifier and compensation, drives a pulse-width modulator: ramp generator, comparator, and switch. The output of the switch is filtered by an LC tank and feedback to the control block. The duty cycle of the pulse-width modulator determines the output voltage of the regulator. The inductor and capacitor non-idealities [self-resonance frequency, ESR, ...] are modeled but not shown. Finally an EMI filter has been included in the design.

Figure 1: Buck-Down Converter schematic

First, let's look at the dynamic response of the regulator. After settling the start-up transient, the regulator operates at the frequency of the ramp generator. When operating at steady-state, the dc level is 5.002V and there is ripple on the regulated output voltage, ~+/-7mV. The transient response of the regulator is shown in figure 2.

Figure 2: Buck-Down Converter transient response

While transient analysis can be used to verify the overall performance of the circuit, it is difficult to analyze the circuit's performance in the time domain using transient analysis, for example, consider the challenge of trying to simulate the phase margin and gain margin of the control loop. Ideally we would like to be able to use simulation to improve the buck-down converter design in the same way that using ac, noise, stability analysis can be used for design of linear circuits. However, linear analysis can not be directly applied to switching regulator designs so we need to find a new methodology for analyzing the switching regulator. Since the switching regulator has a periodic steady-state, we will apply the periodic steady-state analysis technology in Spectre RF. In this case, a source is used to generate the ramp so driven periodic steady-state analysis is used. The complete setup for PSS analysis is shown in Figure 3.

Figure SEQ 3: PSS Analysis setup

Since a switching regulator has fast changing time domain waveforms, the Shooting Newton [time domain] periodic steady-state engine was selected. If the Harmonic Balance engine is used, then a large number of tones would need to be selected in order to correctly represent the voltage at the output of the comparator and the switch output since these waveforms are nearly square waves. In this case, the stabilization time [tstab] is equal to the transient simulation time. In practice, a shorter stabilization time would be used to reduce simulation time. Allowing the circuit to settle to close to steady-state will help convergence. For this test example using a tstab of 2-3us should be sufficient.

Figure 4: Buck-Down Converter periodic steady-state response

The plots for periodic steady-state response show the switch drive signal, net015 [0-12V], the output of the Switch, Switcher Output [-0.8V-12V], the buck converter output after the LC tank, Regulated Output [4.995V-5.009V]. Plots of the transient and periodic steady-state response match if overlayed and the average output from transient analysis and periodic steady-state analysis are consistent, 5.002V. In the next append, we will look at performing periodic small signal analysis to analyze the converters performance. If you have any questions about this append or would like more information, please let me know!

Arthur Schaldenbrand

Spectre RF By Any Other Name ...

Art3 — Wed, 22 Apr 2009 13:00:00 GMT

It has been a while since I last appende d, hope you are well!

It was a little bit difficult to come up with a subject to write about and then recently I was in a meeting where we were talking about transient noise analysis. A designer was discussing the issue of analyzing the noise of a Pipeline ADC as an example of how they use the transient noise. The conversation started me to wondering whether or not this might be a good application for Spectre RF. After all, Spectre RF PNOISE analysis can be used to analyze the noise of Sample and Hold in the Pipeline ADC. Since then I have been spent some time exploring how to use Spectre RF to analyze data conversion circuits. The experience has reminded me of the the versatility of Spectre RF's periodic steady-state and noise analysis in analyzing complex problems. Shown in Figure 1 is an example of the periodic steady-state results for an 8bit current output Digital-to-Analog Converter, DAC. The periodic steady-state analysis results can be used to measure the SFDR and THD for the DAC.

Figure 1: PSS Results for an 8-Bit Switched Current DAC

So back to the title, what is in a name? I have been using Spectre RF for more than 10 years and have often used Spectre "RF" for unusual applications, for example, analyzing switched-mode power supply designs. Yet this was first time I have seriously looked at Spectre RF for data converters. I too had fallen into the trap of thinking that Spectre "RF" is for "RF" circuits. In the next append, we will look further into simulating data converters with Spectre RF. In the meantime, it would be good to hear from you, have you ever used Spectre RF for non-RF applications?

Art Shaldenbrand

Simulating MOS Transistor ft

Art3 — Sat, 09 Aug 2008 07:25:00 GMT

One other question that you might ask is, this approach works for bipolars but what happens when you need to characterize a MOS transistor. Nothing changes, use the same testbench and measurements, see figure 1. In this testbench a MOS transistor is being compared to a bipolar transistor.

Figure 1: MOS and BJT Comparison

The simulation results are shown in Figure 2. The difference in the results is that the low frequency bipolar transistors current gain is limited by the base current, while the MOS transistor current gain is not limited. Note, in advanced node processes, MOS transistors do have significant gate leakage and the plot for the MOS transistor would look more like the plot for the bipolar transistor.

Figure 2: Comparison of current gain

So the same techniques that you would to characterize a bipolar transistor and also be applied to MOS transistor.

Measuring Transistor ft

Art3 — Wed, 16 Jul 2008 13:30:00 GMT

So let’s consider a practical example of creating test benches and performing measurements, starting with how to characterize a transistor. A couple of questions to consider before starting are:

What parameters do you want to measure?
What types of test benches are required to measure these parameters?

Let’s start by considering how to measure the ft of a transistor, ft is a standard figure of merit used by analog designers to evaluate a transistor’s performance. Later we will consider how to measure some other common transistor parameters fmax, Noise Figure, as well as, measuring device stability.

First, let’s review the meaning of ft. It is defined as the unity gain frequency of a transistor’s short circuit current gain. The first point is that we need to measure the short circuit current gain so ideally the output terminal, collector [drain] of the transistor will be connected to a power supply. The next point is that we need to calculate the current gain of the transistor. For Virtuoso Analog Design Environment users, the Virtuoso Visualization and Analysis waveform calculator can be used to perform this measurement. To calculate ft, plot the current gain by dividing the collector [drain] current by the base [gate] current and then using the cross function to find the unity gain frequency. An example of calculating ft, is shown in Figure 1.

Figure 1: Measuring Transistor f_t

When creating a simulation test bench the natural place to start is the actual measurement test bench. To measure ft, an RF network analyzer can be used to measure the s-parameters and then the s-parameters can be converted into h-parameters. By plotting the h21, the ft can be estimated by extrapolating the unity gain frequency of the h21. This approach works well in the lab because wideband shorts do not exist in the real world. So RF measurements need to be performed with input and output matching and a result s-parameters are the natural method for characterizing transistors. One issue when testing in the lab is the need to for separate bias and RF sources. Typically these sources are isolated with a bias T. In place of a bias T, we will use an inductor [pass the bias voltage at dc] and a capacitor [pass the RF input at frequency].

Figure 2: Emulating the Network Analyzer Setup to Measure h21

Using the lab test bench introduces some complexity that is not required when performing the measurement in simulation. By taking advantage of the “ideal” nature simulation, the test bench can be simplified. In simulation, we can create a perfect short using a voltage source. The voltage source provides bias and acts as a short circuit replacing the output matching circuitry in the original test bench. The RF input has been replaced by a current source with ac magnitude of 1 so the current gain can be directly measured. The input bias is still controlled by setting a dc voltage, see
Figure 3. This test bench works well when measuring ft for a single bias condition. However, it is difficult to sweep the bias current of the transistor as can be done in the lab with a bias generator.

Figure 3: Enhanced Test bench with an Output Short

The next enhancement is to replace the bias voltage source and resistor with a diode connected transistor and a current source to set the bias current of the device under test [DUT], see Figure 4. Using a diode connected transistor to generate the bias voltage allows the bias current to be easily controlled. The dc bias and the RF input are still isolated by the pseudo bias T. This change to the test bench allows a designer to characterize the effect of bias current on ft so the transistor can be operated at its maximum ft.

Figure 4: Improved ft Testbench

Another enhancement to the test bench would be to replace the inductor and the capacitor used in the pseudo bias-T, shown in Figure 5. Virtuoso Spectre simulator provides users analysis dependent switches that can be set to open and closed depending on the analysis to be performed. This allows the designer to use the same test bench to perform multiple tests, for example, NF, fmax, etc.

Figure 5: Using analysis dependent switches

The test bench I use to measure ft is even simpler, the the bias network [diode, analysis dependent switches, and RF source] is replaced by an ideal current mirror. The current mirror provides feedback to stabilize the bias point. The current source that sets the bias current is also RF input source the bias T is eliminated. BTW, you might recognize this type of circuit, it is called a Wilson current mirror, shown in Figure 6.

Figure 6: My ft Test bench
To review the test bench development process, we started by replicating the test bench we used in the lab in simulation. Then the test bench was optimized by tuning it to take advantage the “ideal” nature of a SPICE simulator. Along the way we made several improvement to the measurements process.
1) Directly measured the ft, eliminating the need to generate the s-parameters and then calculate the h-parameters.
2) Added the ability to sweep the bias current so plots of ft vs. Ic can be generated, see Figure 7.

Figure 7: Plot of ft vs. Ic

In closing, I hope that this example of creating a test bench and making measurements will be useful for you. Please let me know what you think.

Best Regards,
Art Schaldenbrand

Senrinotabi

Art3 — Sat, 12 Jul 2008 04:54:00 GMT

Greetings! My name is Art Schaldenbrand and I have been at Cadence for 12 years supporting the custom IC design tools in the Virtuoso platform. My interests tend to be as widely varied as the customers I work with, ranging from Wireless Design to CMOS Image Sensor design and Power Management design.

One common theme that comes up when talking to customers about any aspect of design is the challenge of using simulation to understand their design, from creating testbenches to measuring circuit parameters.

In subsequent appends, I would like to discuss these issues and share ideas with you about how to use simulation more effectively.

- Art