Gerald "Jerry" Grzenia Blog

What's Good About Allegro PCB Editor Net Groups? See for Yourself in 16.6!

Jerry GenPart — Tue, 18 Jun 2013 08:15:00 GMT

Just a brief blog today about a new feature in Allegro PCB Editor.

A new net grouping mechanism has been added in Allegro PCB Editor 16.6 called ‘NET_GROUPS’. Essentially, the Net Group replaces the bus object.

A Net Group is a collection of net objects. Different types of net objects, such as nets, buses, differential pairs, and XNets can be added as members of a Net Group. A net object can be a member of one Net Group only.

A Net Group can be constructed in the Constraint Manager.

If constraints are defined on a Net Group, the constraints are applicable to all members of the Net Group. With the introduction of Net Groups, user-defined collections of net objects are now composed as a Net Group instead of a bus.

The Object Type for the Net Group is 'NGrp':

Please share your usage of Net Groups in Allegro PCB Editor.

Jerry "GenPart" Grzenia

What's Good About RF PCB and Agilent ADS Via Exchange? 16.6 Has Many New Enhancements!

Jerry GenPart — Tue, 11 Jun 2013 14:46:00 GMT

The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that exports to ADS, and also the enhancements for existing layout IFF interface (import and export) to support the generic via exchange.

Layer-to-layer via structures are almost always used in PCB designs. These common structures are not standardized in ADS -- they are represented in several ways. These include instances of via models such as the microstrip VIA2 and as layout-only footprints that define the catch pads and drill holes with simple polygons.

The disconnection between the capabilities of PCB tool via structures, and the equivalent objects in ADS, makes design transfer difficult. A PCB tool via structure must be flattened to simple polygons for transfer to ADS, losing most of the information contained in the original PCB via. Likewise, those simple polygons can be transferred back to the PCB tool, but are not identified as a via structure and not treated as a layer-to-layer connection. ADS does not have the PCB compatible via library, which means there is no padstack definition for a generic PCB via.

To solve the problem, Cadence and Agilent developed a solution -- you can export Allegro generic via padstacks first from the PCB Editor, and then ADS will build a PCB-style via library with the pcbViaLib utility offered in ADS2011.10. Agilent has provided the pcbViaLib design kit, which provides via import utilities and a new ADS component, the pcbVia. This design kit defines a data file format that holds the definition of a PCB-tool style via structure, which is read by the pcbVia component and used with a layout macro to render exactly the same layout footprint in ADS as in the PCB tool.

When you export an Allegro layout design with generic vias to ADS by IFF, you can select export vias as components so all generic vias will be mapped to ADS via components. You can also use the via components in ADS layout and then export the ADS design with the kind of via components by IFF. When importing the design into PCB Editor by IFF, the I/F will automatically map back the ADS via components to Allegro generic via padstacks.

Here is the flow for via management between Allegro PCB Editor and ADS:

Read on for more details …

Export Allegro Generic Via Padstacks to ADS

There is a utility under the RF-PCB to export generic vias for ADS via component creation. You can click RF-PCB > Export Padstacks to ADS:

All vias used in the design will be listed and then you can select some/all vias to export. Please notice only vias in the layout will be listed on the form, so if you want to export a via padstack, you have to place the via into a design. The via group name is for ADS usage. Once you create the via components on the ADS side, you can place a via component in ADS layout from the specific via group.

Note: It’s best to use a unique group name for each design so that ADS will not get confused. The exporting for via padstacks is not based on IFF format but AEL.

Constructing ADS Via Components

You can only get the required utility in ADS2011.10 or later. If you installed the specific design kit (you need to ask for it from Agilent), you will see this menu in ADS layout:

In ADS layout, click PCB Via Utilities > Import Via/Padstack Group… Browse to the proper .ael file exported from Allegro PCB Editor, then you will create the via components:

Export Allegro Design with Generic Vias to ADS by IFF

For a design with generic vias in PCB Editor like the following:

Click RF-PCB > IFF Interface > Export… to get the following dialog:

You can click the More options button, then you can see the Vias tab. Two options are available for via transfer mode. By default, all vias will be considered as components to export. You can still change it to Shape for the exporting as before. You can also RMB click on the header bar to select Change all to components as below:

If you export all vias as components, then all selected generic vias will be written out as via components in IFF file so that ADS can recognize them.

Import Layout IFF with Mapped Via Components into ADS

Make a new workspace in ADS and make sure the PCBVIALIB design kit is in current workspace. To import the design into ADS via IFF, click File > Import… in ADS layout, and then select the Cadence/PCB option, and browse the proper folder for the source files:

You will get the ADS layout will all generic vias converted into ADS via components:

If you double click a via in ADS layout, you will see the details for the via component:

Use Via Components in ADS

Once the via components created in ADS, you can export a layout design with generic vias from Allegro PCB Editor and then import the design into ADS by IFF. The Allegro generic vias can be replaced by ADS via components. Also you may directly use those via components in ADS side. Before you add a via component into the design, you need to know which vias are available. You can click PCB Via Utilities > List Via Groups, all available via names and via groups will be listed:

To add a via component into ADS layout, you can directly enter pcbVia at the following field:

The following dialog will appear:

You may need to change the viaGroupName and viaName and also padTypes. You can get the viaGroupName and viaName by clicking PCB Via Utilities > List Via Groups. For padTypes, you need to manually specify the value.

The meaning of the padTypes is to specify the pad usage on each layer. On each layer there will be a figure (range: 0-7) to indicate the pad usage on the layer. For example, 2 means the pad on this layer is for anti-pad usage. 4 means the pad on this layer is used as regular pad.

The details of the definition for the padTypes are as following:

So when you use the via components in ADS, you need to know the layer number of the original via in Allegro design (when you export the padstack from Allegro).

Export Layout IFF with Via Components from ADS

Export a design from ADS layout by click File >Export…, and select the Cadence/PCB option form drop-down list:

Import IFF with Via Components into Allegro

In PCB Editor, click RF-PCB > IFF Interface > Import…, browse to the proper layout.iff file:

All via components in the IFF file will be mapped back to Allegro generic vias:

I look forward to your comments!

Jerry "GenPart" Grzenia

What's Good About PCB SI AutoSolving Models in SigXplorer? You’ll Need the 16.6 Release to See!

Jerry GenPart — Wed, 29 May 2013 13:16:00 GMT

In previous releases, when you extract a net into SigXplorer, all the structures are automatically solved in Allegro PCB SI and then passed to SigXplorer. At times, the layerstack of the extracted structure might differ from the real layerstack in terms of the voids in a plane layer or shapes on the conducting layer. In such cases, the structure needs to be re-solved in SigXplorer. At other times, a field solution in SigXplorer takes a long time to run and often runs when not needed.
The 16.6 release of Allegro PCB SI provides support for on-demand solving of models using Bem2D, Ems2D, and FSVia. However, unlike previous releases, now compulsory model solving during extraction from PCB SI is eliminated. The vias and trace models are unsolved when extracted from PCB SI and no impedance values are reported for trace models after extraction if no matched models are found in the existing working IML library.

Read on for more details …

AutoSolve

The autoSolve parameter, when set to On, automatically calls the field solver when you make changes in the parameters of a trace in the spreadsheet, for example. By default, the autoSolve parameter at the circuit level is set to Off. As a result, during extraction, no solving is triggered except for FSVia. FSVia models are always solved during extraction:

For the commands which require a field solution, such as Simulate, Generate S-Parameters, and Transform to Constraint Manager, the default status of the autoSolve parameter is overridden and models are produced.

Solving Models

Models can only be solved using one of the following methods if the autoSolve parameter is set to Off by default -

Running a simulation
Using the Manage Unsolved Parts command
Using the Solve Batch Mode command

The Manage Unsolved Parts command helps you manage all the unsolved parts including vias and traces. This command can be accessed through the Analyze menu or by right clicking in the SigXp canvas -

Analyze menu:

RMB menu:

The command launches the Unsolved Part dialog which lists all the parts that have not been solved:

The Part Name column lists unsolved parts, while the Type column shows the type of the part, such as via or trace. The currently selected solver for vias and traces are also displayed. For example, in the figure above, FSvia will be used to solve the Vias, while Bem2D is used to solve the traces.

Note: All of the parts in the design appear in this dialog if there are no solved models associated with the extracted geometry found in the interconnect model library. If you run the Solver for one of the vias or traces, it is possible that the geometry matches one or more of the other elements. If so, the next time you launch this dialog, it may show fewer parts than expected.

Solving in Batch Mode

You can also solve traces and all vias using the Solve Batch command. Use this command to solve a single part in order to see the impedance, for example, or to create a model in the library with the current parameters.

Right-click on an unsolved part and choose Solve Batch Mode (FSvia):

Please feel free to share your feedback on this new PCB SI capability.

Jerry “GenPart” Grzenia

What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!

Jerry GenPart — Mon, 20 May 2013 19:02:00 GMT

Just a very "quick read" on a new option for Quickplace this week.

The Allegro PCB Editor Quickplace is an application used to ‘quickly’ scatter components around the perimeter of the design or to a room location. By default, components are placed not to overlap each other. As a result, the application may fail to place components if space is not available. A new control option in the 16.6 release,"Overlap components by," has been introduced to improve completion percentages. You can control the amount of overlap - the default value is seeded at 50%.

Read on for more details …

Invoke Place – Quickplace
Enable the option "Overlap components by," which is located near the end of the form:

Set ‘Edge’ = ‘Top’
Click ‘Place’ then review the results:

Feel free to provide feedback on this new capability.

Jerry “GenPart” Grzenia

What's Good About AMS Data Precision Options? They’re in the 16.6 Release!

Jerry GenPart — Mon, 13 May 2013 16:14:00 GMT

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage loses its resolution, displaying staircase waveforms. With 64-bit precision, for the same signal, a perfect ramp waveform is displayed.

Here’s a simulation output with the 32-bit data precision set (notice the staircase style of output):

Now, change the Probe Data option to 64-bit:

Here’s the resulting waveform (notice the smooth results):

I look forward to your feedback!

Jerry "GenPart" Grzenia

What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements!

Jerry GenPart — Mon, 06 May 2013 17:14:00 GMT

Just a quick blog this week to mention a couple productivity enahancements for Capture-CIS. The 16.6 Allegro Design Entry CIS (Capture) product has a few new enhancements for Saving designs.

Read on for more details ...

Save

In the Hierarchy viewer, you’ll now see pages and library components which have been modified by the designer marked with an asterisk (“*”). These are schematics and pages that require saving prior to existing Capture:

Save As

This enables a user-controlled save of associated files along with the project at a new specified location while maintaining the original references.

Available options:

Copy DSN to Project Folder
Rename DSN to match Project
Copy all referred files present within the project folder
Copy all referred files present outside of the project folder

Saved associated files include referred projects, designs, libraries, simulation profiles, output files, etc.

Select Project (Design Resources) and RMB click on Save As:

Change the destination directory and project name:

Please share your experiences using these new features.

Jerry "GenPart" Grzenia

What's Good About ADW’s Design Migration? 16.6 has many new enhancements!

Jerry GenPart — Mon, 29 Apr 2013 18:24:00 GMT

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required multiple executables:

–   Netassembler
–   Archiver
–   Purge
–   Packager

It was also less robust with dependencies on external programs, and the error resolution was not always clear.

With the 16.6 release, design migration is more efficient and less error prone. Below is a quick summary of what’s new in ADW 16.6 Design Migration.

Read on for more details …

New 16.6 Design Migration Features and Settings
Command line operation
“Designmigration –help” for full list of options and use

PART_NUMBER synchronization from the Library Flow
<PCBDW_LIB>/distributions/env/libimport_parts.ini file

Directive based migration
The project .cpm file directives can be preserved during migration
<ADW_CONF_ROOT>/<ATDM_COMPANY>/<ATDM_SITE>/cdssetup/pcbdw/MigrateDirective.txt

Running Design Migration

Please share your experience using the ADW Design Migration process.

Jerry "GenPart" Grzenia

What's Good About FSP’s Design Compare? Check Out 16.6!

Jerry GenPart — Thu, 18 Apr 2013 14:59:00 GMT

The 16.6 Allegro FPGA System Planner (FSP) product has an extremely helpful Design Compare capability.

With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP Design Compare form compares two FSP designs and is similar, but not identical, to the one used in Allegro PCB Editor.

The Design Compare form

Design Compare is a stand-alone form – it does not require the master, or any other design, to be open in FSP.
Click on the Design Compare icon or use the File > Design Compare pull-down:

In the Design Compare form, select the PCB copy on the right and the master design on the left (the order does not make a difference, but it’s easier to track differences if the master design is on the left).

Click the Compare button.

The “Show Only Diff” button helps to focus in on the differences. This is a “sticky” button – click to turn it on, click to turn it off.

The green arrows between the two sides and the yellow arrows at the top perform identical functions.

“Merge All To Left” and “Merge All To Right” will sync the designs in one step:

The FSP version of Design Compare is a little different than the one used in Allegro PCB editor. For one, there is no cross-probing in FSP like there is in Allegro. Also, in Allegro, the sections (connectivity, placement/ref des, etc.) are shown as tabs because the differences are displayed as a flattened list, for the entire design. In FSP, the items are displayed hierarchically and are selected from a drop-down:

Placement differences between the PCB copy and the FSP master are shown textually and graphically:

Merge the changes

You can merge all of the PCB changes into the FSP master. Click the “Merge All To Left” button:

You may encounter situations where an attempt to merge one signal(s) forces the merge of other signals:

This could happen if there is a cyclic dependency in the net connectivity. For example, if net n1 has to be moved to pin B26 and B26 is currently connected to net n2, then n1 and n2 are dependent nets. In other words, they both have to be moved together.

Please share your experiences using the FSP Design Compare capability.

Jerry “GenPart” Grzenia

What's Good About DEHDL’s Constraints Comparison? The Secret's in the 16.6 Release!

Jerry GenPart — Tue, 16 Apr 2013 13:40:00 GMT

The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare two databases for constraint differences. The databases that can be compared are of the following types:
• Schematics (.cpm)
• Layout design (.brd, .sip, .mcm)
• Constraints Manager Database (.dcf, .tcf)

The Constraint Comparison Utility can be used for comparing two different revisions/versions of the schematic or board databases. This utility can also be used for comparing the schematic database with the board database. A report is generated as a result of the comparison and lets you see all the changes which have been made to the design database since it was last synced up. This report helps you ensure that none of the constraints are conflicting and thus might overwrite on sync up.

The utility can be integrated in any of your design flows where you feel that you need to see the constraints differences in two databases before proceeding further in the design.
The utility can be invoked from the command line using command cmDiffUtility. This command launches the Cadence Constraints Differencing Utility dialog box, as shown below, where you can specify the two databases which need to be compared for constraints differences:

The button (browse) can be used to select the database. Once you click this button, the file selection dialog box appears. This dialog box displays the files based on the file type filter. By default the filter is set to “Constraints Files (*.dcf, *.tcf)”.

You can select any of the following options to change the filter setting and select appropriate databases:

Once both the databases are selected, the “Compare Files” button is enabled. Click this button to start the database comparison. The results of comparison between the two databases are reported in a Firefox window:

The report is displayed as a single screen, with two frames – left frame containing the object tree and the right frame containing the details of the selected tree item.

The complete report contains hyperlinks and helps in navigating through any of the objects within the various tools – Design Entry HDL, Allegro PCB Editor, Constraint Manger. When you click a category in the tree in the left frame, the details containing lists of all the objects of that category are opened in the right frame. These details contain the object name and brief description of the changes observed.

All the object names are also hyperlinked. You can click any of the objects to view more details. The object names are also visible in the tree view in the left frame, and the detailed view can also be opened by selecting the object name there. Since the different object categories are listed in the tree view, you will notice that you can navigate to the same difference from multiple places.

Please share your experiences using this new feature.

Jerry “GenPart” Grzenia

What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself in 16.6!

Jerry GenPart — Tue, 09 Apr 2013 15:47:00 GMT

Beginning with the Allegro PCB Editor 16.6 release, you are provided a methodology to export a technology (.tcf) or constraints (.dcf) file which is a generic cross-section. A generic-cross-section file (GCSF) captures constraints for specific layer types. Currently, a GCSF supports four types of layers: TOP, INTERNAL (internal signal), PLANE, and BOTTOM.

Importing a GCSF will not update the design’s cross-section, but will update the design’s constraint information (electrical, physical, and spacing) based upon the current import modes (overwrite, merge, and replace).

When a GCSF is imported into a board, constraints from that techfile will be mapped as follows -
1.    TOP - TOP (topmost etch layer)
2.    INTERNAL - signal layers between TOP and BOTTOM
3.    PLANE - all plane layers
4.    BOTTOM - BOTTOM (bottommost etch layer)

Generating a GCSF

1. Open an existing board or create a new one and edit constraints.
2. In Constraint Manager, use File > Export > (Technology file or Constraints file):

3. Select the “Generic” radio button in the “Export cross-section” section.

The “Generic” radio button is enabled only if the “Physical & spacing constraints” box is checked.
The “Configure” button is enabled only when the “Generic” radio button is selected.
The “None” radio button is enabled only if “Physical & spacing constraints” box is not checked – otherwise cross-section data is necessary.

4. Click the “Configure” button if you want to select the layers you would like to use as TOP, BOTTOM, INTERNAL, and PLANE (layer mapping):

This step is optional. If generic cross-section is not configured, the default mapping will be used.
User selections are remembered only for the current dialog form – when you invoke the export dialog again, the default mapping will be used.

Default mapping:

TOP: first etch layer

INTERNAL: first signal layer after TOP

PLANE: first plane layer

BOTTOM: last etch layer

To exclude a generic layer from the techfile, select <IGNORE>:

In the situation shown in the screenshot above, the resulting generic techfile will have only three generic layers – TOP, PLANE, and BOTTOM.

Importing GCSF

Open Constraint Manager and select File > Import > (Technology file or Constraints file).
Select the GCSF that you have exported from a different database and choose an Import Mode (overwrite, merge, or replace).

If in the imported GCSF some of the generic layers are ignored, then layers matching the ignored layer will not be changed. This is what the report will look like:

Note: When a GCSF is imported, the cross-section of the original board stays intact (i.e. the number of layers, their names, and characteristics remain as before importing; only the Csets are imported).

The GCSF techfile units will behave the same way as any other techfile units. A suggested approach would be to have the same units used in both the original and the target board.

I look forward to your feedback!

Jerry “GenPart” Grzenia