Joseph Hupcey Blog

DVCon 2013: Functional Verification Is EDA’s “Killer App”

jvh3 — Mon, 11 Mar 2013 06:28:00 GMT

With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done. Here are some of the some of the highlights I took away from this informative event:

DVCon 2013 was a one stop shop for panels, papers, posters,
live demos, and tutorials on functional verification

* Great panels on Verification Planning and Drastically Improving D&V

Two panels at the conference provided valuable food for thought in their own ways. First, in regard to the Cadence lunch panel on "Best Practices in Verification Planning", EDA industry observer Peggy Aycinena wrote:

Sometimes magic happens at panel discussions at technical conferences, and that was the case mid-day on Wednesday at DVCon in San Jose this week, where the conversation was lively, entertaining and informative on the pedestrian, albeit foundational, topic of "Best Practices in Verification Planning." Ironically, the hour-long conversation did not appear to be planned at all, but to be organic and spontaneous ...

Granted I'm biased - but I have to agree whole heartedly. The panelists were generous in sharing their experiences with the mixture of art and science required by verification project planning, and I urge you to review either of Peggy's account of the panel or Industry Insights' Richard's Goering's in depth report.

Later that day "panel magic" happened again at the Industry Leaders panel on "The Road to 1M Design Starts". To everyone's delight, the panelists embraced the spirit of brainstorming how design and verification can be made significantly (think 20x, even 100x) more efficient. Sound impossible? One panelist gamely recalled that not many years ago there was a "software crisis" where the best software managers could expect was a net of 10 tested lines of code per day per engineer. Fast forward to the present, and teenagers with a lot of imagination but limited programming experience are creating money-making apps on incredibly complex mobile platforms thanks to very well thought out development tools and libraries. The panel challenged the audience to consider the lessons of such anecdotes in increasing abstraction and automation for EDA tool providers and their customers alike.

Richard Goering covers this panel in depth here in his Industry Insights blog.

* Apps as the new EDA paradigm

At last year's DVCon one of my product teams ("Team Verify") introduced the idea formal apps in our tutorial. (In a nutshell, a formal app enables usage of powerful formal engines "under-the-hood" by an engineer who has never used formal before, to solve specific problems.) At the time we were the only ones promoting this concept and offering the underlying product support. What a difference a year makes -- not only have our immediate competitors adapted this approach, but the "app" term was being applied to both formal, multi-engine, and pure dynamic simulation offerings and every thing in between. Of course, it's hard to be surprised by this given the EDA-related appeal is obvious: because apps are focused on specific, painful problems -- i.e. they are customer-centric by definition and in practice -- they are a clear win for both end users and vendors.

* The e/Specman Surge

After years of having waves of Specman-related abstracts be rejected seemingly out of hand, this year the assembly finally got to see what Specmaniacs have been eager to share with this verification community. One look at the posters by Meirav Nitzan of Xilinx (1P.21, Taming the Beast: A Smart Generation of Design Attributes (Parameters) for Verification Closure using Specman) and Horace Chan of PMC Sierra (1P.25 Maximize Vertical Reuse, Building Module to System Verification Environments with UVM e) and it's obvious that ‘e' and Specman usage are both thriving and they remain at the forefront of verification innovation.

Until next DVCon, may your power consumption be low and your throughput be high.

Joe Hupcey III

On Twitter: @jhupcey, http://twitter.com/jhupcey

Reference Links

DVCon 2013 Proceedings, http://dvcon.org/

DVCon 2013 YouTube playlist of speaker and panelist video interviews:
http://www.youtube.com/playlist?list=PLYdInKVfi0Kantj1U3H8pk9NkxFykT0rG

Richard Goering Industry Insights report: DVCon 2013 Expert Panel: How to Succeed with Verification Planning
http://www.cadence.com/Community/blogs/ii/archive/2013/03/05/dvcon-2013-expert-panel-how-to-succeed-with-verification-planning.aspx

Richard Goering Industry Insights report: DVCon 2013 Panel: 1 Million IC Design Starts - How Can We Get There?
http://www.cadence.com/Community/blogs/ii/archive/2013/03/01/dvcon-2013-panel-1-million-ic-design-starts-how-can-we-get-there.aspx

Peggy Aycinena, EDA Café: DVCon 2013: Best Practices in Verification Planning
http://www10.edacafe.com/blogs/whatwouldjoedo/2013/02/28/dvcon-2013-best-practices-in-verification-planning/

2013 CES: Top 4 Trends Benefiting EDA

jvh3 — Thu, 17 Jan 2013 16:02:00 GMT

While a variety of EDA customer segments are growing, consumer electronics continues to drive the lion's share EDA of industry revenues. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While I couldn't personally attend CES this year, like last year my two trusted agents (specifically, Unified Communications (UC) expert David Danto of Dimension Data, and Joseph Hupcey Jr., video & communications systems architect and father of yours truly) were on the ground to field check the myriad of reports streaming in from legacy and new media. Thus, allow me to highlight the following trends from CES 2013 that I suggest will have a big impact on EDA this year.

1 - TV's ongoing evolution: clearly the most visible product category at CES were the new crop of "UltraHD" a/k/a "4K" resolution TVs. That's 3840 X 2160 pixels, or twice the horizontal and vertical resolution of the 1080p HDTV format, with four times as many pixels overall. Concurrently a lot of very pretty, very large screen OLEDs were given center stage in many booths, suggesting that after over 10 years of CES previews this vibrant, richly color saturated display technology is finally ready for prime time. My agents report that that 4K screens are noticeably better than today's HD - it's not quite the same dramatic leap from SD to HD - but the difference is visible enough to tempt people to upgrade if the price is right. And thus the key question(s) revolve around volume production availability and pricing, i.e. when will the cameras, DVRs, streaming support boxes and services, and the TV sets themselves be available at the price points consumers expect?

As it turns out many professional and even some prosumer cameras already support 4K today. Quite a few productions are shot in 4K and after the final edit are down sampled to standard HD (don't ask me why, but somehow 4K video down sampled to 1080p looks richer than natively shot HD.) There are also a handful of professional grade theater projectors that support 4K. However, the good news for EDA and our customers' perspective is that's pretty much where the equipment support ends. The entire video data flow after the editor is up for grabs - DVRs, routers, and any other apps you can think of for TV need to be re-created to support consumer UltraHD. Given the bandwidth required to shuffle 4K frames around, clearly hardware-assisted verification products will continue to enjoy robust demand. With the ongoing growth of apps on TV platform, I further assert hardware/software design and verification solutions will also see ongoing growth. Last but not least, low power design and verification requirements - whether from regulatory bodies or end-customers themselves -- will continue to be a factor in this new generation of equipment.

Bottom-line: I agree that UltraHD will inspire demand for new TVs and supporting equipment, which means many more SoCs and peripheral ICs will need to be designed and shipped.

2 - "Born Mobile": this tag line was the theme of Qualcomm's opening keynote presentation, and indeed could be applied to over half of CES where smart, mobile devices of all forms - and a plethora of supporting accessories - took up a large chunk of the exhibit hall acreage. I see EDA being well positioned to benefit in several major categories: low power (self-explanatory), advanced node tool chain support, and design and verification IP.

At the risk of stating the obvious, the demand for increasing performance and functionality is clearly unabated, and hence the investments being made in 14nm and lower is money well spent by our industry. Another trend expertly observed in this EETimes interview of Broadcom's co-founder and CTO Henry Samueli is that almost everything on the show floor had embeded WiFi connectivity. Beyond the opportunities for network infrastructure equipment growth, I believe this significant step toward the "Internet of Things" heralds opportunities in design and verification IP - not for just WiFi and other radio IP, but IP to enable the rapid smartening up of previously unconnected, dumb devices like refrigerators.

3 - Born Mobile, Automotive Style: CES 2013 devoted a massive area to in-car entertainment and supporting accessories. Such was its scale that my agents were barely able to scratch the surface of this pavilion, but they came away impressed at how this category has visibly grown year-over-year in size and scope. It used to be all about glitzy car stereos, speakers of all shapes and sizes, and amusing arrays of blinking lights to decorate the audio installation. Today, the offerings are all about outfitting the passenger cabin like a home entertainment center, where you can customize the standard platform with apps like any other self-respecting modern device. The obvious point: in addition to the growth in electronics being used under-the-hood, the demand for multiple mobile entertainment centers in the driveway is good news for semiconductor growth.

4 - Standards-Based IP Enabling Clever Innovation: Perhaps a better case in point for anticipating growth in standards-based IP and low power design & verification is the eminently practical StickNFind Bluetooth Stickers. Simply affix their special sticker to something you often lose (car keys, TV remote control, phone, luggage), and when it goes missing you can hunt it down using their iOS or Android smartphone app to follow a radar-like display to sweep for the lost item. Clearly products like this are enabled by the availability of high quality, standards-based design and verification IP; and in turn we can expect clever new applications like this to drive growth.

If you went to CES this year – or not -- please share your observations in the comments below, or offline.

Until next CES, may your throughput be high and your power consumption be low.

Joe Hupcey III

On Twitter: https://twitter.com/jhupcey @jhupcey

P.S. Speaking of trade shows, in the verification space the annual DVCon's clear focus on functional verification technology and methodology has made it a growing, high value technical and trade forum. Hence, my colleagues and fellow bloggers will be there in force February 25-28 at the DoubleTree Hotel in San Jose, CA! In particular I welcome you to join me at the Wednesday lunch panel, "Expert Panel: Best Practices in Verification Planning" and the Thursday tutorial entitled "Fast Track Your UVM Debug Productivity with Simulation and Acceleration" (includes coffee & lunch) Register today!

Reference Links and/or Other Interesting CES 2013 reports

David Danto of Dimension Data's report on CES 2013: A View From The Road Volume 7, Number 1 -2013: International CES

SemiWiki: Battling SoCs: QCOM vs NVIDIA vs Samsung

EETimes DesignNews: CES Slideshow: The Next Big (or Little) Things

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study With the GoPro Hero2 Camera

jvh3 — Wed, 12 Sep 2012 15:00:00 GMT

Right up there with functional verification, the challenges of low power design and verification present an existential threat to our customers' products, and ultimately their businesses. Clearly both sides of the low power coin -- reducing generated heat and/or increasing efficiency to make the most of every available joule -- are of primary concern. But what happens when external, environmental factors conspire to betray even the best low power electrical design? In the case of the GoPro "Hero2" camera, ironically the device's waterproof housing that has help propel this amazing system to some incredible heights can sometimes undermine its operational performance in certain corner cases.

First, let me describe the system setup. As shown in the image below, the GoPro Hero2 camera is the little cube on the left. In the middle is the (empty) polycarbonate protective housing that's gasketed to keep out water and dirt. On the right the camera is sealed inside the housing.

As per this video I shot exclusively with GoPro Hero2 this summer, I can personally attest that the camera and housing make for a very solid and effective mechanical system. (If the embedded video doesn't play, click here.

Overall the camera performed brilliantly. However, there was one issue that emerged: whenever the camera got too hot it would automatically shut down to avoid damaging itself. For example, when the system is in direct sunlight the housing seems to act like a greenhouse and/or it insulates the camera such that the camera heats up significantly faster than when it's out of the housing (especially on an already hot summer day). So while I praise the Hero2's designers for building-in this automatic fail safe, at the same time it's frustrating to wait for the camera to cool down. (FYI, keeping the system submerged in the pool, or putting it in a cooler with the drinks and snacks expedites the turnaround process. But I digress ...)

What are the lessons for EDA here? I see three:

* The need to model "out of band" behaviors in the digital design domain - i.e. consideration of expected environmental factors in addition to the device's specified logic and firmware performance - will need to become more prevalent as our customers develop more devices destined for mobile use.

* Electronic Design Automation (EDA) will need to get even closer to Mechanical Design Automation (MDA). I know my colleagues in PCB design and IC packaging are well down this road, but this GoPro case study suggests that SystemC/RTL design and verification must also consider macro-level physical factors as well. Beyond today's UVM Low Power flows, should there be a "UVM Thermal Behavior" verification flow?

* Last but not least, the general moral of this story is that as far as we've come, collectively the EDA industry has a ways to go before our innovations make low power one of our customers' lower priorities.

Joe Hupcey III

On Twitter: http://twitter.com/jhupcey, @jhupcey

P.S. For fellow parents:
Chances are you have probably heard of GoPro cameras before, but might have dismissed them as being only for young adventurers. Certainly GoPro supports such customers and their extreme sports very well. However, I quickly realized that this camera and its ruggedized shell is as effective for capturing my constantly on-the-go daughter's activities as it is for motor sports and outdoor adventures. Since I'm constantly asked about the Hero2 system by other parents, allow me to anticipate the question "Does the GoPro ‘work' for capturing family-style activities?" with a hearty "Yes". In a nutshell, it's a perfect second camera for the many times where you would rather avoid subjecting your "regular" camera (be it a cell phone camera, point&shoot, DSLR, or camcorder) to rigors and risks of family-oriented activities like swimming, bicycling, rainy hikes, and winter sports.

Video: Interview with Professional Teenage Technology Coach Kristine Bonhoff

jvh3 — Tue, 31 Jul 2012 13:00:00 GMT

Over the past several years at various EDA trade events, one of the more popular forums have been panel discussions and interviews asking teenagers about the technology in their daily lives. However, those forums have been comprised of amateurs, whereas in this interview I've secured a professional technology consultant -- Ms. Kristine Bonhoff, a college student by day, and a paid technical coach and volunteer in her spare time. Specifically, people of a certain age pay Kristine to coach them on how to get the most out of the various gadgets and related apps they own. She also volunteers to give tech training courses to inner city residents.

In this interview Kristine shares her clients' most common FAQs, their biggest positive and negative misconceptions about various technologies, and her wish list for the future.

If the video doesn't play, click here.

I believe you will find much food for thought in her remarks. My take-away is that there are two clear and very challenging implications for the EDA industry:

* Apps will continue to drive the requirements and demand for their respective host devices, and not the other way around.

* Enabling low cost to the end-consumer - whether it's a low retail price or via clever rent-to-own business models - is as important for our customers as ever.

Joe Hupcey III

On Twitter: http://twitter.com/jhupcey, @jhupcey

Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal (UVM-MS)

jvh3 — Tue, 24 Jul 2012 15:00:00 GMT

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through my DVCon 2012 folder -- lo and behold I came across the following video interview. It was shot during the show, but the official approval fell between the cracks and didn't come through until recently. Regardless, the issues raised in the paper that's the subject of the interview (From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design) are as challenging as ever. Here the paper's author Neyaz Khan, a mixed signal verification R&D manager at Maxim Semiconductor, discusses what needs to be considered when the Universal Verification Methodology (UVM) is extended to support mixed signal verification projects, the implications for circuit modeling, and the optimal R&D team composition.

If the embedded video fails to play, click here.

Note: if you have never attended a DVCon, you can expect to meet design and verification experts like Neyaz everywhere you turn - clearly worth the price of admission!

Question: if you are in the digital-mixed signal field, are you seeing similar trends in your company and/or customer base? Please share your thoughts below, or contact me offline.

Until next DVCon, may your throughput be high and your power consumption be low!

Joe Hupcey III

On Twitter: @jhupcey, http://twitter.com/jhupcey

Reference Links
DVCon 2013 Call For Abstracts

Neyaz's DVCon 2012 paper, From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design

Richard Goering Industry Insights report on the book Neyaz co-authored: "Advanced Verification" Book Brings UVM to Mixed Signal, Low Power, Multi-Language

My Photo Essay, Video Playlist, and Comments on DVCon 2012

DAC 2012 Video: Dr. Kerstin Eder, University of Bristol, About Her Course on Functional Verification

jvh3 — Thu, 05 Jul 2012 13:00:00 GMT

Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK, teaches a course on functional verification. In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped up by industry immediately upon graduation.

If the embedded video doesn't play, click here.

Brief digression in regard to the industry demand for her graduates:

Anecdotally I can confirm the high demand for verification engineers -- fresh out of school or experienced -- here in the USA and other geographies. For example, I can tell you first-hand that here in Silicon Valley we are seeing an increase in poaching: a few weeks before DAC I had scheduled a meeting with a verification group based at the Santa Clara offices of a large, world-wide semiconductor company. They had to cancel because two key verification engineers that we were going to meet with had just quit to go to another company!

In short, if you are an engineer or computer scientist between jobs, earning your way through courses and/or training like that offered by Dr. Eder will give you a leg up in this tough economy -- the verification field seems to be about as recession proof as it gets in the technology business. If you can't go back to school, you can get a running start on your own by taking advantage of the many resources introducing the Universal Verification Methodology (UVM). For starters, there is a ton of great, free material on the Accellera UVM World site -- http://www.uvmworld.org/. Cadence has also published two books on verification: A Practical Guide to Adopting the Universal Verification Methodology (UVM) provides a great overview of UVM, and Advanced Verification Topics uses UVM as a framework for functional verification with mixed-signal, multiple languages, low power, metric-driven verification, and more.

Joe Hupcey III

On Twitter: @jhupcey, http://twitter.com/jhupcey

Reference Link
Dr. Eder's home page: http://www.cs.bris.ac.uk/~eder/

Video: DAC 2012 Update on AMIQ’s DVT IDE – New RTL Design Work Flow Support

jvh3 — Mon, 02 Jul 2012 13:00:00 GMT

Readers of this blog and of Team Specman will recall that Integrated Development Environment (IDE) and verification services provider AMIQ has been in the vanguard of supporting functional verification methodologies and testbench creation for years. The success of verification engineers using AMIQ's "DVT" IDE product has been increasingly noticed by their RTL designer colleagues such that AMIQ is now adding new capabilities to DVT to support RTL design work flows. In this interview shot on the DAC 2012 expo floor, AMIQ CEO Cristian Amitroaie describes how they have extended the DVT IDE to address the needs of design engineers, including powerful new capabilities to refactor and visualize the code and signal flow.

If the video doesn't play, click here.

Question: are your RTL design engineers becoming more concerned about integrating with and/or perhaps even adopting verification-style methodologies?

Joe Hupcey III

On Twitter: http://twitter.com/jhupcey, @jhupcey

Reference Links
DVCon 2012: AMIQ launches "Verissimo" - a verification-centric, UVM-aware SystemVerilog linter

The DVT website: http://www.dvteclipse.com/

Also recall AMIQ's evaluation process is a breeze -- just fill out this form:
http://www.dvteclipse.com/design_and_verification_tools_trial_request.php
and they email you a demo license. That's it!

DAC 2012 Video: R&D Fellow Mike Stellfox on the Emerging Bottlenecks in SoC System Verification

jvh3 — Wed, 27 Jun 2012 13:00:00 GMT

R&D Fellow Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into production. In this interview on the floor of the Design Automation Conference (DAC 2012), Mike gives a brief snapshot of how innovations in debug automation have moved from the lab to the show floor, and how ad-hoc hardware-software SoC verification processes are breaking down, thus calling for more repeatable, automated solutions.

If the embedded video doesn't play, click here.

Question: are you seeing similar trends in your company and/or customer base? Please share your thoughts below, or contact me or Mike offline.

Joe Hupcey III

On Twitter: @jhupcey, http://twitter.com/jhupcey

Video: DAC 2012 Discussion with EET's Brian Fuller on EDA and Video

jvh3 — Mon, 25 Jun 2012 15:30:00 GMT

Continuing our conversation on leveraging social media for EDA, at the Design Automation Conference (DAC 2012) I had the honor of interviewing again with EETimes editor Brian Fuller -- this time the focus of the conversation was on video. Specifically we talked about which video formats have proven to be most popular, and which are most effective for delivering complex technical information.

To play the video, click on the photo above or click here: http://goo.gl/BtDOp (Until the intro material from the live feed is edited out, you might need to manually skip ahead to the 5:06 mark in the video.)

Looking back at this conversation, the key point that I hope you come away with is that product managers -- not just corporate marketers -- need to include video as part of their social media campaigns and overall promotional strategy for their products. Like any other form of collateral, if the video is focused on a high value topic presented in a no-nonsense way, customers and prospects will watch. And thanks to modern search engines, they can discover your videos months and even years after they are first posted. Plus, these days high-quality video is relatively cheap to produce, and essentially free to distribute.

Product managers: are you seeing similar positive responses to your product-related videos? Please share your thoughts below, tweet them, or contact me offline.

Joe Hupcey III

On Twitter: @jhupcey -- http://twitter.com/jhupcey

Reference Links
My YouTube channel where most of the videos referred to in the interview are hosted:
http://www.youtube.com/jhupcey

An example of a "snack sized" tech tip video:
http://youtu.be/gQ5ozp5NuO8

Our prior video discussion on effective social media channels for EDA:
http://bcove.me/oj7mkdrb

Brian's EETimes+AVNet "Drive For Innovation" home page, hosting numerous videos of innovators across the country:
http://www.driveforinnovation.com/

Photo Essay and Comments on DAC 2012 in San Francisco, CA

jvh3 — Fri, 15 Jun 2012 16:41:00 GMT

In addition to the annotated image gallery (click here or on the image), below are some long form comments on particular aspects of this year's Design Automation Conference (DAC 2012).

Verification momentum - I grant that I might be influenced by some amount of selection bias, but I could swear that this year there was way more interest and vendor presence in the functional verification space than at recent DACs. Our group was certainly out in force; where in addition to the popularity of our demo suites and demo pod we were plenty busy supporting customer meetings, booth theater presentations, User Track papers and posters, and standards organization activities like the UCIS 1.0 launch luncheon. And across the show floor it seemed like every third booth was touting a functional verification offering of some form. With the 20nm node on the horizon -- and thus gigagate chips with 100s of IPs becoming mainstream vs. the province of only our largest customers - all this verification-related energy comes as no surprise. (Recall there was similar momentum in this space at DVCon and at CDNLive San Jose earlier this year.)

Formal & ABV momentum - similar to last year's experience, I sensed an increased visibility and interest in formal & assertion-based verification (ABV) related technologies. For starters, we received many such queries at the booth demo pod about our Coverage Unreachability app (some fortuitously inspired buy our Formal-driven Lego Rubik's Cube solving robot). There were also novel, formal-based initiatives like the "Oski Challenge", where services house Oski Technology took a sight-unseen IP block from NVIDIA and found 4 serious issues in the 72 hour time frame of DAC (full disclosure: Oski used Incisive Enterprise Verifier for this ambitious project). Finally, the DAC User Track best paper was about a bypass memory verification project that used Incisive Enterprise Verifier. (Coincidence?)

The low profile of cloud computing - in sharp contrast to last year's DAC (recall Richard Goering's report on the 2011 DAC panel, "DAC Panel Says ‘Yes' to EDA in the Cloud -- But Differs on When" captures the prevailing sentiment of that time well), there was scant evidence of cloud-oriented solutions anywhere on the floor. This is not to suggest that EDA-centric cloud solutions are dead (for example, I know Cadence's Hosted Solutions continues to build on their loyal customer base). Instead, it's apparent that the majority of EDA customers are either (a) reluctant to embrace cloud solutions in general for whatever reasons, or (b) are reluctant to have EDA vendors handling this aspect of their operations. Granted there are a number of applications and data sets that are either too inefficient or just too sensitive to move in and out of the cloud. But in the greater world outside EDA, with every passing day this list appears to be shrinking ...

DAC itself - despite the marginal increase in attendance vs. last year, the show was dramatically smaller than the last time it was in San Francisco. It seems that many customers are too busy to come to a general forum like DAC. Conversely, they seem to make time for smaller, topic-focused events like DVCon, ESC/Design West, or even specific technology tracks at vendor events like CDNLive. Additionally, in 2012 there are numerous channels where customers can get information and support when and where they need it. The bottom-line: while customers continue to vote with their feet year-after-year, at least in 2012 it was clear to me that the declining DAC attendance figures do not reflect the health of the EDA industry, or the electronics and semiconductor industries that we serve.

To conclude on a positive note, the Cadence Denali Party was just as well attended and fun as ever -- this set has a handful of images and a brief video for you to see for yourself.

Until next DAC, may your throughput be high and your power consumption be low.

Joe Hupcey III