Brad Griffin Blog

Re: questions about Allegro Package Designer

Maxwell86 — Mon, 07 Jun 2010 17:49:41 GMT

Hello,

Characterization and SI/PI analysis of APD designs is done with Allegro Package SI (APSI). Here is a link to the datasheet: http://www.cadence.com/rl/Resources/datasheets/7429_Allegro_IC_PKG_DS_FINAL.pdf

See page 7 for a detailed list of features.

Best regards,

brad

Allegro PCB SI Offers Out-of-the-Box IBIS 5.0 Support

Maxwell86 — Thu, 11 Feb 2010 19:00:00 GMT

IBIS is sometimes known as the bird of knowledge, but is also the popular standard in modeling I/O buffers. Well, IBIS recently grew some big new wings when the 5.0 version of the spec was ratified. Those big wings include support for algorithmic modeling of SerDes transceivers. Instead of just modeling with numbers and tables, the 5.0 standard now allows software modules or dynamically linked libraries (DLLs) to be included in the model. This well defined software interface allows for very sophisticated algorithms that match the sophisticated equalization algorithms that take place inside the SerDes to be implemented by signal integrity simulation tools.

Official support for IBIS 5.0 AMI models is now available in Allegro PCB SI. While Cadence has supported the AMI standard for over two years, it was not until recently that the IBIS committee released their official parser and that has now been integrated into the latest PCB SI release.

Users of PCB SI should navigate to downloads.cadence.com, select SPB163 and download the latest hotfix.

Cadence is pleased that the work they first validated with IBM at DesignCon 2007 (see Interrogating the chips in 2007 EE Times article) has reached this ultimate level of standardization. It took a lot of time, energy, and cooperation with other companies, but both Cadence and Cadence customers will be well served for their patience and persistence.

After you have a chance to download the latest hotfix and work with our sample AMI models, please let us know your feelings about the “out-of-the-box” IBIS-AMI support in Cadence Allegro PCB SI.

Brad Griffin

Come See TeamAllegro at DesignCon2010

Maxwell86 — Sat, 30 Jan 2010 00:00:00 GMT

A new year means another DesignCon and 2010 is an exciting year for the PCB and IC Packaging team at Cadence – sometimes known as TeamAllegro.

This year you will find the Cadence booth at an ideal location in the center of the Exhibition floor. We will have a demo pod dedicated to Allegro and SiP. We’ll be happy to show you the latest technology around multi-gigabit, DDR3, and power integrity as it works seamlessly with Allegro PCB, IC Packaging, and Cadence SiP design databases.

We are also very proud to be demonstrating the new user interface for our Signal Integrity tool.

This new version can utilize IBIS models directly as well HSpice and Spectre transistor models through a simple import wizard.

One other feature you should drop by and see is the new multi-gigabit screening feature that guides you to the routed signals on your board that are most likely to give you trouble with compliance testing.

This year, we will be taking special note of the paper being delivered by Donald Telian and Sergio Camerllo as they discuss simulation and modeling techniques for 6+ Gbps channel design. Use this link to get this session added to your calendar.

One other thing to note is that social media will have a big role at this year’s DesignCon. Cadence will be participating in a panel on social media that we hope you will attend. Those of you on Twitter should be following @DesignCon2010 and you may also want to follow @TeamAllegro. We will keep you posted on activities throughout the event.

Let us know your thoughts on DesignCon2010 as well as the latest features in Allegro and SiP.

Brad Griffin

APD and SiP Layout 16.3 - Virtual-ly Amazing

Maxwell86 — Fri, 04 Dec 2009 21:30:00 GMT

On December 2, the Cadence Allegro team went live with the Cadence Allegro and OrCAD 16.3 Virtual Conference (CAO16.3).

This virtual first in EDA was an amazing success with hundreds of visitors, many of whom visited the SiP and IC Packaging booth.

If you missed this event as it was happening, do not be concerned. You can still register and check out the content in the booth. You will want to pay special attention to the newest product in the SiP and IC Packaging space, Cadence SiP Layout XL. Video demonstrations and papers are at your fingertips!

I think you will also enjoy the presentations from our sponsors. Once you've had a chance to look around, let me know what you think of EDA's first Virtual Conference.

Brad Griffin

Co-Design - Its Not Just an Exercise in Excel Any More - Learn Why at the Aug. 26 Webinar

Maxwell86 — Fri, 14 Aug 2009 14:01:00 GMT

Co-Design … some are trying to do it with spreadsheets … everyone is talking about it. But talk is cheap. Can you really optimize a package footprint and a chip I/O padring such that that package and PCB costs can be minimized?

What if using a straight forward flow you could take the devices to which your chip needs to interface and place them on a canvass with your chip and package. And then what if you could then see the maze of interconnect lines that crisscross in every imaginable direction giving you the daunting task of trying to figure out how to unravel that mess? But then, what if, with a few simple clicks of a mouse, you could turn …

Wouldn’t that make the routing your board and package easier? Wouldn’t that help keep costs down on your final product?

Yes, as a chip designer, you can look out into the package and board and optimize the full system. If you want to learn how Cadence SiP Digital Architect empowers chip designers to do just that, come see John Park’s webinar on August 26. You can register for the “SoC I/O Padring Optimization Using Cadence SiP Co-Design Technology” webinar by clicking here.

Please let us know what you think of the webinar.

Brad Griffin

Power Issues? Manage Your IR Drop The "Advanced" Way

Maxwell86 — Tue, 11 Aug 2009 13:00:00 GMT

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written by Advanced Layout Solutions. In this post, Chris Halford discusses how his company works to ensure the PCBs they design meet requirments for voltage and temperature stability. As Chris mentions, the challenge of managing power paths is complicated by the need to carve up power planes into swiss cheese like structres around high pin count BGA devices. We're pleased to hear of the successes Chris and his team have found navigating these challenges using Allegro PCB SI, and specifcally using the IR Drop feature available in all 16.x releases of the tool.

You can find this whitepaper as well as many other resources for Signal / Power integrity in our Resource Library (click here).

Please let us know if you've had similar experiences.

Brad Griffin

Everything You Want to Know About APD / SiP 16.2 - Bill Acito Webinar on March 18

Maxwell86 — Wed, 11 Mar 2009 15:06:00 GMT

(Note: Click here to view Bill Acito's webinar.)

If you caught Jerry GenPart's blog in November on Advanced Plating Bar Checks and wondered what else is new in APD 16.2, you are in luck. On Wed, March 18, Bill Acito, Product Engineer, will review the long list of new technology available in the latest release.

As an example, you'll see how the latest HDI technology in the Allegro platform is supported in APD / SiP.

And also the wirebond enhancements.

Please join us for the webinar. To register to see it live or view an archived recording (after March 18), please click here and choose the What's New in IC Packaging / SiP webinar.

We look forward to your feedback on this foray through the latest and greatest APD features.

Designing DDR3 Interfaces In a Constraint Driven Design Environment

Maxwell86 — Tue, 24 Feb 2009 22:30:00 GMT

If you’ve been wondering how to capture high speed memory interface design intent early in your design process and drive that through to final verification, the Allegro PCB team has a number of ways we can help.

First, be sure to attend or watch a recording of the webinar planned for March 11 where we will walk through some of the latest technology built to address high speed memory interface design. You can register on this page.

After the webinar, you may want to look into our web-based, self-paced training courses. To learn more, watch this video as Dave Palumbo of our Educational Services team introduces you to a course that teaches the front-to-back constraint managed flow using a DDR2 memory interface as an example.

Registering for a course or to see the full catalog of training courses can be done at www.cadence.com/education

Let us know what you think of the webinar and / or the training course.

Allegro PCB SI at DesignCon

Maxwell86 — Fri, 23 Jan 2009 17:13:00 GMT

Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro PCB SI for both serial link channel analysis as well as high-speed memory interface design verification. In addition to other demos in the booth, be sure to mark your calendars for the Business Forum Panel, Do It Right or Do It Over? Signal Integrity Engineers in the Era of Highly Compressed Project Schedules where industry professionals talk about how schedule timing constraints can be just as critical as setup and hold timing.

Also, be sure to stick around for Thursday and attend the paper, New Serial Link Simulation Process, 6 Gbps SAS Case Study. Donald Telian will dicuss his engagment at Hitachi where AMI models were used with Allegro PCB SI.

Hope to see you there. Be sure to say hello.

Cadence SiP and IC Packaging at DesignCon

Maxwell86 — Fri, 23 Jan 2009 17:00:00 GMT

Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI. This integration not only supports signal integrity, but also there is new package power integrity technology.

We will also be showing techniques where Package-on-Package designs can be created, optimized, and analyzed.

I also hope you will drop by the Multi-Die Chip/Package Co-Design for SiP Applications Technical Panel on Tuesday afternoon. Please be sure to come up and say hello to me.

Let us know what you think of DesignCon.