https://community.cadence.com/searchen-USTelligent Community 11en-usnoSearch resultshttps://community.cadence.com/cadence_technology_forums/computational-fluid-dynamics/f/turbo/59579/importing-cgns-file-to-fidelity-turboSat, 15 Jun 2024 12:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59579cfd enthusiast/cadence_technology_forums/computational-fluid-dynamics/f/turbo/59579/importing-cgns-file-to-fidelity-turbo0 Hello Everyone, I have been trying to import a mesh I made in CFX to fidelity using a .cgns format. I usually just click on the "import geometry, mesh or FINE Open Project" button above the CAD Tree > choose the .cgns file > Import mode (import mesh). The first warning I get is "The following cgns files c:\Users.... .cgns, are of type ADF. This file type is not supported since Fidelity 2022.1. Do you want to convert to HDF5?" then i click on yes. I then repeat the process, but with the newly created .cgns file, which leads to the following erros when I try importing it again: Warning : Inconsistencies found in imported mesh. Please, check the log file of the import mesh for more information. Import FINE project: R_C001_.cgns: NIImportFineOpenProject::updateTreeDo() no geometry container Importing the .igg file format of the same project works fine, however I get the follwing information: Mesh Setup 1 with volume mesh has been imported. Imported project contains the volume mesh available for viewing, although Mesh Setup settings are kept as Fidelity default values. I have been also experiencing troubles importing meshes in .cgns formats that I made in fidelity previously. This all leads me to believe, that I'm doing something fundamentaly wrong while importing meshes. Any Help would be much appreaciated. Thank you! https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59513/shape-to-void-conversion/1398724#1398724Sat, 15 Jun 2024 04:58:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398724somit/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59513/shape-to-void-conversion/1398724#1398724 No i don't think it is easy. https://community.cadence.com/cadence_technology_forums/pcb-design/f/design-entry-hdl/59541/plotting-to-pdf-in-design-entry-hdl/1398723#1398723Sat, 15 Jun 2024 04:56:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398723somit/cadence_technology_forums/pcb-design/f/design-entry-hdl/59541/plotting-to-pdf-in-design-entry-hdl/1398723#1398723 What is HDL file? https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/59578/need-help-extracting-net-alias-namesSat, 15 Jun 2024 00:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59578AB_1717543042707/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/59578/need-help-extracting-net-alias-names0 Hello, I want to see if there is a way to extract the aliases of a net using TCL. I believe the command I am looking for is GetNetAliasArray() however, I can not figure out how to get the output to readable text. The command GetNetAliasArray() returns DboPtrArray and I can't find the TCL helper command to convert this data type into text, if that's even how you do it. If anyone knows how to do this or if there is a different approach to this I would appreciate it. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59543/maestro-results-pane-order-undo-sorting-gray-out/1398722#1398722Fri, 14 Jun 2024 20:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398722Andrew Beckett/cadence_technology_forums/f/custom-ic-design/59543/maestro-results-pane-order-undo-sorting-gray-out/1398722#1398722 Ok, so you’re using the a broken version. The intention of this button is that it will restore the default order if you’ve sorted one of the columns, but a change in IC23.1 resulted in the button always being greyed out which was clearly a bug. That has been fixed but you’ll need to use a later hotfix version to get the fix - as I mentioned before. Andrew https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59543/maestro-results-pane-order-undo-sorting-gray-out/1398721#1398721Fri, 14 Jun 2024 19:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398721hdngo/cadence_technology_forums/f/custom-ic-design/59543/maestro-results-pane-order-undo-sorting-gray-out/1398721#1398721 Thanks Andrew! I did sort the column by accident. I am using version IC23.1-64B.43. Why do we have this function in the first place? I don't see any benefit of locking it up if the user accidently sorting the output. Thanks again! https://community.cadence.com/cadence_blogs_8/b/corporate/posts/the-history-of-electronics-in-sportsFri, 14 Jun 2024 19:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1363110Corporate/cadence_blogs_8/b/corporate/posts/the-history-of-electronics-in-sports0 In today's fast-paced world, technology touches nearly every part of our lives, including sports. Electronics play a pivotal role in athlete performance, training, and even fan engagement. As we gear up for the upcoming Olympics, we wanted to explore the fascinating history of electronics in sports, from their early adoption to the groundbreaking innovations that have transformed the industry. Milestones in Electronics that Transformed the Sports Industry The integration of electronics and sports began modestly. In the early 20th century, stopwatches and basic timing devices were among the first electronic tools to be used in professional sports. These early devices were crucial in providing accurate time measurements for races and competitions. In the 1960s, the introduction of electronic scoreboards revolutionized how games were viewed and followed. For the first time, fans could see real-time updates on the game, enhancing the viewing experience. From this modest beginning, the use of electronics in sports has evolved immensely over the years, including: Instant Replay CBS aired the first instant replay during the Army-Navy football game in 1963 . This innovation forever changed how sports were broadcast, allowing for better analysis and understanding of critical moments in the game. Heart Rate Monitors Polar introduced the first wireless heart rate monitor in 1977 . This device allowed athletes to monitor their cardiovascular performance in real-time, providing invaluable data for optimizing training regimens. Wearable Technology The 21st century saw the rise of wearable technology , with devices like the Fitbit and Garmin watches becoming household names. These gadgets track various physical activities and vital statistics, helping athletes and enthusiasts alike to monitor their performance and health. Hawk-Eye Technology Hawk-Eye, a computer vision system, was first used in cricket in 2001 . It has since expanded to sports like tennis and soccer, providing precise ball tracking and helping officials make more accurate decisions. The integration of electronics in sports has gone from simple timing devices to sophisticated technologies that enhance performance, accuracy, and the overall fan experience. These advancements have not only changed how sports are played and viewed but have also opened up new possibilities for future developments that can transform the landscape of sports even further. Successful Integration of Electronics in Professional Sports NFL and Instant Replay The NFL was one of the first sports leagues to adopt instant replay technology. This significant move has not only improved the fairness and accuracy of the game but has also enhanced the viewer experience by providing clarity on contentious decisions. Instant replay allows officials to review and correct calls, ensuring that the integrity of the game is maintained. Moreover, fans appreciate the transparency it brings, as they can see the reasoning behind decisions that might otherwise be controversial. This technology has set a standard that many other sports leagues have followed, proving its value in the world of professional sports. Check out the Cadence-49ers partnership to learn more about technology collaboration in sports. NBA and Wearable Tech The NBA has embraced wearable technology to monitor players' health and performance metrics. These devices track a variety of data points, including heart rate, movement, and sleep patterns. Teams use data from wearables to make informed decisions on player conditioning and injury prevention, allowing them to tailor training programs to individual needs and minimize the risk of overtraining and injuries. This technological integration ensures that athletes maintain peak performance while safeguarding their long-term health. Formula 1 and Data Analytics Formula 1 racing teams use data analytics extensively to gain a competitive edge. Sensors on the cars collect vast amounts of data in real-time, including metrics such as speed, tire pressure, fuel consumption, and engine performance. This data is then transmitted back to the teams' pit crews and engineers, who analyze it to make split-second decisions on strategy, pit stops, and adjustments that can significantly impact race outcomes. By leveraging advanced analytics, teams can optimize their performance and react swiftly to changing conditions on the track. Electronics also play a major role for Formula 1 racing behind the scenes during the design stage. Check out the Cadence-McLaren partnership to learn more about technology collaboration in sports. The Future of Electronics in Sports Emerging technologies promise to push the boundaries even further. Here are some potential future applications: AI and Machine Learning Artificial intelligence and machine learning algorithms are being developed to analyze vast amounts of data, providing insights that can enhance training programs and strategies. Advancements in semiconductor technology are driving progress in sensors, data analysis, and connectivity. Efficient data processing requires robust, fast AI semiconductor chips. Cadence's AI-enhanced EDA tools streamline high-end chip design, offering solutions like the Cadence SPICE simulation software for faster circuit design. Cadence supports rapid design and verification , critical emulation and prototyping, and provides Cadence Tensilica HiFi DSP for efficient AI processing in compact devices. Virtual and Augmented Reality VR and AR are set to revolutionize both athlete training and fan engagement. Athletes could use VR to simulate game scenarios, allowing them to practice strategies and improve decision-making skills in a controlled environment. On the other hand, AR could provide fans with immersive viewing experiences by overlaying real-time statistics and interactive elements onto live games, enhancing their understanding and enjoyment of the sport. This technological advancement promises to transform how we train athletes and experience sports as fans. Smart Fabrics Researchers are developing advanced fabrics embedded with sensors that can monitor various physiological parameters such as heart rate, body temperature, and muscle activity. These innovative smart fabrics could provide real-time feedback on an athlete’s performance, helping to prevent potential injuries and optimize training routines. By continuously tracking and analyzing data, these fabrics could revolutionize the way athletes train, offering personalized insights and enabling more informed decisions for better performance and health management. Exploring Technology Intersections The integration of electronics in sports has come a long way from simple timing devices to advanced AI-driven analytics. These advancements have not only enhanced athlete performance but have also significantly improved the fan experience. As technology continues to evolve, its impact on the sports industry will undoubtedly grow, making the future of electronics in sports an exciting frontier. Ready to explore where technology will take us next across various industry sectors? Join our blog community now and stay updated on the latest advancements in tech. https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59573/via-to-via-spacing-on-the-same-layer/1398720#1398720Fri, 14 Jun 2024 19:02:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398720techiecs/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/59573/via-to-via-spacing-on-the-same-layer/1398720#1398720 -SPB 17.4 Hotfix 28 (QIR4) onward, you can set the same net checks for via pads and holes(Same net Hole to Hole and Via to Via checks) by using the Allegro PCB venture license. -To set these checks, first, create the DFF CSet under Manufacturing > Design for Fabrication > DFF constraint set > Copper spacing and expand the 'Same net checks'. -After creating DFF copper spacing CSet and setting the CSet usage as Etch, assign this CSet to the referenced DFF CSet under Design for Fabrication > Design > Copper Spacing. -In analysis modes, enable the same net checks under Design For Fabrication > Copper Spacing. Similarly, under Design for Fabrication>DFF constraint set>Copper Spacing, there are checks for 'Vias' here. You might give it a try to see if it helps in your scenario to check via to via spacing. https://community.cadence.com/cadence_blogs_8/b/corporate/posts/cadencelive-silicon-valley-2024Fri, 14 Jun 2024 18:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1363061ErinGrant/cadence_blogs_8/b/corporate/posts/cadencelive-silicon-valley-20240 CadenceLIVE Silicon Valley 2024 was a notable event recently held at the Santa Clara Convention Center, drawing a diverse crowd of users, developers, and industry experts. This annual conference showcases the latest advancements in electronic system design and semiconductor technologies. The event featured a range of activities, including visionary keynotes from prominent figures such as Jensen Huang, CEO of NVIDIA, Cristiano Amon, CEO of Qualcomm, and Anirudh Devgan, CEO of Cadence. These keynotes delved into cutting-edge trends and innovations in AI, semiconductor technology, and electronic design. In addition to the keynotes, CadenceLIVE included numerous user presentations and technical sessions. These presentations covered solutions for current design challenges, with topics ranging from advanced silicon technologies to mixed-signal design. The event provided an opportunity for people from across the tech industry to learn from one another through peer-to-peer user presentations, interactions with Cadence experts, and conversations at the Designer Expo. Angie Hathorne and Nunio Villegas “Attendance at CadenceLIVE Silicon Valley was impressive and we personally spoke with many more customers than last year about Cadence Training.” said Angie Hathorn and Nunio Villegas from Education Services in North America, who were at the event in person to meet with customers again this year. Customers took the opportunity to learn about Training innovations and express their enthusiasm for the Cadence Online Training program, which has remained free of charge for Support customers beyond COVID—for which Cadence Training earns a lot of praise. With such positive customer feedback, it’s safe to say that Cadence Training communication resonates with customers and that Training is an important and accelerating wheel for users when it comes to upskilling, updating, and gaining technical expertise. At CadenceLIVE we spoke to many customers about the latest innovation, Bridging the Learning Gap . In today’s fast-paced technological world, learning or skill gaps are a real and recurring challenge. There is a very strong and real need for well-trained engineers in the semiconductor design industry, and whether you’re a new hire, a recent graduate, or an engineer changing jobs, you’ll need to become productive fast . What’s Your Gap? Being aware of a gap is one thing. Having access to efficient and well-structured solutions is another. And we wouldn't be Cadence if we didn't help you do something about it. Cadence Training has designed two new programs to bridge your learning gaps and to help you quickly become one of the skilled talents in the industry: Bridging the Learning Gap The Onboarding Curricula contains six training recommendations for Custom IC/Analog/RF Design , PCB Design , and Digital Design . Please be aware that you can gain your single digital badge for almost all single courses assigned to this Onboarding Curricula . Speaking now about the Tech Domain Certification Programs , which contains Training collections for specific design domains – a student can take the collection of courses for a specific technology domain and claim one badge per course as well as an additional digital badge for that specific domain. At the moment, this program is available for Digital Design and Verification , but there are more to come shortly! For those who missed the in-person event, CadenceLIVE offers an on-demand site that provides access to recorded sessions and additional resources. This hybrid approach ensures that the insights and innovations shared at the conference are accessible to a broader audience. For more details, visit the official CadenceLIVE site. https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59553/how-to-utilize-the-dbids-i-got-from-dbgettrueoverlaps/1398719#1398719Fri, 14 Jun 2024 18:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398719dakuang01/cadence_technology_forums/f/custom-ic-skill/59553/how-to-utilize-the-dbids-i-got-from-dbgettrueoverlaps/1398719#1398719 Hi Andrew, I've been trying a few methods to approach the cells with the cellname "abcde_*" but I ran into issues. Basically, the question you asked is the very issue I'm having. Depending on the hierarchy of the layout, I don't know how to figure out where the cells are in the data. The only thing I know is the leaf object and the cell I'm looking for are the elements of the very bottom of the concatenated list in hierarchy-wise like the image I attached before. They're in the same level. Or do I need to check every single element whether each element is "inst" or "mosaic" with the cellname I'm searching? I might need to use a recursive function. And I'm not very familiar with it. Any advice? Please help me! Thanks, dakuang01 https://community.cadence.com/cadence_technology_forums/computational-fluid-dynamics/f/turbo/59577/cpu-time-in-omnis-turbo/1398718#1398718Fri, 14 Jun 2024 16:31:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398718gs_cfd_cdn/cadence_technology_forums/computational-fluid-dynamics/f/turbo/59577/cpu-time-in-omnis-turbo/1398718#1398718 In the case of Open Solver, navigate to the output and select the fourth option. The screenshot is attached for reference. But in the case of Turbo solver, you need to check with the command manager. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/59562/mobility-and-cox-value/1398717#1398717Fri, 14 Jun 2024 15:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398717Maria98/cadence_technology_forums/f/custom-ic-design/59562/mobility-and-cox-value/1398717#1398717 Thank you for the reply. Actually, I wanted to theoretically calculate the results that I got from the basic simulation. Mobility and cox values are often required in basic calculations. The primitive device model is bsim4. There are two parameters: ron and rout with 52.41 and 51.15 respectively. Which one should be considered? I tried to simulate Ron by putting a port on the drain side of a single transistor and calculated Ron through z11 real part, which is 56.73ohm. (with the required bias conditions of 1.2V at gate and 0V at drain). can I consider it as Rds? Meanwhile, the Rgate is also found zero in the DC operating point list! How can I verify both values, Rds and Rg of the simulated transistor model for the calculation of theoretical equations of basic circuits? Thank you https://community.cadence.com/cadence_technology_forums/f/pcell-designer/59569/locating-pcell-designer/1398716#1398716Fri, 14 Jun 2024 15:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398716dandadom/cadence_technology_forums/f/pcell-designer/59569/locating-pcell-designer/1398716#1398716 Thank you Andrew, I appreciate the help! https://community.cadence.com/cadence_technology_forums/f/pcell-designer/59569/locating-pcell-designer/1398715#1398715Fri, 14 Jun 2024 15:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398715Andrew Beckett/cadence_technology_forums/f/pcell-designer/59569/locating-pcell-designer/1398715#1398715 Dominik, You would need to download the PCD25 (latest hotfix) release from http://downloads.cadence.com and there's a video on installing it here: Installing Cadence PCell Designer (you'll also find other videos in the channel on the right hand side with that link which give introductions). There's a couple of rapid adoption kits too: Generating a Layout Parameterized Cell using PCell Designer - Basic Generating a Schematic Parameterized Cell using PCell Designer Plus the reference manual can be found in the Custom IC Design section of the Product Manuals page. Andrew https://community.cadence.com/cadence_technology_forums/computational-fluid-dynamics/f/turbo/59577/cpu-time-in-omnis-turboFri, 14 Jun 2024 13:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59577cfd enthusiast/cadence_technology_forums/computational-fluid-dynamics/f/turbo/59577/cpu-time-in-omnis-turbo1 Hello everyone, in Omnis when i run a simulation I can see the simulation time in the command manager. However I am not sure if I am seeing the CPU time or total Time, since it is only called elapsed time. Also I can't find the elapsed time in the log files of the simulation. Is it called differently? Thank you! https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/59558/syscap-power-object-name-don-t-change/1398714#1398714Fri, 14 Jun 2024 13:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398714rg13/cadence_technology_forums/pcb-design/f/allegro-x-system-capture/59558/syscap-power-object-name-don-t-change/1398714#1398714 VDD is just a note/text on symbol graphics to recognize the power symbol named VDD. While placing the power symbol on schematic, it asks you to name the power/ground net and its voltage value. Whatever name you give here, will be the name of connecting power net. Hope it clarifies! NOTE: To change the symbol graphics, you can open the Part developer (PDV) and can change the text over there. https://community.cadence.com/cadence_technology_forums/pcb-design/f/licensing-and-installation/59571/orcad-x-on-arm-architecture/1398713#1398713Fri, 14 Jun 2024 12:47:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398713rg13/cadence_technology_forums/pcb-design/f/licensing-and-installation/59571/orcad-x-on-arm-architecture/1398713#1398713 Currently for OrCAD X , here is Hardware requirement: For more details about Hardware and Software requirement for Orcad X, you can refer following link of Cadence online support portal: Cadence OrCAD X and Allegro X 23.1 Installation Guide for Windows -- Hardware and Software Requirements https://community.cadence.com/cadence_technology_forums/system-analysis/f/sigrity/59576/sigrity-tip-of-the-day-how-to-simulate-tabbed-routed-shapes-by-using-a-new-feature-in-sigrity-powersiFri, 14 Jun 2024 10:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:59576SimTech/cadence_technology_forums/system-analysis/f/sigrity/59576/sigrity-tip-of-the-day-how-to-simulate-tabbed-routed-shapes-by-using-a-new-feature-in-sigrity-powersi0 Hello there! Are you struggling with simulating tabbed routed, or arc routed shapes in your PCB layouts? Well, we have a solution for you! We understand that hybrid-engine-based tools might not provide the expected results when dealing with complex structures, and full-wave solvers can be computationally expensive. That is why we have introduced an additional functionality in PowerSI to call the Clarity IE solver to solve the selected arc routing and tabbed routing shapes. In PowerSI, you can now use the Clarity 3D-IE solver feature to generate accurate simulation results while creating cutting polygons for parallel tab traces. To do this, select the Enable Cutting Clarity Block (ClarityIE license required) check box from the Special Handling page in the Options dialog box. Then, select the tabbed routed or arc routed shapes by using the cutting boundary option and import them into Edit Cutting Clarity Block . Once you have done that, run the PowerSI simulation, and the shapes within the cutting boundary will be simulated using the Clarity IE solver, providing an accurate solution. This feature will help you streamline your simulation workflow, reduce errors, and increase productivity. Try it today and share your experiences and questions in the comments below. Happy simulating! Team SimTech Cadence Design Systems https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59566/how-to-select-all-floating-wires-in-a-schematic-both-connected-to-terminals-or-not-connected-to-a-terminal/1398712#1398712Fri, 14 Jun 2024 10:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398712AurelBuche/cadence_technology_forums/f/custom-ic-skill/59566/how-to-select-all-floating-wires-in-a-schematic-both-connected-to-terminals-or-not-connected-to-a-terminal/1398712#1398712 No need to apologize, I was just surprised [quote userid="273143" url="~/cadence_technology_forums/f/custom-ic-skill/59566/how-to-select-all-floating-wires-in-a-schematic-both-connected-to-terminals-or-not-connected-to-a-terminal/1398707#1398707"]There is no indication that this question relates to a schematic.[/quote] You cannot say that though... https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/59566/how-to-select-all-floating-wires-in-a-schematic-both-connected-to-terminals-or-not-connected-to-a-terminal/1398711#1398711Fri, 14 Jun 2024 10:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1398711AurelBuche/cadence_technology_forums/f/custom-ic-skill/59566/how-to-select-all-floating-wires-in-a-schematic-both-connected-to-terminals-or-not-connected-to-a-terminal/1398711#1398711 Here's the code that get the floating wires using schCheck tramt don't hesitate if you have questions about it as this can appear complex SKILL++ if you are not familiar with Scheme ;; `inScheme' used as this is SKILL++ file ;; if current file extension is .ils, this can be skipped ( inScheme ( let () ( defun get_floating_wires (cv) "Run `schCheck' to extract CV connectivity then return the list of wires having an associated 'floating' marker" ( schCheck cv) ( foreach mapcan marker cv -> markers ( and ( pcreMatchp "floating" marker -> msg ( pcreGenCompileOptBits ?caseLess t )) ( forall obj marker -> objects ( equal "line" obj -> objType)) marker -> objects ))) ( defun get_connected_wires (wire) "Return the list of wires connected to WIRE (including itself)" ( let ((done_wires ( makeTable t nil )) (to_do_wires ( list wire)) ) ;; to_do_wires is a list of all wires whose neighbours have not been fetched yet ;; wires in this list are processed one by one until the list is empty ( while to_do_wires ;; Fetch next wire to process, mark it as done immediately to avoid ;; reprocessing it ( setq wire (pop to_do_wires)) ( setf done_wires[wire] t ) ;; Add connected wires that have not been processed yet to to_do_wires list ( foreach obj ( dbProduceOverlap wire -> cellView wire -> bBox 0) ( when ( and ( equal "line" obj -> objType) ( equal obj -> net wire -> net) ( not done_wires[obj]) ) (push obj to_do_wires) ))) ;; Return the list of done wires done_wires[?] )) ( defglobalfun ab_select_floating_wires ( @key (cv ( geGetEditCellView )) @rest _ ) "Select floating wires in CV (this implies running `schCheck' which extracts connectivity)" ;; Make sure input cellview is a schematic one ( assert ( equal "schematic" cv -> cellViewType) "Not a schematic view: %s/%s/%s" cv -> libName cv -> cellName cv -> viewName) ;; Fetch and select floating wires ( mapc ' geSelectFi g ( mapcan get_connected_wires (get_floating_wires cv))) ) ) ;closure ) ;inScheme