https://community.cadence.com/search?q=*%3A*&category=blog&users=2782&sort=date%20desc&Redirected=trueen-USTelligent Community 12en-usnoSearch results for '*:*' by user ID 2782https://community.cadence.com/cadence_blogs_8/b/fv/posts/the-challenge-of-system-integration-and-bring-upTue, 03 May 2011 20:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1268016Ran Avinun/cadence_blogs_8/b/fv/posts/the-challenge-of-system-integration-and-bring-up0In the last few years, I have talked with many companies and analysts and consistently heard that system integration time is becoming one of the key challenges in system development. Many companies spend 50% of their total development cycle on system integration and bring-up. This blog will describe the key challenges customers face today, and will refer to a new Cadence approach and offerings to address them. Post-Silicon System Integration and Bring-Up The flood of application-driven devices forces semiconductor and system companies to embed multiple processors and millions lines of code into their devices. We (the consumers) demand new products with enhanced capabilities and shorter development times. Many of the system companies are still using silicon prototyping boards as the main vehicle to integrate their environment. Obviously, this approach creates major risk for them, since any major hardware change found at this phase requires board and silicon iterations, not to mention that debug at the lab using silicon prototyping is painful. The days of getting first silicon as the key goal are over. The desire of any electronic company is to minimize the time from silicon prototyping to volume, and the first step to get there is to minimize the time to first working silicon with first working software. The final system integration phase is mostly done when your channel (the marketing organization, distributors, retailers and others) is making the final preparations for product launches. Accurate predictability for the release date at this phase is very critical for the project. Any iteration at this phase can cause significant delays in product introduction and as a result could cost tens of millions of dollars (see the chart below). . Source: IBS 2010 System companies need to use hardware-aware software development tools that allow early software development and testing of the full system. The tools need to support interactions with the semiconductor companies, and therefore enable them to start and validate their product pre-silicon. Pre-Silicon System Integration and Bring-Up: In order to mitigate the system integration risk and reduce post-silicon system integration time, semiconductor (and system) companies need to use hardware/software platforms at the pre-silicon phase. They also need to start to interact with their customers (the system companies), share some of these platforms with them and create a handshake process that will allow them to discover and fix quickly potential hardware software issues early in the design phase. Unfortunately, there is no single product that can optimally serve all system development design phases. Each phase requires a different platform optimized for the specific task, and therefore a comprehensive set of platforms is required. Many of the bring-up tasks as you migrate from one platform to another are very similar -- however, users were forced in the past to manually create their own scripts and "re-invent the wheel" as they moved into a new design phase. Customers would like to re-use their environment including many side files, compile, debug, verification IP, real-world interfaces and the preparation work they have done as they migrate from one level of abstraction to another or one design phase to the next one. Tight connections among pre-silicon system development platforms and the ability to use standards and plugged-in third-party tools are required. Finally, it is important to create these platforms in a way that allows hardware and software developers to interact, and therefore addresses their scalability needs in terms of capacity, performance and affordability for volume distribution. Cadence Solution The Cadence System Development Suite (illustrated below) introduced this week addresses many of the system challenges mentioned above with the goal to reduce both pre-silicon and post-silicon bring-up and integration time by up to 50%. Please visit us this week at CDNLive! EMEA in Munich or at the Embedded Systems Conference in San Jose to see demonstrations of the new hardware/software platforms and the integrated solution we have introduced.https://community.cadence.com/cadence_blogs_8/b/fv/posts/why-the-demand-for-acceleration-and-emulation-is-growingMon, 14 Feb 2011 19:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1250319Ran Avinun/cadence_blogs_8/b/fv/posts/why-the-demand-for-acceleration-and-emulation-is-growing2The dream of any marketer is a growing demand for its product line. Let me start this blog by quoting the System Realization (part of the Cadence EDA360 strategy) section from the transcript of the recent (Q4) Cadence earnings call. "In April (2010), we introduced the Verification Computing Platform, enabling emulation, acceleration, and simulation all on one single platform. Customers who are designing SoCs at 40nm and below find this product necessary to meet the time-to-market and quality targets. Demand for this product was exceptionally high in the fourth quarter, the result of the expanded orders from existing customers and new customers who used the platform to bring out some of this year's most extraordinary products." Anytime the economy is recovering from a recession, we see the demand for semiconductor devices growing, and with it this increased demand for acceleration and emulation. Last year, we have seen an even sharper increase in the demand for these products at Cadence. Why? Let's talk about some of the market trends: 1. Most of the new SoC devices are embedded. With the smart phone (both iPhone and Android-based phones) and ARM-based design "Tsunami," the potential revenue (produced by the semiconductor and the system companies) in terms of both upside and risk is larger than ever. Overall, there is a reason why the market capitalization of Google and Apple combined is above $520B, and ARM market capitalization just hit today $14B. 2. Any new embedded device has more software than hardware and for the HW-dependent software layers, you can't start software development until you have matured hardware. HW/SW and embedded system integration is becoming the critical path in any system development. 3. The hardware portion of new embedded devices is more complex and mostly includes multiple cores. In a recent discussion with one of our customers, he said: "In the past, during the debug process, I could point into the specific line of software code which was the root cause of the hardware failure. Today, when I have 12 cores in the design with multiple operating systems, it is very difficult to find the root cause for a particular failure manually. I need to rely on tools for automation and even if I have it, it is a complex task". Simulation used to be the key tool for block and SoC verification. In the new world, where you have many external interfaces to your device, a lot of SW and a huge complexity in integration, your simulation performance can't keep up with the requirements. Unlike in the past, hardware-assisted verification is a must have. 4. The growing business demand (which in many cases is pushed by us -- the end customer) creates huge pressure to hit the shipment window on time. Therefore, the demand for HW/SW development platforms and high-performance simulation acceleration platforms for verification acceleration is growing. So why is it that the demand for other platforms (such as FPGA-based prototyping and/or virtual prototyping) is not growing at the same rate? I believe that overall, the demand for all HW/SW platforms and SoC/system integration tools is growing. However , acceleration and emulation still has unique value propositions : 1. A larger percentage of designs are crossing the 64 million gate range. Emulation is still the most convenient way and maybe the only way to port and validate such large designs (hardware and software) at a cycle accurate level. Yes, it is true, if you mostly need to test the SW independent layers and you do not particularly care about cycle accuracy, there are other methods to do it. However, with the hardware dependent layers, corner cases at the RTL/gate level are the ones that eventually can delay your system delivery. 2. With the ease-of-use improvement and the large number of available SpeedBridge adapters, emulation bring-up is a task that can take now days for most designs. Therefore if you have the majority of your design defined in RTL, this is the fastest way to get to system validation. 3. The new methodologies (OVM and UVM) are very efficient; however, they are running out of steam as you get to the SoC and system level. SoC verification is not scaling any more if you just use simulation. In parallel, the new standard methodologies (combination of UVM acceleration and SCE-MI) made it much easier to port designs in simulation and run them in acceleration. Moving forward, HVL-based simulation acceleration could have a huge opportunity to grow. 4. Within the last 20 years, a lot of emphasis in emulation was put on debug, to the point that today in many cases the debug in emulation is as simple (or maybe more efficient) for large designs than in simulation. Add on top of the above a new platform from Cadence ( Palladium XP , Verification Computing Platform) supporting performance speed that has not seen in the emulation business for a long time, hot-swap to and from the Incisive Enterprise Simulator, scalable capacity, very fast turnaround time as a result of fast compile time, and low power verification and analysis capabilities -- and this demand for acceleration and emulation will not surprise you any more. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/system-level-design-and-verification-industry-trends-part-iiTue, 28 Dec 2010 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1247273Ran Avinun/cadence_blogs_8/b/fv/posts/system-level-design-and-verification-industry-trends-part-ii02010 was a very dynamic year for the electronic systems industry overall and Cadence in particular. In this set of blogs, I discuss some of the trends that started in 2010 and will continue in 2011. In part I, I talked about the key growth market, key industry challenges and the role of EDA. In this blog post (part II), I will talk about Cadence offerings addressing these challenges. Cadence System Design and Verification -- Addressing IP Productivity and System Integration In order to be successful, the System/SoC companies need to improve two key parameters in their system development: 1. Development (creation and reuse) productivity of differentiating core IP 2. SoC/System and IP integration (including HW/SW and multi-IP verification/validation) At Cadence, we look at system-level design beyond the narrower focus of ESL. We are focusing on the customer's challenges to realize a new system. Although it is important to drive the flow from the application/software level and the specifications definition phase, ESL is one piece of the solution and not the whole solution. We believe that the problem needs to get addressed by multiple components of the flow, must be connected to the mainstream (core EDA) flow, and needs to be developed based on a set of open, standards-based solutions. We believe the solution needs to be scalable and should rely on an expansion of existing products and methodologies available in the market. To address the key challenges mentioned above, Cadence's short-term systems strategy focuses on two vectors: 1. Move design and verification to a higher-level of abstraction to enhance productivity and predictability . In 2010, we introduced the industry's first TLM-driven Design and Verification methodology book with a focus on IP design and verification to articulate our recommended methodology. It includes a top-down design flow with examples based on the C-to-Silicon Compiler high-level synthesis (HLS) tool, which works with an embedded Encounter RTL Compiler and the Calypto SLEC System-HLS equivalence checker. It also provides an optimized path to Altera and Xilinx FPGAs and to Cadence Palladium Series / Palladium XP emulators. Other unique features build into this methodology include Engineering Change Order (ECO) capabilities that combine C-to-Silicon and Encounter Conformal ECO together with a top down metric-driven verification flow based on the Incisive Enterprise Simulator and the OVM / UVM methodologies. Feedback about the flow and the methodology has been provided by industry experts Grant Martin and Brian Bailey, and companies such as Casio , ST , TI and Fujitsu . In 2011, we are planning to proliferate and enhance the above flows with a focus on ease-of-use to provide faster time-to-RTL, enhance quality of results (QoR) and improve the TLM-to-GDS flow. We are also going to extend these flows beyond a single IP block. One of our key challenges is to educate the industry (and the individual teams) about C++/SystemC to make them comfortable with the new flows. The good news is that we are starting to see large companies building the infrastructure to support these flows. 2. Provide an integrated HW/SW development solution to improve quality and time-to-market . As I have stated above, System/SoC (HW/SW), IP integration and bring-up time are becoming the bottlenecks in any new complex digital design, especially in the consumer market. Pre-silicon HW/SW development platforms are becoming an essential part of the system integration and validation phase. They enable performance and capacity scalability and provide a vehicle to verify and debug your hardware and software. In 2010, we have seen significant increase in the demand for System/SoC integration, verification and validation. RTL testbench simulation alone can't address the full system verification problem as a result of increased HW design complexity and the popularity of embedded processor/cores. HW-assisted verification plays a major role here and is currently the largest commercial revenue component that can address these challenges. In 2010 Cadence introduced the Palladium XP Verification Computing Platform, which combines simulation, acceleration and emulation into a single platform. It provides, for the first time, impressive emulation performance that can reach 4 MHz while maintaining the strengths of Palladium emulation and Xtreme acceleration. Palladium XP received feedback from customers such as nVidia and Nethra Imaging . Starting in 2010 and continuing in 2011, we are expending the traditional emulation and transaction-based acceleration use models adding Metric-Driven Verification and low-power verification and analysis. Some examples for these flows can be provided through presentations from ARM , Freescale , TI and Broadcom . 3. With the need to rely on outsourcing and external IP and the pressure to integrate multiple IPs quickly into an SoC, Verification IP is becoming a "must have". Cadence continues to expand its portfolio with 3 dimensions: a. Expansion of the core testbench simulation Verification IP leveraging Denali IP and our internal VIP. b. Expansion of Verification IP to support multiple levels of abstraction and multiple platforms. c. Expansion of our rich SpeedBridge portfolio and "real world" interfaces. 4. As we have discussed above, we at Cadence can't do it alone and therefore need to partner with others in order to deliver a complete flow. In this section, I will focus on the ecosystem . In 2010, Cadence announced its System Realization collaboration with Wind River and ARM and its contribution to the TSMC ESL reference flow 11 . Later on, we have introduced the System Realization Alliance with 20+ partners. These partners including IP, Software, EDA and service providers (including education and training) companies. In the last few months, we have delivered together with these partners multiple webinars to educate the market with the new technologies and the mutual flows with Cadence. These companies include Xtreme EDA, CircuitSutra, Imperas, Calypto, ARM, TSMC, CoFluent, Jeda Technologies and Magillem. You should expect to see more collaboration in 2011between Cadence and the System Realization Alliance members. Finally, Cadence continues to be very active in driving some of the key system standardization activities including Open System Initiative ( OSCI) with its focus on TLM-2.0, SystemC synthesizable subset, and overall interoperability; SystemC IEEE 1666 ; Accellera with its focus on the I nterface Technical Committee (developing standard co-emulation API -- SCE-MI which is migrating now to 2.1); Unified Coverage Interoperability (UCIS); IP-XACT ; Verification IP interoperability and UVM . I wish all of you a happy new year. As always, I am interested to hear your feedback. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/system-industry-trends-quick-look-at-2010-highlights-and-upcoming-2011-part-1Thu, 16 Dec 2010 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1247272Ran Avinun/cadence_blogs_8/b/fv/posts/system-industry-trends-quick-look-at-2010-highlights-and-upcoming-2011-part-112010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I will talk about the key growth markets, key industry challenges, and the role of EDA. In the next blog (part II), I will talk about Cadence offerings addressing these challenges. Key Growth Market -- Application-Driven Internet Mobile The introduction of Apple's iPad, the continuous success of the Apple's iPhone and the new growth of Google Android based phones propelled the Internet mobile industry in 2010. According to IDC , application-enabled devices will soon overtake PC shipments, reaching 462 million global shipments in 2012 (vs. 448 million PC shipments in the same year). The drivers for this usage are the content providers and their "apps." Companies such as Facebook (with 500M+ subscribers), movie/video streaming provider Netflix (16M+ subscribers) and the Apple Apps Store (reaching a $1.4B economy and growing at a faster rate than the number of Internet subscribers in 1994-1996) are forcing the system companies (and to some extent the semiconductor companies) to innovate and deliver new products based on new technologies. So definitely, if we look at key growth areas, we should look at mobile Internet, its ecosystem, and expanded industries including the communication infrastructure, cloud computing, gaming and other Internet-based multimedia devices/applications. The EDA360 vision paper published by Cadence in 2010 articulates the market requirements as we migrate to applications-driven devices. This vision paper analyzes the macro trends happening in the electronics industry (including IP, Semiconductor, Software, System and EDA companies) and calls for an action and tight collaboration among the different providers in order to optimize System, SoC and Silicon Realizations. Key Industry Challenges -- Time-to-volume and Time-to-Integration In order to address the demands and trends mentioned above, semiconductor and system companies are facing major time-to-market challenges. Their customers (the content providers and their end users) are asking for faster, lower-cost, lower-power mobile Internet devices that can be always-on and work reliably, running a variety of software applications. The software content (in all layers) is exceeding the hardware content, and the end devices are becoming more complex and are requiring multiple processors and many IP blocks. Many devices must provide secured payment transactions and high bandwidth multimedia/video applications through wireless connections, while providing high quality of service. System design companies are under pressure to change the way they design, verify and integrate. In the past, their focus was on process, back-end optimization, application-specific solutions with differentiation provided through few hardware IP components that were the core for their business. Today, the focus of the system companies is shifting into device optimization for set of software applications and time-to-volume (the ability to ship on time a large volume of devices that will be able to run the applications described above in an optimal and reliable way, at the right cost and power consumption with competitive features). As the development cycle shrinks into 6 months and integration takes 3-4 months, one of the key challenges is the ability to integrate and deliver a new competitive consumer product (including hardware and software) that will hit the market on time. The EDA role -- More Than a Technology Provider The EDA industry has a major role solving the key system/SoC challenges mentioned above. As Cadence stated many times within the past year, one company can't do it alone. This should be an industry effort with collaboration of multiple companies. In the last 10 years, the EDA industry initiated a new approach (system-level design, using a higher level of abstraction) in order to solve integration and productivity issues. During this timeframe, new ESL (Electronic System Level) technologies have been introduced. Some of them were ready to be deployed only recently. Many of the semiconductor companies who ignored these technologies, or had a perception that these technologies are too risky in the past, are now becoming believers and therefore building the infrastructure to deploy them. Others are looking for any new solution that can help them to be more productive. One of these technologies is high-level synthesis, which helps tremendously to increase design and verification productivity through faster IP creation , reuse and faster exploration . When we (Cadence) introduced a new High-Level Synthesis (HLS) product, C-to-Silicon Compiler, to the market 2 years ago, the common questions from the customers were: "What are the potential benefits of HLS? Which standard language is going to evolve? Why should we look into this? How do I know that my Quality of Results (QoR) is going to be at least as good as hand-written RTL?" By now, SystemC (with C/C++ as a subset) has been accepted as the standard language for high-level design. The key U.S. companies started to acknowledge the value of HLS, and many of the HLS tools are providing good QoR. In 2010, the questions were more along the line of "how can we integrate this technology with our mainstream flow? What do we need to do in order to prepare our infrastructure to use it? How can we educate our engineers so they will be able to use it? Which methodology should we apply?" I give this as an example to show that EDA providers are becoming more than just technology providers. High-Level Synthesis is just one (albeit important) piece of the puzzle, and it is important for any EDA company to have this technology in order to have key competitive advantages in its portfolio. However, it is as (or more) important for the EDA companies to understand the challenges the IP developers and SoC/system integrators face in order to deploy this technology within their existing flows, and the ecosystem required for deployment. HLS requires integration with other aspects of the flow such as functional verification and TLM-to-GDS design. It requires a network of service providers or design houses and developers who understand this flow. It requires SystemC education of the previous generation (or next generation). And it requires that hardware engineers have a desire to move to the new flow/methodology. In my next blog, I will talk about Cadence offerings addressing these challenges. I wish all of you Happy Holidays. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/system-integration-the-critical-path-in-system-development-processTue, 09 Nov 2010 16:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1228470Ran Avinun/cadence_blogs_8/b/fv/posts/system-integration-the-critical-path-in-system-development-process0The electronic industry is moving from hardware-defined products to software-defined and application-driven products. As a result, product differentiation shifts to software content while hardware platforms and their development processes increasingly become increasingly commodities. Time-to-market pressures and the trend toward software-defined product functionality make the traditional sequential process – SoC/System development followed by board and device development followed by software development – obsolete. SoC/System development requires the integration of many components including main processors, application-specific processors, peripherals, memory, graphics and multiple layers of software where the components themselves include sub-systems and are developed by a diverse set of multi-tier suppliers. The heterogeneous operating principles of the components, their enormous, deeply sequential complexity, and complex HW/SW protocol stacks pose challenges to the system companies they have not encountered before. In addition, compared to the past, the systems and sub-systems must now be developed with a reduced workforce that is increasingly globalized across company and geographical boundaries. Time-to-market is the number one challenge in the system development. System companies are under pressure to meet their market window and to reduce their overall design cycle. Currently, they spend 50% of their development time in HW-SW system integration and bring-up. The key problem is debug. Once you find a problem in your design, you would like to be able to get visibility into the hardware and the software and quickly be able to find out the root cause of the problem, fix it, recompile and re-run the design again. In his latest blog , Brian Bailey gave an excellent overview about the variety of use models of acceleration and emulation. 7 months ago, Cadence introduced the industry's vision, EDA 360 , including System Realization . Within the System Realization domain, we have announced our new Verification Computing Platform -- Palladium XP. The first 7 month period was a home-run for Palladium XP at Cadence and a great success. Why is that? As mentioned above, system integration, validation, debug and bring-up are the key bottlenecks in the system development process. In the current semiconductor competitive environment, customers are pressured to get their product to the market early while meeting the functionality, quality and specifications. You can tape-out your silicon successfully -- however, if your software is not running correctly on top of your hardware, you can not ship the product. Acceleration/emulation is still the main method to validate your full design (HW/SW) especially for high complex designs. The Cadence Verification Computing Platform is addressing many of the problems above with combined simulation, acceleration and emulation capabilities. To hear more from our customers, watch the following Videos: nVidia , Nethra Imaging. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/migrating-from-fpga-based-prototyping-to-palladiumTue, 02 Nov 2010 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1217283Ran Avinun/cadence_blogs_8/b/fv/posts/migrating-from-fpga-based-prototyping-to-palladium0In recent posting published by John Cooley on Deepchip.com, users compared FPGA-based prototyping systems to Palladium systems. I always like to read responses that reflect user views -- as we all know these are always more credible. I would like to summarize the inputs to this posting here: Key Palladium benefits mentioned: 1. Fast Tunaround/Build time (after you find a bug) takes minutes in Palladium vs. hours/days for FPGA-based prototyping. The faster times increase productivity. No dedicated engineer needed for Palladium compilation - "everybody can do it." 2. Visibility into all registers, nets and memories with large trace depths saves debug and emulation time. Finding more bugs (3-4X) with fewer people (1/2). 3. Configurable -- can maintain multiple versions of the design in a simple way in Palladium 4. Multi-user capability helps testing in parallel multiple sub-systems 5. TCL scripting automates compilation process 6. SpeedBridge adapters automatically adjust the external live interfaces for emulation speed 7. Can be used for SW development and boot-up OS earlier (when RTL is generated, even is it is unstable) 8. Scalable capacity 9. Predictable performance 10 . Lower cost of ownership (resources for support) and higher reliability Key FPGA-Based prototyping benefits: 1. Higher performance/speed reduces run-time, especially when the design is more stable and SW development is the primary use model. 2. Cost of materials - if you need multiple platforms as replicants 3. Can run at real-time in some situations In general, the conclusion of most of the users is that these two solutions are complimentary to each other and being used in different phases of the design development process. It would be nice if there was more automation from one system to another. If you have more comments and did not provide a submission to John, I will be interested to hear from you here. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/cdnlive-israel-and-usMon, 25 Oct 2010 14:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1196159Ran Avinun/cadence_blogs_8/b/fv/posts/cdnlive-israel-and-us0The Cadence Design Network provides a great way to learn about the latest design and verification methodologies offered by Cadence, and the ways customers are using them. I had the pleasure to attend CDNLive! in Israel last week. For me, visting Israel is always an exciting time. In addiiton to the fact that I have a lot of friends and family there and the food is great, it is always facsinating to see such a small country with so much influcence on our industry. Most of the large electronic companies (Intel, Broadcom, Marvel, TI, Freescale, Samsung, Qualcomm and the list goes on and on) have subsidaries in Israel with major R&D contributions. In addition, there are always discussions about new ventures and start-ups -- although during my last visit, I noticed that the number of new fabless semiconductor companies has decreased. Rony Friedman from Intel was one of the keynote speakers at CDNLive! Israel. In his talk, he emphasized the need to use HW/SW platforms (including emulation, FPGA-based prototyping and virtual platforms) throughout the development process and looked at this task (system integration) as one of the key challenges in the industry and a new opportunity for the EDA companies. For the first time, Cadence created an embedded software track in this event, presented in collaboration with ARM, WindRiver and GlobalLogic. Please comment on this blog and let me know if you are interestd in attending such tracks in other Cadence events, and we will add these to our agenda in the future. This week (Oct 26th and Oct 27th), our CDNLive! comes to the US (Silicon Valley) and we have a great program here. If you are interested in topics related to System Realization, I would encourage you to attend the following sessions: Oct 26th (Fairmont Hotel in San Jose): Oct 27th (Cadence San Jose campus) - Cadence techtorials: See you all at CDNLive! Silicon Valley. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/silicon-hive-cto-how-transaction-based-acceleration-speeds-ip-verification-and-prevent-digital-tv-quot-crashes-quotMon, 02 Aug 2010 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:648849Ran Avinun/cadence_blogs_8/b/fv/posts/silicon-hive-cto-how-transaction-based-acceleration-speeds-ip-verification-and-prevent-digital-tv-quot-crashes-quot0Jeroen Leijten is Chief Technology Officer for Silicon Hive , a Dutch company that has quickly become one of the world's leading intellectual property (IP) providers of imaging and video processing solutions for rapidly changing market segments such as connected, interactive digital televisions and smart phones. Silicon Hive programmable parallel system solutions are licensed by semiconductor companies such as Samsung, LSI and Intel. Silicon Hive engineers recently implemented a use model called"transaction-based acceleration" (TBA) with the Cadence Palladium III accelerator/emulator to verify some of Silicon Hive's most advanced multimedia system IP solutions (including hardware and software). Jeroen recently sat down to talk with us about his team's work. Q: Jeroen, can you tell us more about Silicon Hive? A: Silicon Hive is a worldwide, independent supplier of semiconductor intellectual property. Our company designs, builds and licenses application-specific system solutions for imaging, video processing and communications using our programmable HiveFlex parallel processor cores, complete vertical HiveGo imaging and video system solutions, and HiveLogic platform. HiveLogic and HiveGo system solutions are supported by HiveCC programming development tools, and by partner-supplied application libraries provided by Silicon Hive and its partners. Our products enable semiconductor and consumer electronics companies to create and integrate fully programmable SoCs, thus improving time to market performance. As we develop our products, we maintain full programmability and field-upgradeability within the cost and power constraints required in our target market segments. Our patented technology originates from 10 years of research and development within Philips Research Laboratories. Silicon Hive spun out of Philips in 2007. Q: What markets is Silicon Hive going after today? A: Our HiveGo VSS (Video System Solutions) aim at the digital televison (HDTV) market, while HiveGo CSS Camera Sub-Systems Solutions are focused on smart phones and multimedia phones. We are one of the very few companies who can deliver the complete image processing chain all the way from sensor to codec, including all the software. Our solutions deliver up to 20 million pixels resolution up to 30 frames per second. We also license our HiveFlex processors standalone together with all the necessary software development tools. However, interestingly, customers today are asking for this less often, preferring full HiveGo system solutions where Silicon Hive and its customers customize and integrate customer's proprietary software. HiveGo CSS imaging solutions are used in wireless handsets. When you consider that more than one billion mobile phones are sold each year, and a rapidly increasing share of these now contain some sort of camera, you start to understand the market potential here. The Digital HDTV market, Internet digital video and connectivity are changing the functional requirements rapidly. The inherent flexibility of our architecture is a big advantage in this market for us, because Internet video codec standards continue to evolve rapidly, changing as frequently as every three months. This really requires software programmability. Q: What do you see as the critical requirements in order for Silicon Hive to win in the digital TV market? A: Like most consumer applications, cost is perhaps the most important, but also quality and performance. Our customers, including OEMs like Samsung and Intel, mandate an extremely low failure rate for the final consumer products. The warranty cost otherwise would be prohibitive. This is totally another level of quality compared to, say, a PC. While a television has become a computer in itself, unlike with a PC, consumers will not accept a TV "crashing" and having to "reboot." However, this kind of problem is difficult to prevent. In order to achieve this, one must build in capabilities for error resilience and error recovery so the TV gracefully recovers from any system errors and does not crash. Obviously, all of this requires a lot of stress testing and verification of the system under a wide set of conditions. Q: Can you tell us more about the verification challenges with Hive Go systems? A: HiveGo products are complex hardware and software system solutions with four or five internal buses, multiple arbiters hooking up to multiple processors, and large memories. The challenge is that you have to verify all the blocks will work together properly in the system. Of course, first you verify blocks working separately, but that is only the starting point. Then you must do system stress testing. The most difficult bugs are those resulting from interaction between blocks, such as corner cases, pipeline stalls, and overflowing buffers, which are almost impossible to predict ahead of time. You also need to verify proper synchronization between hardware and software blocks. Synchronization can be highly timing-dependent. You might never see any problems when testing blocks separately, or running non cycle-accurate simulations. Then at some point you may find problems (such as in a video codec) only after 100 or more video frames have been run through the system. So the only way to find these bugs is to do lengthy simulations with random testing, where you have the different blocks running together and stressing each other. There is no other way to find these kinds of problems. Q: So, after looking at different verification solutions, what options did you consider, and why did you ultimately decide on the Cadence/Palladium III product? A: In the past, Silicon Hive was focused more on offering standalone processors, rather than delivering full systems with application software. In this case RTL simulation with instruction-set simulation (ISS) was quite sufficient. However, verifying multi-core solutions require much more capability than this. At first we tried to make our high-level simulators cycle-accurate. There's a problem -- that requires every building block in our IP portfolio to have its own abstract model, which you have to maintain. Plus the simulation speed really drops dramatically. Then we tried working with FPGA prototype boards. The problem there is that our designs do not typically fit onto one FPGA. So you must partition, or modify the design, or map smaller cores. So you end up modifying the design and not verifying what is actually being delivered. Then we looked at hardware-based acceleration and emulation systems. We decided against FPGA-based emulation due to long turnaround/iteration cycles and also the limited observability. You also have the similar problem as before, where the RTL does not fit everything into one FPGA. So we chose Palladium ultimately because of ease of integration, short iteration/turnaround cycles, full observability, and of course speed. To verify complex video processing systems like ours, you need lengthy simulations with high visibility, and using a system like Palladium III is the only way to find real synchronization bugs in hardware and/or software. Q: Could you describe the transaction-based acceleration (TBA) environment you created with Palladium III? A: So far we used Palladium III in verifying our HiveGo VSS systems -- with video you really need the highest performance possible. Our test bench consists of a bus, connected to our hardware IP and system memory, running alongside a host. Everything except the host is synthesized to Palladium III. The host is represented by using a SystemC model that runs on a PC. The PC uses a transaction-based interface to communicate with Palladium. The resulting speed is several hundred times faster than RTL simulation, approaching that of full in-circuit emulation. It works very well. Q: How easy or difficult was it to get the whole environment to work together? A: Quite frankly, during our first time it took quite some efforts to get the TBA interface up and running, with great support from Cadence. But now in hindsight, because we know what to do, it seems pretty easy and straightforward. One issue was that our designs are VHDL based, while Palladium flow works better with Verilog based flow. So if somebody was using entirely Verilog, they might not have the problems we encountered. Another issue was adapting the compilation flow; molding the make-files into our flow took some time. Q: How would you compare the performance of Palladium accelerators/emulators to FPGA-based systems? A: Of course, FPGA-based systems are generally quite faster, but that is only part of the story. When you are verifying a complex system, what you also need to look at is iteration cycle time, which for us is even more important. For example, the simulation speeds we are achieving with our Palladium III system are about 100 frames of full HD video in about 30 minutes (1/500 of real-time). It takes us about 20 minutes to compile the design, so total iteration cycle time is about 1 hour. This lets our engineers run several iterations per day. On the other hand, with an FPGA-based system you could probably run video frames 20-25 times faster, which is great, but if you run into a bug you have two real problems. First, it's very difficult to probe different signals, so finding the cause of a bug can be very challenging. Second, the time to partition and compile the design for the FPGA generally takes much longer. You also have the problem where partitioning or adapting the design to fit or work in the FPGA might change the functionality in non-obvious ways. So at the end, it becomes much more difficult to uncover and fix any bugs. The FPGA approach makes the most sense when 95% of the bugs are out. If you have any synchronization problems, corner-cases, or overflowing buffers, then you likely won't find them using an FPGA approach. Q: Would you recommend that other companies invest in a Palladium system...why? A: If a company is making complex system designs including hardware and software, if they want a way to run long simulations (which is very important in video and graphics applications) to discover corner cases, then I would definitely recommend a system like Palladium, certainly over any FPGA based solutions. The primary reason is that FPGA solutions lack controllability and observability. If you have time in your schedule, then an FPGA solution can work, but it will have longer iteration cycles. Palladium has an enormous advantage by enabling shorter iteration cycles. Q: How do you see Silicon Hive and Cadence working together in the future...what's next? A: Silicon Hive and Cadence have been working together for a long time, and we appreciate the level of support Cadence provides. In the near future, we are exploring how to use Palladium for power exploration and power analysis in combination with TBA. This will allow us to perform power analysis on complete software stacks. The reason you need TBA there is because these stacks require a lot of rapid interaction between Palladium and the host in order to function correctly. Another interest of ours is to combine Specman constrained-random testing runs with Palladium, together with TBA. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/system-development-what-to-see-at-dac-2010Mon, 07 Jun 2010 22:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62809Ran Avinun/cadence_blogs_8/b/fv/posts/system-development-what-to-see-at-dac-20100The EDA360 vision paper specifies key System Realization challenges. Embedded software development and verification are rapidly becoming the key increasing cost factors for the electronics industry. Integration and re-use are becoming critical for the success of any electronic company. In this blog, I will summarize the specific system development discussions, presentations and demos that Cadence and its collaboration partners will provide during the upcoming Design Automation Conference (DAC) along with other system-level activities that will be held during the show. If you are a system, software, algorithm, or verification engineer, or a designer who is migrating into a higher level of abstraction, I am sure you will find this information to be useful. This year, Cadence will have four key activities on the exhibit floor around its booth (Hall B #1334): 1. Suite presentations - These presentations will provide you a good overview about the specific solutions that Cadence provides to address specific challenges. A combination of presentations and demos that covers Cadence solutions for System Realization challenges will be covered within the following session: System Development with Scalable Performance, Improved Productivity and HW/SW Integration . We will present this overview several times a day on Monday (June 14) through Wednesday (June 16). I recommend that you register (using the above link) to a specific slot prior to the show. 2. Pod areas at the booth - Learn more about EDA360 by attending one of Cadence pods. Each pod will have a high-level overview about one of the EDA360 components (System Realization, SoC Realization and Silicon Realization) and a complimentary set of demos provided by Cadence technical experts. The System Realization pod (look for the Palladium XP Verification Computing Platform) will offer a combination of live and video demos including: a. Palladium XP Introduction video demo b. ARM VSTREAM video demo c. Cadence/Wind River Simics demo d. HW/SW co-debug with ARM based design e. Metric Driven Verification for acceleration 3. Cadence theater is located just across the booth. Learn from experience of Cadence customers and partners how other companies use or collaborate with Cadence solutions, methodologies and flows in order to reduce the cost of development and increase productivity and profitability. I will cover the specific topics and presenters on the day to day agenda below. 4. Private meetings - if you are interested in meeting with Cadence system design and verification management or technical experts, please contact me through email at ran@cadence.com and I will help you coordinate the meeting. Cadence will also have a presence at the TSMC booth (Hall C booth #294), ChipEstimate.com (covering chip planning solutions) at Hall C booth #521, and OVM World/UVM World at Hall B booth #1350. See below for day by day activities. Friday - June 11 There is a small IEEE International event called High Level Design Validation and Test (HLDVT) Workshop 2010 at the Anaheim Convention Center. This event is co-located with DAC 2010. The workshop focuses on addressing the current bottlenecks in validation and test of complex and heterogeneous systems by both employing high-level specifications and developing associated tools, techniques and methodologies to enable drastic reductions in the overall design, validation and test effort. Session 6 (4:25pm) is going to focus on test and debug and specifically emulation, with presentations from Mentor, Cadence, IBM and a speaker from academia. Sunday - June 13 There are three events I would like to highlight: 1. The 13th North America SystemC User Group Meeting from 2:30-6pm at the Anaheim Hilton California Ballroom A. New videos include a keynote from Michael (Mac) McNamara about the synthesizable subset of SystemC. 2. The EDA Consortium and the DAC Executive Committee will get things going with a Kick-Off Reception Sunday at 6:00 pm at the Hilton. I like to go to this event, which has been for many years the opening for DAC and an opportunity to meet your friends from the industry. The sponsorship this year comes from user companies including ARM, Intel, NVidia, Qualcomm, and STMicroelectronics. 3. Right after the reception, at Ballroom A at 7:30pm Gary Smith and Mary Olson will provide an annual update on the state of EDA including trends and forecasts. Monday - June 14 1. If you did not attend the update from Gary Smith on Sunday evening, you will have the opportunity to hear Gary on a Monday morning Pavilion Panel on "What's Hot at DAC." 2. A full day (9am-5pm) DAC co-located event organized by the European Electronic Chips and Systems Design Initiative ( ECSI ) is called: "Choosing Advanced Verification Methods: So Many Possibilities, So Little Time." Brian Bailey will provide the keynote speech and a combination of EDA verification vendors and customers will cover different verification topics. Mike Stellfox (from Cadence) will facilitate the verification planning topic with focus on ESL. J.C. Yeh from the Industrial Technology Research Institute (ITRI) of Taiwan will present ITRI experiences with the Cadence solution. 3. Cadence theater system presentations: a. Simon Davidmann, President & CEO of Imperas Software Limited will present at 2:30pm "Imperas and Cadence: Breaking New Ground in Embedded Software Verification" b. Stan Krolikowski, OSCI board member and officer, will present at 2pm "OSCI standards-based update" c. Tom Sandoval, CEO of Calypto Design Systems , will present at 3:00pm on "Next Generation EDA" 4. Other Cadence demos and suite presentations, as were mentioned above. Tuesday - June 15 1. Management day sponsored by Cadence runs from 10:30 to 6pm at the convention center room 204C. Within this day, there is an interesting session covering the topic "Decision Making for Complex ICs" including panelists from PMC-Sierra, TI and AMCC. 2. Cadence theater system presentations: a. Michel Genard, Vice President of Product Strategy and Marketing at Wind River Simics will present at 11:30 "Helping the EDA360 System Realization Vision Become Reality" b. Vincent.Korstanje, Director of Technical Marketing for System Design tools at ARM, will present at 2pm "Moving towards EDA360 with ARM/Cadence System Realization Collaboration" c. Ashok Mehta, a verification manager from TSMC , will present at 4:30pm "TSMC Open Innovation Platform (OIP) ESL Enablement Flow with Cadence" 3. Other Cadence demos and suite presentations as were mentioned above. Wednesday - June 16 1. User track poster session on 1:30pm at 2nd Floor Foyer Adjacent to 208AB. This is the second User Track poster session at DAC. Join us in viewing approximately 40 posters including a case study involving an OVM-based ESL verification flow by Jen-Chieh Yeh from ITRI 2. Cadence theater system presentations: a. Brian Bailey will present at 10am on "Functional Virtual Prototypes as part of ESL flow" b. Simon Davidmann, President & CEO of Imperas Software Limited will present at 11am "Imperas and Cadence: Breaking New Ground in Embedded Software Verification" c. Vincent.Korstanje, Director of Technical Marketing for System Design tools at ARM, will present at 2pm "Moving towards EDA360 with ARM/Cadence System Realization Collaboration" 3. Other Cadence demos and suite presentations as were mentioned above Thursday - June 17 1. Embedded SoC enablement day runs from 9am to 6pm at the convention center room 303A: a. An interesting session from 9am to 11am will cover the topic "Enabling tomorrow's complex SoC" with participants from Intel, Virage Logic and Cadence. b. The session "Trade-Offs and Choices for Embedded Solutions" will discuss SoC development trade-offs with participants from MontaVista, Xilinx, TSMC and ARM. 2. User Track Poster Session at room 208AB from 4:30pm to 6pm including: Developing Synthesizable IP Modules from TLM 2.0 Descriptions - A Methodology Case Study By: Christian Sauer & Felice Balarin, Cadence Design Systems 3. Panel - What Input Language is the Best Choice for High-Level Synthesis (HLS)? - at room 207AB from 4:30pm to 6pm. Speakers at this panel are from Cadence, Forte, Synfora, Mentor and Calypto. The above listings represent a fraction of the events on the DAC conference program. A complete program listing can be found on the DAC web site, as can registration information. The Cadence DAC web site lists Cadence activities. I hope to see you at DAC 2010. If you have any questions in related to the above, I will be happy to respond. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/tlm-2-0-as-part-of-the-eda360-visionFri, 28 May 2010 16:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62536Ran Avinun/cadence_blogs_8/b/fv/posts/tlm-2-0-as-part-of-the-eda360-vision0Ann Steffora Mutschler recently covered in her blog the progress the industry has made with OSCI transaction-level modeling (TLM 2.0) and the requirements moving forward. Per my quote in the blog, Cadence is a big advocate of standards-based designs and tools, and we believe TLM 2.0 is a good foundation for the future. This view fits with the EDA360 vision , which says you need to merge top-down and bottom-up design methodologies. The migration methodology for System Realization is going to focus on a software-driven or application-driven approach. If you look at the past (and to some extent the existing) design flow, companies have created their virtual prototyping models orthogonally (disconnected) from their RTL models and then tried to figure out how to connect the two together. One of the inputs I gave Ann, which was not emphasized by her in the blog, is the key requirement to connect the 3 worlds of virtual prototyping, design under verification, and high-level synthesis into a single modeling environment. The industry was slow in this migration, both in the standardization committees as well as in the progress that was made by the tool suppliers. This was partially as a result of technology maturity. The existing TLM 2.0 standards and the synthesizable subset are much different. Now that we have mature high-level synthesis technology and TLM 2.0 has become a stable standard, we need to focus on the migration of these two. As for some of the customers, I met one who recently told me: "this was THE major challenge in the industry in the last 10 years." I bet you the world will look different in the the next couple of years. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/crises-in-the-semiconductor-industryTue, 23 Mar 2010 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:35222Ran Avinun/cadence_blogs_8/b/fv/posts/crises-in-the-semiconductor-industry3I am on my way to Japan and I have just finished to read an excellent book and in my opinion a "must have" for any marketer and executive in the EDA and the semiconductor industries. The book is called " Chips and Change - How Crisis Reshapes the Semiconductor Industry " by Clair Brown and Greg Linden. If you are new to this industry, it will help you to understand the history of the semiconductor companies, the challenges they faced and the revolutionary changes, they had to go through in the last generation. Obviously the EDA industry was heavily influenced by these changes as well. If you are industry veteran like me, it will help you to arrange your thoughts and get observation about the changes you have seen (but may not think about) in the last few decades. The book describes 8 crises happened in the last 30 years and their impact on the leading semiconductor companies and the US economy. The book reminds us that our important industry (the EDA industry) serves $250B while we harvest only 1%-2% of this revenue. The book goes through a thorough analysis of the globalization that started in manufacturing and continued with the design portion however at the end paints a conclusion that this trend does not really change the competitive map since many of the semiconductor companies have globalized themselves as well and therefore maintained their competitive advantage. The chapter that was most interesting to me was chapter 3 which covers the crisis around the rising cost of design. The chip becomes the system with SoC cost rising from $7.6B in 1997 to $46B in 2005 (20% of the total chip revenue) to the point, you need to get a return of $400M sales in order to justify $20M SoC investment. The key design cost components as described by the book are: Hardware/Software co-design with increased cost of 1081% over the last four process generation Software cost with SoC (HW/SW) integration as the most critical issue with increased cost of 375% in the same period. Validation with 90% increased cost at the same period. As written in the book, the industry is trying to solve this problem in multiple ways. Two of them are emerging methodologies: Reusable IP - the need to create or acquire IP that can be integrated and re-used quickly by the customers as they migrate from one design to another was described as the key issue being faced by designers today. I was excited to hear about this topic since Cadence addresses this issue already today by focusing on a TLM-driven design and verification methodology with emphasis on IP reuse. Cadence is also working on other solutions that will help customers to integrate IPs into their SoC quickly. Stay tuned! System-level design approach - by moving to ESL, the industry can potentially reduce the cost of development. Although the book mentioned that this is a long journey that has started at the end of the 90's, it recognized the fact that this approach has a lot of merit. There were two reasons the book mentioned, the adoption for this method is not fast enough. A) This approach was used in the past mostly for modeling and HW/SW validation without wide adoption in the connection to implementation - again, this is 100% in line with Cadence approach. B) Designers are always pressured by the next deadline and therefore do not have the time to learn new technologies. We (the EDA vendors) need to continue to invest in education of the market and showing the productivity improvement the leading customers are getting. I would like to hear your opinion as well and if you liked what you read above, I recommend you to buy the book and read more details in this chapter and the other 7 interesting chapters. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/methodology-is-important-but-language-matters-part-2Tue, 09 Feb 2010 14:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:25059Ran Avinun/cadence_blogs_8/b/fv/posts/methodology-is-important-but-language-matters-part-22In this blog, I would like to discuss the direction in the languages that will be chosen for TLM (or ESL) verification. Transaction-Level Models have been used for long time as simulation models. As we start to use more and more high-level synthesis, the link to design and implementation is becoming more important and as such, we need to develop also a mainstream verification environment that will support the new flow. Extension of existing verification methodology is required In order to help the industry (and the large number of verification engineers) migrate to a new level of abstraction, we will undoubtedly need to go through a time of "mixed-level abstraction" in which RTL and TLM models are verified together. Even when most new IP designs are created at the TLM level, many legacy models (written in RTL) will still need to be integrated. We cannot underestimate the infrastructure creation efforts in which verification engineers (and executives) have invested over the last 10-12 years; they will not throw away this environment overnight and the only acceptable solution will be incremental. Therefore, the best way to get "buy-in" from existing verification engineers would be to help build an incremental verification environment (serving both RTL and TLM) on top of their existing one. I would also predict that the TLM testbench verification environment will eventually have the same requirements (or more) as today's RTL test bench: VIP, constrained random stimulus, Metric-Driven Verification, etc. however will provide much higher productivity. A new TLM IP must be thoroughly verified (like RTL IP is being thoroughly verified today) and the resulting RTL will also need to be thoroughly verified. A simple verification environment at the TLM level will not be sufficient. Designers need to use the best-known methods for thoroughly and efficiently verifying a design model that will be implemented in Hardware, where the cost of failure is extremely high. These best-known methods are based on Metric-Driven Verification simulation approaches which include automated constrained-random stimulus, self-checking, and coverage-driven metrics to measure completeness. These should apply to both TLM and RTL IP. The trick is to understand what needs to be verified at each level so the verification process will be optimized to each level. You need to verify a design that will be implemented in hardware where the cost of failure is extremely high, so we should leverage the best known methods from the RTL verification world and adapt them. You would then naturally select a verification language for TLM (ESL) that has long-standing competence for advanced verification with the ones that have been used in the last 5-10 years and are still being used today for RTL verification - e or SystemVerilog. While there are methodology issues to resolve, the first step is to agree on the essential verification languages that will be used. Again, this does not mean that for certain tasks designers will not use other languages ( SystemC , C, C++, etc.) for test benches or even as part of a software stimulus; however the main advanced verification environment (the one that the mainstream verification engineers need to build) will use the same language for RTL, TLM, and the mix of those. So which verification language should be used? If you are using e today for RTL verification, do not look further. In addition to its aspect oriented features and maturity level, e is a transaction level language since it was built independent of any design language or abstraction. This language allows you to handle TLM structures in a simple way and has been used with these models for long time. e is already being used to verify embedded SW and Cadence has already a product ( Incisive Software Extensions ) leveraging these capabilities. Even if you are not using e for RTL verification, you might want to take a look at e as a testbench language for TLM and leverage the benefits the language has. SystemVerilog testbench obviously is going to be a good choice for customers who are dedicated to this language in RTL and would like to use the same testbench language for TLM and RTL. Cadence is committed to support both SystemVerilog and e as advanced verification languages for hardware designs (which interact with embedded software) under test written in TLM, RTL and the mixed of those. So, what does it mean to you? Chose carefully the testbench language, you would like to use. There are advantages and disadvantages to each one of them. It is important to mention that methodology, tools, and the way design and verification engineers build their environment are as important as the language, if not more so. However, history has shown that we cannot ignore the issue of language - language unquestionably matters - when discussing TLM (or ESL) design and verification the same way that language matters when we communicate with the local community in different countries. Cadence preferred language for TLM design is SystemC and for advanced verification testbench, e and SystemVerilog under the umbrella of OVM (now UVM) while SystemC (or C/C++) can be used as a simple testbench language for system engineers who would like to verify their own code or as part of the stimulus of the design produced by software engineers. I know this is a topic that will create a lot of debate; therefore, I would be happy to hear your opinions. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/methodology-is-important-but-language-matters-part-iTue, 26 Jan 2010 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:25058Ran Avinun/cadence_blogs_8/b/fv/posts/methodology-is-important-but-language-matters-part-i2Historical trends in languages Many of us have traveled around the world, and while we can often communicate with local people in our own language, we realize it is best to communicate using the local language. It helps to "break the ice" if you at least try to use some of the local language, perhaps from a guide book. The moment you do it, barriers are removed, and you are more trusted. All this considered, it is still a significant handicap to use the wrong language for the task at hand, especially if you need to have a serious conversation. We see the same barrier (or need) as we look at design and verification languages. In 1989, short time after I started my career at Daisy Systems, I enjoyed teaching customers VHDL as a new design language replacing schematic diagrams. Several years later, I witnessed the transition of the market to Verilog and eventually the migration to mixed-level design using both Verilog and VHDL. I saw the transition from OVL to PSL to SVA, as assertion languages, and eventually the support of the mix of these languages (the design, the verification, and the assertion). In the next two blogs, I would like to discuss the directions in the languages that will be chosen for TLM (or ESL) design and verification addressing hardware developers. Obviously, we can't ignore the other target audience - the SW developers. Software developers have no "religious" preferences about hardware design languages. All they want is speed and early access to the hardware platform while they continue to work in their friendly development environment. The new hardware design language - C/C++ vs. M vs. SystemC As we at Cadence engage with customers using high-level synthesis (HLS), we see two camps: one that drives SystemC (with TLM) as the main design language and another that drives C/C++ as the main design language. And while other languages are being used at a higher level of abstraction (such as M-Matlab), I do not see them becoming part of the mainstream design flow in the near future since their output produces Quality of Results that are far from being ideal for implementation. Cadence endorses the industry standard SystemC extension of C/C++ and drives this as the key design language for new IP development. Cadence also provides tools that let customers' model simple datapath functions in pure ANSI C or C++, and then automatically import or convert them into a complete SystemC environment. SystemC has many built-in capabilities for supporting hardware modeling at abstract level as well as standard TLM APIs for software virtual prototype. We see SystemC as the basis for an order of magnitude increase in productivity - one can model their entire hierarchical design (datapath, control logic, or complex bus protocols) in an industry-standard way to understand and validate concurrency and complex code, while using high-abstraction untimed C++ for most of the main functionality. One can synthesize the hardware design and get a virtual model from a single source code - eliminating today's huge risk where the software is designed to work on a virtual platform which operates similar to, but not the same as how the actual hardware platform operates. ("What you see is what you get!"). This new approach can combine three use models (algorithmic model, virtual prototyping model and architectural model that can be implemented) into one. So where do we go from here. Will RTL disappear? Not likely. RTL will continue to be part of the flow similar to gate-level today and we will see more designs that will create RTL automatically as an output rather than hand coded. So, is it worth it? Why should we change? Our customers reporting 3-4X better productivity during the creation of their IP and 10X when they reuse or explore architectural trade-offs for their IP. As design cost is increasing and IP reuse becomes major part of development process, 10X productivity improvement can not be ignored by the executive management. Do you agree? I would like to hear your opinion too. My next blog will be dedicated to TLM verification language. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/emulation-is-here-to-stayMon, 02 Nov 2009 21:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:22480Ran Avinun/cadence_blogs_8/b/fv/posts/emulation-is-here-to-stay1A recent blog by Brian Bailey covered the emulation war. I would like to correct some of the facts Brian has mentioned and also add my own comments. First, Brian, you owe Cadence an apology :) You forgot some of the emulation announcements from Cadence. You mentioned Nethra Imaging, AMD and Silicon Hive as the ones that were announced in the past year. You forgot the following announcements: Sharp , Netronome , ICT and the recent nVidia announcement about their Palladium usage at the Fermi project (see my blog about "this week Cadence earning call") - all these announced in 2009. If you look at the past year, you can add to this list also Comsys and ARM so depends on your definition, you should count Cadence emulation public announcements of 6-9 companies. As far as the role of the emulation market, since the number of large and complex devices in the range of 50+M gates is increasing and there is a need to run these designs with high fidelity , I predict this market will grow. Similar to 2003, as we will get out of the recession, I expect the CAGR here will increase at the high side of a single digit or even double digit growth. I agree with your assessment that beyond emulation and overall HW-assisted verification, there will be more designs that will start in SystemC or in general in high-level of abstraction. These could be either synthesize to RTL and ported to emulation using high-level synthesis tools or will be ported to virtual platforms if the accuracy level is not critical. Overall with increased of HW and SW complexity and IP reuse, the budget for sub-system, SoC verification, validation and integration will grow and therefore all tools addressing this market will increase usage. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/from-cadence-earning-call-this-weekMon, 02 Nov 2009 16:01:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:22465Ran Avinun/cadence_blogs_8/b/fv/posts/from-cadence-earning-call-this-week0In system development, we have focused on two key customer challenges. First, we are increasing their productivity by elevating design and verification to the next level of abstraction. This quarter, we announced the industry’s first transaction-level modeling, or TLM, design and verification flow. We also announced integration of this flow to support leading embedded software environments, enabling OVM -based, hardware / software co-verification. Second, we introduced a system validation solution, in collaboration with Rhode & Schwarz International to address the emerging 4G wireless market. Rohde & Schwarz International is a leading supplier of solutions in the fields of test and measurement, wireless, broadcasting, and radio communications. These two initiatives combine to provide a more effective design and verification system development environment for our customers, enabling them to significantly reduce costs. Customers such as ITRI , Nethra Imaging and Silicon Hive benefit from this now. In addition, nVIDIA recently used the Cadence solution with Incisive Palladium to deliver its most complex graphics processor to date. This next generation GPU, code named "Fermi", with CUDA and unified Cache Architecture, has 512 cores representing three billion transistors, making it three times larger than the previous high-end graphics processor. The Cadence solution’s ability to verify this entire multi-core design and its embedded software, represented a major breakthrough in electronic design scalability, and was crucial to the rollout of the widely acclaimed Fermi GPU. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/4g-is-here-nowTue, 27 Oct 2009 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:22255Ran Avinun/cadence_blogs_8/b/fv/posts/4g-is-here-now0If you have not heard about 4G yet, it is here now. Verizon has already paid earlier this year $9.4B for an open access to the new spectrum. It'll be using the spectrum as the core of their high-speed 4G LTE network - see below. http://gizmodo.com/376103/verizons-936-billion-700mhz-plans-high+speed-4g-lte-network-up-and-running-before-att I predict, you will see many new designs (mobile, Wimax and base stations) addressing the new 4G standard. Every time, this is happening, companies need to develop new library of IPs, new platforms and therefore invest in design and verification. This is music to the ears of EDA companies and new fabless semiconductor companies. Cadence and and Rohde & Schwarz announced last week a combined solution to enable early validation of next-gen 4G/LTE wireless design. http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=100509_RohdeSchwarz Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/cadence-system-design-and-verification-at-dac-2009-Mon, 06 Jul 2009 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:18803Ran Avinun/cadence_blogs_8/b/fv/posts/cadence-system-design-and-verification-at-dac-2009-0Traditionally in Cadence Marketing there were always two major events you really had to focus on: Sales Kick Off in the winter and the Design Automation Conference (DAC) in the summer. A lot has changed. Starting a few years ago, Cadence added a great deal more: webinars, seminars, segment-specific trade shows, and of course CDNLive! -- all to help you, our customers and users, stay up to date on the latest Cadence technology.Some voices in the past have accused Cadence of "ignoring" the annual DAC show. I can't comment about the past, but I can assure you that in 2009, DAC is important as ever. I have been in this industry for long time and attended many DAC shows and I can say for sure this year marks one of the most active DACs for Cadence that I can remember. Product Managers, AEs, even R&D people, have all been working round-the-clock to put together a line-up of demos, presentations, speaking opportunities, booths and other events, all so you can learn about the latest Cadence products and technologies.A very major highlight this year will be Cadence's new focus on the ESL/TLM space. In the past year we delivered a lot of new technologies there (and are announcing some new ones as well!). Recognizing the size and complexity of this space, as well as the huge opportunities for semiconductor, systems and EDA companies alike, Cadence is putting special focus on collaborating with partners (and even competitors) to bring an exciting line-up of events for you to enjoy. Please join us for a variety of fun and educational events at the DAC show this 27-30 July at the Moscone Center in downtown San Francisco. Below is a summary of Cadence System Design and Verification activities at DAC. This list includes also DAC events with participation of Cadence employees. Monday - July 27th 10:30am-11:00am Cadence Eco-system booth 4300 (North Hall) - Calypto Calypto provides Sequential Logic Equivalency Checking (SLEC) capability as part of a TLM to RTL flow. Cadence C-to-Silicon Compiler creates automatic scripts for Calypto SLEC tool in order to compare the resulted RTL with the original SystemC TLM code. Calypto CTO Anmol Mathur will discuss how Calypto’s SLEC family provides comprehensive formal verification in flows using high-level synthesis tools such as C-to-Silicon Compiler. 5pm-5:30pm - Cadence Eco-system booth 4300 (North Hall) - Rohde & Schwarz Rohde & Schwarz will present an early validation of wireless SoC using the CMW protocol tester. In this presentation, Rhode & Schwarz will feature their wideband tester and wireless protocol checking as part of Cadence ecosystem. Tuesday - July 28t h 9:30am-10am - Cadence ecosystem booth 4300 (North Hall) - Rohde & Schwarz - see above 10am-11am - Cadence eco-system booth 4300 (North Hall) - panel Topic: What is the eco-system role in Virtual Platform/Prototyping ? With the increased percentage of Software content in electronic devices, there is an increasing demand for high-performance platforms for pre-silicon hardware/software verification and integration. Transaction-level models provide an excellent way to build such an environment. This panel will discuss the trends happening in this domain in terms of standardization and interoperability and the ecosystem required to support it from multiple points of view: the design tools provider, the processor IP provider, the verification manager, the system integrator and the SW developer. Participants: Cadence, ARM, Virtutech and ST - I will moderate this panel. 11:30-1:30pm - Room 306-308 - System D&V luncheon Topic: "Is SystemC/TLM D&V Ready to Replace RTL? With a mix of "believes" and "skeptics", prepare for a stimulating debate on whether SystemC / TLM driven design has now evolved to a point where it is mounting a credible challenge to traditional RTL based design. Hear from the companies driving this evolution as they describe the productivity gains and real-world challenges they face in migrating their people, processes and technologies to this new approach. Sponsors: Cadence, Forte & Calypto Moderator: Freescale Panelists: including verification and high-level synthesis users To register and get more information go to: http://www.cadence.com/dac2009/pages/events.aspx 1pm-3pm - Exhibitor Forum Booth 4359 (North Hall) - Steve Svoboda, Cadence Design Systems "System-Level Design and Chip Architecture Flow for Low-Power ICs" 4:30pm-6pm User Track: Room 132 - Jason Andrews, Architect, Cadence Design Systems Design Flow for Embedded System Device Driver Development and Verification Wednesday - July 29th. Virtual Platform Workshop, room 301: 9:45am-10:45am - Jens Stellmacher, Cadence Design Systems Modeling, Analysis and Refinement of Heterogeneous Interconnected Systems Using Virtual Platforms 11:11:30am - Cadence Ecosystem booth 4300 (North Hall) - Calypto - see above 12pm-2pm - Jason Andrews, Architect, Cadence Design Systems Building and Using Virtual Platforms Thursday - July 30th 11am-11:30am - Cadence Ecosystem booth 4300 (North Hall) - ITRI ITRI (Industrial Technology Research Institute) uses Cadence's TLM-Driven design and verification flow (including C-to-Silicon and Incisive Enterprise Simulator) for their ARM-based design with AXI bus interface. In this presentation, ITRI will describe their flow, their use models and highlight results they have achieved to date. 4:30pm-6pm, room 131 - Jason Andrews , Architect, Cadence Design Systems The Wild West: Conquest of Complex Hardware-dependent Software Design Daily activities: July 27th to July 30th Cadence Eco-system booth 4300 (North Hall) When: Monday (July 27th) afternoon, Tuesday (July 28th) morning Wednesday (July 29th) afternoon, Thursday (July 30th) morning As part of the ARM pod of this booth, Cadence and ARM are going to demonstrate their mutual verification capabilities for ARM-based designs. You will be able to see three different demos including: ARM-based HW/SW Environment with Dynamic Power Analysis ARM fast models integrated into Incisive Enterprise Simulator Metric-Driven Verification Flow for ARM’s AMBA Fabrics Using OVM Cadence DAC suite - Booth 3751 (North Hall) - SystemC TLM-Driven Design and Verification Flow When: Multiple time slots every day Using design examples, this session will showcase the full Cadence SystemC/TLM-driven flow for SoC front-end design and verification. The demo will highlight C-to-Silicon Compiler for micro-architecture exploration and RTL development and ncisive Enterprise Simulator. This demo will also highlight the critical roles of Cadence metric-driven verification techniques running on top of Open Verification Methodology (OVM) verification IP and design-planning tools working throughout the flow to ensure SoC quality and predictability. The flow will show the productivity benefits of IP/VIP reuse. For more details and registration go to: http://www.cadence.com/dac2009/pages/demo.aspx#sd Cadence DAC suite - Booth 3751 (North Hall) - Reduce Power While Reducing risk When: Multiple time slots every day This session will show environment and methodology for design, verification, and implementation of digital and mixed-signal designs. It spans early system-level exploration through physical design and signoff, and leverages comprehensive exploration, estimation and analysis technology throughout including the ability to incorporate real-world hardware and software execution data. This demo will show you how the Cadence Low-Power Solution enables low power for all designs. For more details and registration go to: http://www.cadence.com/dac2009/pages/demo.aspx#sd Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/system-d-amp-v-at-cdnlive-emeaMon, 18 May 2009 21:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:17716Ran Avinun/cadence_blogs_8/b/fv/posts/system-d-amp-v-at-cdnlive-emea0CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying $340 for a round trip (record low for trip to Europe). Someone told me today the reason for this was that I have made my reservation at the same time the swine flu news were at their peak and with the decrease in demand for flights the tickets prices went down (go figure!). I like to start with one piece of good news. On my way to the airport the taxi driver told me that in the last month, his business started to recover. Mostly, my taxi driver input is a good indicator to the economic situation so maybe, we are at the start of a recovery (yeah!). If you are a system architect, system engineer, verification engineer, SW developer or logic designer, I think, you have a lot to see at this show. The highlight of today was the system low-power techtorial. Through presentations and demonstrations and a lot of interactions with the audience, the seminar provided the audience a good understanding of the power issues and how these can be resolved with Cadence solution. One of the engineers in the audience told me it took him months to analyze the results we showed in the seminar you can get in minutes. Tomorrow afternoon, we are going to have 3 exciting ESL demos - highly recommended! Next-generation high-level synthesis technology to enable TLM-driven design and verification flow. Integration of processor IP models with Cadence Incisive Enterprise Simulator Integration of Cadence Metric-Driven Verification using Incisive Software Extensions with Virtutech Simic s virtual platform. On Wednesday, we are going to have customer presentations (see below) at the System D&V column . We are demonstrating our Xtreme and Palladium demos at the Cadence booth. See below the list: Complete ARM-Based HW/SW Co-Verification Environment using Palladium III Transaction-Based Acceleration for an Ethernet-Based Design using Xtreme III System-Level Power Analysis with Palladium III / Dynamic Power Analysis Emulation of Wireless SoCs with Palladium III Overall, we have a great conference here. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/edn-s-19th-annual-innovation-awardsFri, 03 Apr 2009 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:16397Ran Avinun/cadence_blogs_8/b/fv/posts/edn-s-19th-annual-innovation-awards0Two of Cadence system D&V products have been selected as the finalists for the EDN innovation award : Palladium DPA (Dynamic Power Analysis) and C-to-Silicon Compiler . I went to the award Dinner this week. In the entrance, I have met Ron Wilson who told me that he believes in the current economic situation, high-level synthesis has a lot of promise since customers are looking for cost saving and productivity and therefore likely will be interested in such a product. As we have got in, I realized there are not too many recognized faces. When I looked at the whole list of categories, I have realized that out of almost 30 categories, only four of them cover the EDA market however I bet with you, each one of these products is using EDA tools as part of the development. This again confirms the level of dependency, the electronics industry has, in EDA products although the EDA industry is relatively small. As a person who was involved with HW products for many years (and still is today), it was interesting to see the variety of HW products (many of them addressing power) that were presented in this award dinner. The ceremony was organized very well and 4 EDA products won the final awards. One of them was Palladium DPA in the design analysis (which I was very proud of). Surprisingly (or maybe not surprisingly) Cadence, Synopsys, Mentor and The MathWorks (who was added to the EDA industry by EDAC in the last few years) won a single award each. I was also wondering why C-to-Silicon Compiler (high-level synthesis product) was competing at the same category (called design creation and IP) with a chip-level router tool? In any case, it was my honor to see one of the products (Palladium DPA), I am responsible for, winning the final award and especially kudos to the development team whao innovated a lot in this product. If you are interested to know more about Palladium DPA, Maulik Patel, Product Marketing Manager published an article explaining this product in details: Introducing Dynamic Power Analysis (Using High-Performance System-Level Power Estimation to Build Leaner, Meaner, and Greener Products). If you want to get more details about both C-to-Silicon, Palladium DPA and Cadence system low-power solution sign-up for one of the local events at: http://www.secure-register.net/cadence.php?product=8. Ran Avinunhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/esl-where-are-we-and-where-we-are-goingTue, 24 Feb 2009 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:15068Ran Avinun/cadence_blogs_8/b/fv/posts/esl-where-are-we-and-where-we-are-going0Many of the messages published by Gabe Moretti in his recent EETimes article resonate very well with Cadence strategy. Specifically: Evolving standards are important with SystemC and TLM becoming the center of the ESL world Cadence supports SystemC with its Incisive Enterprise Simulator and C-to-Silicon high-level synthesis The need to connect the "ESL" world into the "RTL" world in order to migrate this (the ESL) world into the mainstream Our philosophy is that any new IP which is being developed by design engineers should be developed at high-level of abstraction with the end in mind - i.e. this IP should be able to be automatically translated into RTL The need for ESL synthesizers to address both control and datapath domains Indeed, this is a key capability of Cadence C-to-Silicon Compiler The concept of Model-Based Design (MBD) is based on continuous refinements of the design, progressing to less and less abstract representations, that are all automatically generated from the previous, more abstract, representation. C-to-Silicon is capable of extracting models in different levels of abstraction (Untimed, timed etc..) and producing models within different levels of abstraction (Approximately accurate, Cycle accurate and RTL). The evolution of platform-based design with IP re-use - the need to reduce development cost with the increased number of derivative IPs in the market create huge pressure on designers to re-use. The transition to a higher-level of abstraction can provide designers the following re-use benefits: The same IP can be ported into multiple designs or multiple process nodes just by changing the constraints - the base design intent (algorithm) can stay the same. This approach can save weeks/months of manual RTL code development. Multiple architectures can be created and assessed quickly The design complexity can be reduced significantly Design debug becomes much easier and few bugs can be found earlier Key requirement for the above is ability to run ECO (Electrical Change Order) allows customers to easily identified the changed and incrementally synthesize the design without creating major change to their verification environment. The combination of C-to-Silicon ECO and Conformal ECO enables this flow. Yes, the industry is making progress in the ESL domain and designers are starting to recognize it.