Steven Lewis Blog

Cadence is the OpenText Connectivity Partner of the Year

NewYorkSteve — Mon, 28 Nov 2011 22:00:00 GMT

Cadence is pleased to be honored by the OpenText Global Partners Program as their 2011 Connectivity Partner of the Year. The award is a reflection of the close working relationship that we have had with OpenText over the past several years, providing our mutual customers with the best experiences when using Cadence Virtuoso tool suite with OpenText's ExceedOn Demand product line, which provides remote access to Virtuoso. We have done a number of webinars and joint papers to describe how best for our customers to set up both tools to maximize the benefits, particularly when working in a globalized work environment. Once again, on behalf of Cadence, I'd like to thank OpenText for their generous acknowledgment.

The following resources provide more information about OpenText and ExceedOn Demand.

Blog Post

http://www.cadence.com/Community/blogs/ii/archive/2011/07/28/q-amp-a-how-opentext-provides-remote-access-to-virtuoso.aspx

Whitepaper

http://connectivity.opentext.com/resource-centre/whitepapers/achieving-optimal-performance-with-cadence-virtuoso.aspx

Video

http://www10.edacafe.com/video/Get-free-evaluation-OpenText-Exceed-onDemand-OpenText-Remote-Connectivity-Cadence-Virtuoso-Stephen-Lewis/35159/media.html

Webinar

http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=442

Steve Lewis

Virtuoso IC6.1.5: Software and Fine Red Wine

NewYorkSteve — Mon, 14 Mar 2011 12:00:00 GMT

Software, like fine red wine, can get better with age as well -- but it requires constant advancements to remain a vibrant contributor. Such is the case with the Virtuoso IC6.1.5 custom/analog technology release, which delivers on the promise of Silicon Realization with capabilities that maintain design intent throughout the custom/analog flow, simplify the abstraction of analog information to provide high-performance verification capability, and lead to design convergence by providing a common cockpit for in-design signoff technology and support for the Cadence Low-Power Solution.

The enhanced Virtuoso-based custom/analog flow spans design, implementation and verification. The amount of individual tool updates are too numerous to blog about, so I encourage our users to spend a bit of time with the What's New document that is available from Cadence Online Support. Instead, I want to highlight and provide more details on the three larger elements that are encapsulated in the IC6.1.5 release.

Support for Globalized Teams: A variety of new publishing features within the schematic, analysis environment, and waveform window allow for the easy exchange of information across the web. We realize that many of our customers work on a 24-hour clock, and the ability to exchange accurate information at each hand-off point is crucial to keeping a design on track. In previous versions of our software, we have given our customers the ability to closely monitor the design and the implementation of their circuits by using Cadence's design constraint technology. You can learn more about this technology by viewing the Constraint Webinar if you wish.

With this release of Virtuoso, our users can create hyperlinked schematics and datasheets that can be put together instantly, and enable design review at any moment. There is no need to fumble around anymore looking for that particular document that is stored somewhere that makes no sense! Instead, the documentation is stored with the design, and becomes a managed "cellview" just like the schematic or the layout. Archiving is a snap since all the data you will ever need is now located exactly where it should be -- with the design. You really can maintain the intent of your custom/analog design whether it is around the room or around the globe.

New Design Methodologies: Understanding the "impact" of the analog portion of any design is crucial to the success of on-time arrival for your chip. In some cases, it is the parasitics and signal integrity of the analog portion that goes awry. In other cases, it is the integration of the analog into a larger SoC where the problems begin. In either case, Cadence provides solutions to these problems.

For troublesome analog, we offer the parasitic-aware design flow, which allows users to determine the impact of design choices much sooner in the design process. Users can easily include previous knowledge of topologies within the design flow, using these parasitic "estimates" to quickly assess design impact, and then use a combination of constraints and automated layout features to prototype blocks that can be fully extracted and analyzed. These loops are very short and can provide the designer with a much better sense of the design long before any formal layout is fully committed to paper.

Once the prototyping is done, the implementation engineer will also have a better direction to take the lead to a faster "ultimate" solution. They can see the critical design choices and have the tools they are using to implement the design respond to those critical decisions, thus supplementing their own knowledge to create an environment that employs best practices of the manual and automated design flow. If using design constraints, they can be easily checked to see if they were achieved or not, and if not, a notation can be made as to why not. If the implementation engineers discover that important implementation choices need to be made, they can add information (constraints) and back-annotate these to the schematic to act as the golden reference.

In the case of analog abstraction, the new features for Virtuoso IC6.1.5 include the automatic creation of a Common Power Format file from an analog schematic to test the effects of turning on/off different regions of the chip during its operation. Through a simple GUI, the analog engineer defines the power needs for his block, and that information along with the schematic generates the proper CPF file. This file is now used as part of the Cadence Low-Power Solution. This enables the Cadence Low-Power Solution to extend to the ever increasing number mixed-signal designs.

And lastly, with IC6.1.5 we give you the ability to make your existing methodologies new again with the addition of our next generation Accelerated Parallel Simulator and new waveform technology. We continue to expand our simulation technology to take advantage of the latest hardware configurations that are available. We see our customers paying attention not only to their software requirements, but also their capital budgets to make the best choices when it comes to spending for new hardware.

For customers who invest in multi-core machines, Cadence wants to make sure that you are able to exploit that technology as efficiently as possible. To that end we are introducing our APS in a "Distributed" mode. We have been offering our customers speed on single core and multi-core compute platforms. Now we allow you the power to harness multiple, multi-core compute platforms for your most demanding transient simulations to realize peak performance when you need it, particularly at design sign-off time. And don't worry if those transient files that are produced are tens to hundreds of Gigabytes in size. Our completely new an upgraded waveform window technology has been tuned with our simulators to provide performance that is unmatched within the EDA industry for large databases. Combined with its new measurement and extended mixed-signal analysis capabilities, we look forward to you being pleasantly delighted with the new Virtuoso Visualization and Analysis window that comes standard with our Analog Design Environment product line.

In-Design Signoff: Cadence recognizes the fact that traditional signoff is accomplished today by using expensive tools and the end of an expensive design process to find problems that are now really expensive to fix! Anyone see a problem with that? ...anyone?? Clearly this is NOT the way to approach daily design. Instead Cadence allows its signoff technology under the Virtuoso layout user interface to be accessible at any time during the implementation of the design. For instance, let's say you want to check to see if the IR drop across your power rails was going to be severe enough to miss the power specification. Or, perhaps the electromigration that is expected in this technology is going to cause a hotspot or a short somewhere in your design. Or finally, you may be working with sub-45nm technology which you can almost guarantee won't manufacture a proper mask without intervention and compensation during the design phase.

In the past, a user would leave their layout window, run tools on the outside on the database, and then view the results in a third-party display with the translation and fixing left to user to remember. That's a completely error prone way to design and has no place anymore in sophisticated design methodologies. An engineer should be able to see critical problem directly on their layout within the context of the tool that they will use to either fix the problem, or verify the problem was fixed using some sort of automation. Now you have a real design flow that creates productivity instead of frustration. Cadence allows our advanced technology such as Virtuoso Power System, Cadence Litho Electrical Analyzer and Physical Analyzer and our pattern matching DRC technology from the Cadence Physical Verification System all to be used within the cockpit of the Virtuoso Layout Suite. Find, fix and verify all the time in one location. You can save your expensive verification tools to simply be a signoff that Cadence was right all along.

Cadence is pleased that our customers, most recently Wolfson, have joined a growing list of public supporters for the expanded Virtuoso custom/analog flow, finding productivity improvements across the board and providing them with a 25-30% time saving for their designs. For the last 20 years, Cadence has constantly innovated and led the way in solving the complexities of custom/analog design, implementation, and verification. We look forward to serving your design needs into the future, and sharing a glass of wine as friends when we can.

I encourage you to read the press release, What's New document, other collateral covering the new release of Virtuoso, and discuss your thoughts with me. Are the enhancements what you deem as essential in making you more productive? What do you see out there that you think we should know about?

Steve Lewis

Exceed On Demand And Virtuoso IC6.1

NewYorkSteve — Mon, 22 Mar 2010 18:35:00 GMT

Many of our customers use our Virtuoso software in combination with the windows emulation product from OpenText named "Exceed on Demand". To maximize performance between the two tools, we have some recommendations:

For IC6.1.4 and Exceed on Demand 7, these setting will cause problems between the two programs. You should change the settings to the following:

Steve Lewis

Don't Confuse Primary With Only

NewYorkSteve — Thu, 14 May 2009 13:01:00 GMT

Given the small nature of the EDA industry, I have read with some interest company announcements regarding "Primary" or "Key" EDA partnership status. In reading the content, it became clear to me that the wording was meant to obfuscate some important facts, particularly in the area of analog design which I work in. One might read those press releases and *think* that the quoted customer used only one EDA vendor's software for all their design needs. Or perhaps by "omission", the reader would be expected to make certain "assumptions" that were not true. That is why it was important for me to ask our customer SANYO Corporation to help "set the record straight". They have done so and you can read more by following this link. They are using Virtuoso IC6.1 combined with their extensive design expertise in the area of analog and mixed-signal design to help differentiate themselves from their competitors. Analog and mixed-signal design will differentiate the world's semiconductor companies from each other and help guarantee the strongest survive this economic turmoil. On a related note and just in time for CDNLive! EMEA, I am pleased to announce the completion of the 70th tape-out by our leading European customers using Virtuoso IC6.1.

Cadence has served the needs of the analog design community for 20 years and we will continue to innovate and serve in the years to come. That longevity allows us to set the standard by which all other EDA vendors in this space are judged, which if you think about it, I guess that makes Cadence the "Primary" vendor of analog and mixed-signal EDA design tools even if we are not the only EDA vendor in the world. I look forward to setting the record straight at more accounts.

Steve Lewis

Jurassic Park IV: The Return of ANALOG

NewYorkSteve — Tue, 05 May 2009 13:00:00 GMT

In the lab, no one can hear you scream!

When I was getting my BSEE in the 1980s and studying analog and communications, my friends would say, “Why are you studying that old dinosaur, digital is where it’s at!”. Well, far from being consigned to the La Brea tar pit, analog is once again on the upswing as companies seek ways to differentiate themselves in the marketplace. Over the last several months, I have been reading commentary (most notably from Texas Instruments) and listening to editors talk about the importance of analog and mixed-signal design to propel the electronics of the future which rely heavily on being able to interact with people, who are classically analog.

The difficulty with analog is a time-honored tradition, literally and figuratively. Analog, RF and strongly-analog mixed-signal design, all require a longer design time due to the hand-crafting involved. Classic digital design benefits from both uniformity of design and the homogeneity of cells so that the ability to synthesize a design is relatively easy, and the ability to create millions of transistors designs with full verification is an everyday occurrence. But an RF component of two dozen transistors can take a month to realize as part of the overall chip design. It is this time scaling that presents one of the larger challenges for doing mixed-signal design. At Cadence, we are lucky to have both extensive and strong technology in all of the disciplines that are required to do proper mixed-signal design. And given our breadth, we are also well positioned to bring together the best in class design methodologies in each of those domains to form the leading mixed-signal design solution. The Virtuoso group takes ideas from both the Incisive and Encounter groups to look for opportunities to speed up the analog portion of the design, while maintaining the accuracy required. From Incisive we learn the best ways to handle textural design elements, using compiled databases to speed the simulation, and using test vectors during the verification phase of the design. From Encounter, we learn the best strategies for designing for low-power, and how to combine routing and placement automation with the “assistance” in both of these areas demanded by the “hand-crafters” in the analog space. Combine this breadth of technology with Cadence’s 20 years of experience providing complete analog solutions to the electronics industry allows our analog customers to be the T-Rex’s of their company.

So, give a good roar…and try to keep the belching to a minimum.

Additional Reading:

Steve Lewis

The Value of Virtuoso as an Ecosystem

NewYorkSteve — Thu, 05 Mar 2009 21:37:00 GMT

An ecosystem as defined by Webster's is a "system formed by the interaction of a community of organisms with their environment". This describes perfectly the methodologies so common for analog and custom IC design. Unable to strictly rely on automation or synthesis, the custom design flow is chock full of interactive niche methodologies that have become the differentiator of most analog IC suppliers. But, these methodologies are only at their most effective when their interaction is made as tight as possible. The tightness is required to provide the end user the most cohesive design analysis possible. Moving "in and out" of the design flow leads to big mistakes if not carefully monitored. But where are the important touch points in a design flow? What provides the end user with the right amount of cohesion without a cohersion to use non-integrated tools adding risk to the schedule? Let me argue that Cadence's Virtuoso custom design platform finds the right middle ground with its built-in extensibility. The early developers of the Virtuoso custom design platform understood the need for customization and built a solution that was extensible through either C++ or Cadence's own SKILL programming language.

Our customers have come to rely on the extensibility of Virtuoso in several ways. Larger customers use it to link in their own proprietary tools into the over all Virtuoso design flow to help them differentiate themselves. These proprietary tools are often customized to exploit the company's particular design flow needs, and are usually considered ways for them to gain a productivity advantage in the overall design methodology. The introduction of the OpenAccess database further assisted this effort by removing "translation" barriers common to the old methodologies, such as LEF/DEF. If the integrated tools could take advantage of a common database, tighter coupling is possible. Cadence takes advantage of this coupling by combining Virtuoso with Cadence's other paltforms (Incisive, Encounter and Allegro) to provide larger macro-solutions.

Another way customers depend on the extensibility is via links between Cadence tools and other commercially available EDA tools. This is where the Cadence Connections program comes in to help. While it is true that some of these members provide competitive products to Cadence's, they are mostly working on products that fill niches in the custom design flow where for business reasons, it doesn't make sense for Cadence to be in the market. Those reasons can include everything from it being too small (and therefore best served by a small focused company) to the entrance barrier to get into that market is too high it to be profitable for us.

Beyond integrations, Cadence does a lot of work with other vendors that supply the larger ecosystem. The best example is our work with the world's foundries to build Process Design Kits. PDKs are the "rocket fuel" that accelerates the Virtuoso custom design flow. However, this has become a controversial link point. There are those industry pundits who argue that a single interoperable pCell provides tighter linkage that going through the Virtuoso framework to SKILL pCells. But at what cost? Remember, analog and custom designers want accuracy combined with ease of use in the design flow. If pCells are designed to the lowest common denominator, so that in theory it is interoperable with every design tool, what is the value of the pCell? Due to the physical properties of a pCell, I would argue for tighter integration into the design flow you are using. As it is, quite a few customers feel the need to rewrite existing PDK's to make them more accurate to the design styles they are using. By providing the end-user with a pCell that is even further abstracted from the truth, the end user is left with even a greater amount of work to do. We don't think that is a plan for success and have thus shuned efforts to drive the industry in this direction.

Cadence has provided the Virtuoso ecosystem to our customers and our competitors for nearly 2 decades. As we move through these tough economic times, you can at least be assured that the value of Virtuoso as the hub of the custom ecosystem will be maintained.

Time Marches On...and So Do Hardware Requirements

NewYorkSteve — Wed, 04 Feb 2009 18:33:00 GMT

As more people adopt the new Virtuoso we can determine better the recommendations for both software and hardware requirements. We strongly recommend the following when it comes to your hardware and OS situation:

2GB of memory per active user
Minimum graphics memory at least 64Mbytes per 1600x1200 screen resolution
Network latency must be below 200mS

With the IC 6.1.4 release, we will:

Discontinue support for Solaris 8, 9, RedHat 3, Pentium 3 machines
Add support for Solaris 10 and RH4 and binary compatibility with RH5

We hope these settings will help our users be able to make the most out of your experience
using the new Virtuoso.

Thanks Mr. Colton: Imitation really is the sincerest form of flattery

NewYorkSteve — Wed, 24 Sep 2008 21:00:00 GMT

Recognize the name Charles Caleb Colton? No? He was a British writer who in 1820 coined the phrase, "Imitation is the sincerest form of flattery." His words could not ring more true today. With some amusement, I watched the unveiling of a "new and revolutionary" custom design product on Monday, September 22.

As I watched, I could not help to see that it had an umistakable familiarity (which was also highlighted). It "looked" very similar to the previous generation of Cadence's own Virtuoso software. Capabilities that Virtuoso has had for years, were demonstrated proudly and touted as "revolutionary". Actually when they were developed by Cadence all those years ago, they were revolutionary for an industry steeped in using netlists and a vi editor. "New" custom design comes in using design constraints inside Virtuoso to maintain the intent of the design throughout the process. "Revolutionary" comes by introducing new layout techniques such as module generators And lastly "forward thinking" in mixed-signal comes by combining the power of the Virtuoso and Encounter platform to cut the mixed-signal implementaiton cycle by 25%.

But for me the coup de grace was their "new and revolutionary" marketing campaign for this tool.

Look familiar? It should. Cadence also developed and used a similar marketing campaign in 2006 to launch our new Virtuoso. I was personally involved deeply in the development of the Virtuoso marketing campaign and take great delight in seeing the idea copied.

Well, there you have it.

Our newest bundle of joy ... please welcome Virtuoso IC6.1.3

NewYorkSteve — Mon, 22 Sep 2008 13:07:00 GMT

Folks, I am pleased to announce the delivery of the latest Virtuoso platform. It was a long labor, but father and baby are doing well. One of the reasons that we took a bit longer with this release is because we wanted to make sure it was "right" on 3 counts: Stability, Infrastructure Reliability and Advanced Technology. (See the press release here.)

We worked with 18 different customers to test the myriad of different set-ups and custom flows they have developed over the years with IC 6.1.3 to get rid of the "gotchas" that always seem to plague first releases of software. Infrastructure availability was also key to make sure that machines were properly configured, commercial design management tools and thin-clients worked, and that process design kits would be available.

We are pleased to announce 22 PDKs (including variants) available today each optimized and tested for the Virtuoso design flow. Lastly, with new optimization and design centering, routing, and turbo simulation technology in place and ready to go, the new Virtuoso continues to handle the simplest and the most complex custom designs throughout the industry.

Thanks to all of you for your 20 years of support, and we look forward to next 20 years!

Latest Virtuoso news from CDNLive!

NewYorkSteve — Mon, 22 Sep 2008 12:03:00 GMT

Hey Folks, thanks to all of you who participated in CDNLive SV. There was a lot of great information shared by our customers as to their success using teh latest Virtuoso (which by the way has a new version IC6.1.3 out on downloads).

Three presentations that I would call your attention to come from our customers Freescale, Texas Instruments and ST Microelectronics. Each found new and interesting ways of using the advanced features of the Virtuoso Analog Design Environment XL/GXL and the Virtuoso Layout Suite XL/GXL.

In the case of Freescale, they reported significant improvements in their design and verification productivity by taking advantage of the multiple-testbench capabilities, along with the updated corners analysis and new data displaywhich could speed their analysis of data from many sources simultaneously.

ST reported their success in getting a 30% boost in layout productivity by taking advantage of the usability changes and the new integrated router inside the Virtuoso Layout Suite. And finally TI reported on their use of corners, monte carlo and optimization to increase their confidence that their circuits were going to achieve their yield targets once they went to manufacturing.

Each of these successes was made possible because of the maturing of the new Virtuoso, and its ability to handle complex tasks as easily as the simple basic tasks. This continuum of flexibility it what we strove for in the new geenration of Virtuoso, and that labor has come to a spectacular fruition.