Adam Sherer Blog

Introducing UVM Multi-Language Open Architecture

Adam Sherilog — Sat, 01 Jun 2013 02:06:00 GMT

The new UVM Multi-Language (ML) Open Architecture (OA) posted to the new UVMWorld is the result of a collaboration between Cadence and AMD. It uniquely integrates e, SystemVerilog, SystemC, C/C+, and other languages into a cohesive verification hierarchy and runs on multiple simulators. Moreover, the new solution is open for additional collaboration and technology enhancement.

Since Cadence introduced ML verification four years ago, the need for it has never been greater. Complex SoCs are verified with a combination of industry-standard languages and frameworks including IEEE 1647 (e), 1800 (SystemVerilog), 1666 (SystemC), and Accellera UVM, as well as C/C++, VMM, Perl, and others. The previous ML solution enabled the standard connections but had some limitations. Among the limitations included are a focus on “quick-stitch” integration that allowed for data communication but required significant additional coding to synchronize the communication. In addition, the solution was built primarily for the Incisive Enterprise Simulator.

Bryan Sniderman, Verification Architect for AMD, introduces the requirements that drove the development, the limitations in existing solutions, and the features you can expect in this UVM ML OA video. In the video, Bryan describes how the new solution enables hierarchical integration of the frameworks, seamless phasing, seamless configuration, and has the ability to run on multiple simulators.

You can also learn more about the solution in our webinar, “Introducing UVM Multi-Language Open Architecture,” archived on Cadence.com. If you are at DAC, stop by the Cadence Theater on Wednesday at 4:30pm to hear Mike Stellfox present the solution and take part in our Q/A that will follow. Of course, you can also stop by the booth to learn more as well or send an email to support_uvm_ml@cadence.com if you have any questions. Finally, note that you will need to register in the Accellera Forums to download the UVM ML OA and that registration is open to all.

Think of the UVM ML OA as a new beginning. As you read through and watch the background materials, you’ll probably see a mix of exciting new features and opportunities to further improve the solution. We welcome that input. The solution you see here represents a solid foundation, but there is more that we can do and we are happy to expand the collaboration to bring in those new ideas.

=Adam Sherer on behalf of the AMD and Cadence collaboration

New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF

Adam Sherilog — Tue, 07 May 2013 19:41:00 GMT

On May 7, 2013 Cadence announced a 30% productivity gain in the June 2013 Incisive Enterprise Simulator 13.1 release. Advanced debug visualization, faster turn-around time, and the extension of eight years of low-power verification innovation to IEEE 1801/UPF are the key capabilities in the release.

When we talk about low-power verification its easy to equate it with simulation. For certain, simulation is the heart of a low-power verification solution. Simulation enables engineers to run their design in the context of power intent. The challenge is that a simulation-only approach is inadequate. For example, if engineers could achieve SoC quality by verifying the individual function of each power control module (PCM), then simulation could be enough. For a single power domain, simulation can be enough.

However, when the SoC has multiple power domains -- and we have seen SoCs with hundreds of them -- engineers have to check the PCMs and all of the arcs between the power modes. These SoCs often synchronize some of the domain switching to reduce overall complexity, creating the potential for signal skew errors on the control signals for the connected domains. Managing these complexities requires verification methodologies including advanced debug, verification planning, assertion-based verification, Universal Verification Methodology - Low Power (UVM-LP), and more (see Figure 1).

Figure 1: Comprehensive Low-Power Verification

But even advanced verification methodologies on top of simulation aren't enough. For example, the state machine that defines the legal and illegal power mode transitions is often written in software. The speed and capacity of the Palladium emulation platform is ideal to verify in this context, and it is integrated with simulation sharing debug, UVM acceleration, and static checks for low-power. And, it reports verification progress into a holistic plan for the SoC. Another example is the ability to compare the design in the implementation flow with the design running in simulation to make sure that what we verify is what we intend to build.

Taken together, verification across multiple engines provides the comprehensive low-power verification needed for today's advanced node SoCs. That's the heart of this low-power verification announcement.

Another point you may have noticed is the extension of the Common Power Format (CPF) based power-aware support in the Incisive Enterprise Simulator to IEEE 1801. We chose to bring IEEE 1801 to simulation first because users like you sometimes need to mix vendors for regression flows. Over time, Cadence will extend the low-power capabilities throughout its product suite to IEEE 1801.

If you are using CPF today, you already have the best low-power solution. The evidence is clear: the upcoming IEEE 1801-2013 update includes many of the CPF features contributed to 1801/UPF to enable methodology convergence. Since you already have those features in the CPF flow, any migration before you have a mature IEEE 1801-2013 tool flow would reduce the functionality you have today.

If you are using Unified Power Format (UPF) 1.0 today, you want to start planning your move toward the IEEE 1801-2013 standard. A good first step would be to move to the IEEE 1801-2009 standard. It fills holes in the earlier UPF 1.0 definition. While it does lack key features in -2013, it is an improvement that will make the migration to -2013 easier. The Incisive 13.1 release will run both UPF 1.0 and IEEE 1801-2009 power intent today.

Over the next few weeks you'll see more technical blogs about the low-power capabilities coming in the Incisive 13.1 release. You can also join us on June 19 for a webinar that will introduce those capabilities using the reference design supplied with the Incisive Enterprise Simulator release.

=Adam "The Jouler" Sherer

(Yes, "Sherilog" is still here. :-) )

IBM and Cadence Collaboration Improves Verification Productivity

Adam Sherilog — Wed, 13 Feb 2013 19:00:00 GMT

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve the productivity of IBM’s project teams.

Tom Cole, verification manager for IBM’s Cores group, and I took a few minutes to reflect on verification productivity and discuss what the future holds.

Tom, can you describe the types of products your teams verify?

Our groups develop IP cores for IBM internal and external customer SoC projects. Among these are Ethernet, DDR, PCIe and HSS communications cores and memories. Our projects tend to be on the leading edge of performance and standards.

What are some of the verification challenges your teams face?

Our verification challenges fall into three major categories – mixed-signal, debug, and product-level productivity. All of our cores include PHYs, which makes mixed-signal intrinsic to their functionality, but we all know that transistor-level mixed-signal simulation is too slow for methodologies like OVM and UVM. OVM and UVM increase productivity because they reduce the test-writing effort, but they create another challenge in debugging the enormous amount of data they produce. A part of that data set - coverage - is a critical metric for us because it enables us to measure our verification progress. But it also leads to a capacity challenge due to the enormous data volume.

How are IBM and Cadence collaborating to address these challenges?

Several innovative projects are underway with Cadence to address these verification challenges. For example we have applied the metric driven verification methodology as documented in Nancy Pratt's video summary. Another project that has been running for more than a year models analog circuits with digital mixed-signal models, and shows an order of magnitude performance improvement in preliminary results. As a result, we were able to use the same models in our pre-silicon verification and in our post-silicon wafer test harness. As industry leaders, we also share knowledge derived from our collaboration through technical papers. One example is the SystemVerilog coding for performance paper delivered at DVCon 2012 and the constraint optimization paper we will deliver at DVCon 2013.

What’s next for verification productivity?

Given the complexity of verification, there are several opportunities to improve productivity. For example, a promising approach uses formal checks at the designer level to reduce the time to integrate the testbench and blocks of the design for verification. We are currently collaborating to place these static checks in our code for reuse throughout the verification cycle. This may catch unintended instabilities introduced by ECO design changes earlier in the verification process and further improve our overall verification productivity.

If you have questions for Tom or me, please post your comment and we’ll do our best to answer you quickly!

=Adam Sherer, Cadence

Your First Low-power Verification Project - Webinar

Adam Sherilog — Thu, 11 Oct 2012 17:00:00 GMT

So your team just specified its first design with power management circuits. The designers are telling you, its just a few power shut-off domains defined by CPF or UPF. The verification should be easy-peasy right? Wrong. Each domain has complete controls, isolation, and retention. As a verification engineer, you know that any test could trigger a power change either intentionally or in error. How do you build your environment to verify this first low-power project?

Mickey Rodriguez, Cadence low-power verification product engineer has answers for you. In a webinar on Tuesday October 16 at 9:00 am PDT, Mickey will lead a technical discussion entitled "5 Steps to Your First Power Shutoff (PSO) Verification". The discussion will cover these key topics and utilize the low-power reference implementation in the Incisive Verification Kit provided within with the Incisive Enterprise Simulator:

Explaining PSO concepts including isolation and retention
Checking the power format file for errors using low-power rules in Incisive HAL
Understanding and debugging corruption in Verilog
Identifying typical PSO bugs using SimVsion low-power debug
Leveraging assertions to increase quality and generate low-power verification coverage

So if you are a digital IP designer intersted in knowing how your PSO circuit will be verified, a verification engineer responsible for that verification, or a project manager trying to balance project risk and tighten power-budget requirements, this webinar is for you!

You can sign-up for the webinar here: http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home

=Adam "The Jouler" Sherer, Incisive Product Marketing Director

UVM SystemVerilog in a Multi-Language SoC World: UVM-ML Webinar

Adam Sherilog — Thu, 11 Oct 2012 15:00:00 GMT

Every SoC project uses multiple languages. Even if the design itself is purely Verilog RTL, it's likely that you have some PLI-based stimulus. In many cases there are multiple languages in use due to multiple suppliers, globalized teams, multiple abstractions, and more. Integrating e, SystemVerilog, SystemC, and C/C++ into one simulation is basic but insufficient for SoC verification. The question asked by SoC verification teams is "how can these work together in a cohesive environment?"

Cadence saw this need in the years leading to the UVM and was the first to contribute a multi-language solution. That work was first contributed to the now offline OVMWorld in 2009. It was updated to align with the Accellera Systems Initiative UVM standard and contributed to the UVMWorld in 2010. Since then, this solution was updated several times to remain synchronized with the UVM and add new functionality. With more than 1,500 downloads, it remains the first and leading open-source solution for UVM multi-language applications.

On Thursday October 25 at 9:00 am PDT, we'll review the solution and discuss the latest new features. This technical discussion will be lead by Gabi Leshem, Solutions Architect, and Guy Mosenson, Senior Solutions Architect using the Incisive Verification Kit delivered with the Incisive Enterprise Simulator. The Incisive Verification Kit is a superset of the Cadence UVM reference flow (with 4,000+ downloads covering v1.0 and v1.1) available on UVMWorld. During the discussion you will learn about the following topics:

Requirements for modeling multi-language UVM-based environments
How to implement and integrate a UVM-ML verification environment
Multi-language communication and synchronization features
Advanced debug techniques key to analyzing multi-language environments and resolving multi-language issues

So if you are a verification engineer, designer, or manager interested in leveraging existing VIP and improving reuse, this webinar is for you. You can register for the webinar here: http://www.cadence.com/cadence/events/Pages/eventseries.aspx?series=Functional%20Verification%20Webinar%20Series%202012&CMP=Home.

Regards,

Adam "ML" Sherilog, Incisive Product Marketing Director

Accellera Systems Initiative Releases UVM 1.1b for SystemVerilog

Adam Sherilog — Fri, 01 Jun 2012 18:54:00 GMT

Accellera Systems Initiive released the UVM 1.1b on its website June 1 and announced it on the UVM World site here. Cadence is happy to see this latest release maintaining the APIs and backward compatability of the UVM while improving the quality and stability of the SystemVerilog library.

Building on a decade of experience with the methodology, Cadence offers a unique solution for the UVM. That experience is showcased in the recent series of SystemVerilog and e videos produced by Axel Scherer. Those videos introduce the key concepts in the methodology using the Incisive Enterprise Simulator. You can see more about the unique capabilities of the Incisive Enterprise Simulator for UVM in our DAC booth (highlighting UVM with low-power) and in our suites for more depth.

If you are going to be at DAC I look forward to seeing you there.

=Adam Sherilog, Incisive Product Manger

Where There's Smoke, There's fire in the Belly of an Aspiring Engineer

Adam Sherilog — Mon, 02 Apr 2012 12:40:00 GMT

Humans learn with their hands and, it turns out, electrical engineers are humans. Most of us fondly recall "experiments" we did that made electrical engineering our destiny. But what of the current generation? Have apps deadened the EE in the way video killed the radio star? I am happy to report that the answer, for one future EEs at least, is a resounding "power up!"

For some strange reason, my oldest son thinks EE is a great career path. Maybe its my incessent blabbing about it, but there has to be more. My freshman class had 2000 declared engineers but only 500 that made the junior year programs. Why? I think the answer lies in hands-on. Engineering isn't something you just dream about; its something you do. With your hands. When you literally feel it you know its yours.

To feel it you have to do real projects with raw parts. Two of my favorites from my childhood were my rocket sled and my hydrogen separation experiment. (Warning: DO NOT ATTEMPT THESE AT HOME. Sometimes I wonder how I survived...) My rocket sled idea was born from winter doledrums and boredom from building rockets that just went up. One icy New York day, I cut runners from a Coke can, glued them to a rocket tube with three stabalizing fins and lunched it across our frozen lawn. It worked! I then added wings to see if would lift a bit and, well, I'll leave that next part for another time.

The other experiment was more of a "learning experience." Having seen the apparatus for splitting hydrogen and oxygen from water in school, I decided to build one for myself. I decided to go cheap: a beaker, two 0.5m lengths of bellwire, and a wall outlet. The EMF blew the wires out of the socket and vaporized half of the insulation. Lesson learned. These and other "experiments" led me to create a novel solution leveraging a very fast (at the time) disk response and self-modifying code to fit an application on a BBC Acorn that could not possibly fit because I could "feel" the solution.

So what of this generation of internet kids? Is there hope? Well, I can proudly say for one aspiring engineer, there is.

My 17-year-old son Zach wants to be an EE and I'm proud of that. He knows my stories and, as his dad, I can't just say "burn an eyebrow" but secretly... He started with elaborate paper designs: a back-pack personal flyer, a car powered by a flywheel, and more. And then the "experiments" came. First was the tablet computer made from disassembling an old Macbook and then the bottoms-up assembly of his PC. All good, but no smoke.

Then came the video game cabinet. This was a big one. He had to research the construction, buy the components, then WIRE the system, and then configure the computer. Yes, wire it. Together, we designed and built the cabinet. Then we got the wire-strippers and soldering iron out and made some smoke. Yes, that made me proud, but that wasn't it the turning point. That started yesterday when he spent hours doggedly tracking down all the software components needed to configure Ubuntu to run M.A.M.E. but the real lesson came when he found one of the joysticks didn't work. He diagnosed which wires were cross-coupled and fixed them with my grandfather's screwdrivers. A fourth-generation engineer was born yesterday in smoke and debug. I could not be more proud.

Today, Zach is back in school working through his classes and I'm back at work but the world has changed in a subtle but substantial way. I had a convesation with one of Cadence's R&D managers today where we shared the magic of the "oh wow" moment and how he drives this with his children's Mindstorms Robotics league as well as his own team. Facebook has guaranteed that Zach is having the same conversation with his friends. Where there is smoke, there is fire in the belly of the aspiring engineer.

Now back to our regurlarly scheduled verification blog already in progress. (Thank you for indulging one exceedingly proud poppa. :-) )

=Adam Sherer

(P.S. If folks want references to the cabinet construction, M.A.M.E, and/or what Zach did to get it running on the ancient PC hosting Ubuntu I can probably get a guest blogger to post a comment. :-) )

Assertions Help Avoid Chip Melt

Adam Sherilog — Thu, 22 Mar 2012 20:16:00 GMT

When asked why the use of assertions for low power is rising, I say “at 40nm and below, the chips are just going to melt.” Ann Steffora Mutschler, you quoted me perfectly in your “Avoiding Chip Melt” article!

Assertions are just the tip of the low-power verification iceberg. (Yep: iceberg + low-power +melting chips = metaphorical mayhem!) Kidding aside, in the article, both Erich Marschner from Mentor and I cite the breadth of issues facing complex, multi-domain power-aware chips. We agree that assertions are a simple starting point for designers to outline their power intentions for the verification team to verify. In the Cadence Incisive solution, we take it a step further by generating the power assertions directly from the power-format file.

But as we said, that’s just the start. Teams with power-aware designs should be running low-power in every regression test because any one of those tests could trigger a change in power-state and the simulator should respond appropriately. Doing so will also make it easier to verify the power-aware aspects of the verification plan. With Incisive, you can also generate verification plans from your power-format file and collect coverage to gain a better understanding of the quality of your power-aware circuits. To learn more about this, please attend John Decker’s upcoming “How to Avoid Low-Power Failures” webinar on April 4.

So whether you’re facing the risk of a melting 40nm chip or just trying to differentiate your product by making it power aware, consider low-power assertions as the first step toward a comprehensive low-power verification methodology.

=Adam “keep it cool” Sherer, Cadence Product Director

Gentlemen, Start Your Simulation Engines

Adam Sherilog — Wed, 22 Feb 2012 15:42:00 GMT

As we outlined in our recent performance white paper, every verification team has the need for higher performance simulation. Of course, you can expect on-going innovation from Cadence R&D, but there are some things you can do to get more from your engine at any time. The February 23, 2012 webinar explains just that.

Attendees to the webinar will learn a series of tips they can apply immediately. Among these are environment set-up for efficient simulation, rapid turn-around time starting with techniques to speed elaboration, and faster run-time simulation. The information will be presented by Amit Dua, author of the performance white paper and leader of the team that has conducted performance audits and improvements worldwide.

Gentlmen, and ladies, start your simulation engines!

=Adam "Zoom" Sherer

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Adam Sherilog — Mon, 30 Jan 2012 14:00:00 GMT

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level productivity. Mixed-signal. Low-power. UVM. And. And. And. … And the reality is that advanced node SoCs are so complex that it is truly about all of these. Our new white paper details a systematic approach to verification performance you can use immediately at all levels from core simulation to advanced technologies and methodologies.

For certain, the most common use of simulation is RTL and gate-level simulation. During 25 years since the start of the RTL era, Moore’s law has held true as designs have doubled every 24 months. While the design work is still all done in IEEE 1076 and 1364 (+1800 since 2005 and now some 1666), verification productivity, predictability, and quality is now derived from an ever-increasing suite of standard languages and methodologies. The result is that the typical simulation run today employs a wide range of features beyond RTL and gate.

That history lesson is probably common knowledge, but how to deal with the performance requirements of advanced node SoCs isn’t. Because of all the complexity, the simulator has to be measured in multiple ways to build-in the best performance. That will give us a fast simulator, but if we run that simulator using the golden scripts we created years ago the effect on this fast engine is akin to strapping model-T tires on an F1 car. After we’ve got all the elements of our simulation balanced for performance, it’s time to dig deeper into the code we’re running on the engine. Sure, that code is running accurately, but is it running efficiently? The simulator is just going to execute the code we provide, so we need to profile our code and find algorithms that get the same task done but do it faster. We introduce this last concept in the white paper, but that’s a teaser for a DVCon 2012 SystemVerilog performance paper. Stepping back from profiling, keep watching this blog stream for application notes that will help you implement the ideas in this core simulation section of the white paper.

Now that your simulations are running fast, where do you go to get even more performance? The “Advanced Node SoC Verification Requirements” section of the white paper introduces several technologies and methodologies that, with varying degrees of investment, can provide substantial improvements in performance and productivity. If you are at or below 40nm, or planning to go there, pay careful attention to this section and the Advanced Verification Topics book to understand the options you have for further performance improvements.

When Cadence pioneered commercial simulation with Verilog-XL 25 years ago, life was simple. Chips were designed in schematics, and RTL and gate simulation was all we needed. Simulation has come a long way from those days and is even more relevant in today’s complex chips. This white paper will help you understand how the Incisive Enterprise Simulator has adapted to today’s advanced node SoCs and how it will continue to scale for tomorrow.

=Adam Sherer