Stella Murphy Blog

Video, Part 2: Cadence Demonstrates PCIe Gen3 Advanced Features

StellaM1 — Thu, 04 Aug 2011 00:00:00 GMT

Welcome back for Part 2 of a two-part PCI-SIG video demo featuring Cadence’s PCI Express Gen3 Controller IP advanced capabilities, with a discussion on Single Root I/O Virtualization (SR-IOV). Part 1 was covered in a recent blog post.

What is SR-IOV? Briefly, SR-IOV is a specification that allows a PCIe device to appear to be multiple separate physical PCIe devices. PCI-SIG created and maintains the SR-IOV specification with the goal of having a standard specification to help promote interoperability. One of the milestones achieved for Cadence’s design IP for PCI Express Gen3 is proving SR-IOV interoperability in silicon against an Intel chipset.

Why is it important? The two main advantages of an SR-IOV PCIe device are:

It allows multiple OS’s to have their own private view of the PCIe device
It helps improve I/O performance by reducing latency of the hypervisor

How have Cadence customers used PCI Express Gen3 SR-IOV to solve their design problems? In one example, a SAS RAID controller using 2 physical functions (PFs) and 16 virtual functions (VFs) was able to have 16 guest applications privately access the PCIe device. VFs are “lightweight” and have the advantage of requiring significantly less logic overhead than PFs.

Please see the video below for more details. Also, please comment on how you've seen PCIe Gen3 SR-IOV used in different applications.

Stella Murphy

Video: Cadence Demonstrates PCIe Gen3 Silicon at PCI-SIG Dev-Con (SAS RAID Controller)

StellaM1 — Thu, 28 Jul 2011 18:00:00 GMT

This video is part one of a two-part series demonstrating the Cadence PCI Express Gen3 IP silicon on the customer's PC board while it's being tested with a LeCroy Protocol Analyzer and Exerciser. In part one, Ashwin Matta, Cadence engineering director, discusses the IP performance and core capabilities of the Cadence PCI Express Gen3 IP captured by the display trace.

Highlights:

The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification
The demo shows Cadence's PCIe Gen3 high performance x8 configuration operating at full speed 500Mhz clock rate with a transfer rate close to 8GT/s
The display trace shows the PCIe Gen3 IP transition from Gen1 speed 2.5 GT/s to Gen3 8GT/s
LTSSM flow graph showing equilibrium between upstream and downstream packet transfers and speed of operation at 8GT/s

Please come back soon to view Part 2 of 2 showing the advanced features of Cadence's PCI Express Gen3 IP.

Stella Murphy

Cadence Demonstrates PCI Express 3.0 Controller IP in Customer Silicon

StellaM1 — Thu, 30 Jun 2011 19:00:00 GMT

At the June 2011 PCI-SIG Developer's Conference, Cadence demonstrated Cadence Design IP for PCI Express 3.0 controller IP implemented as a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration in a customer's ASIC. The Cadence PCI Express 3.0 controller in the ASIC reference card was attached to a LeCroy Summit T3-16 analyzer and Summit Z3-16 exerciser platform to demonstrate the Cadence PCI Express 3.0 core with traffic running at 8 GT/s per lane.

The Cadence PCI Express 3.0 design IP complies with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification.The PCI Express Gen3 IP successfully implemented in silicon advanced capabilities like Single-Root I/O Virtualization (SR-IOV), as well as the latest engineering change notices (ECNs) including ID-based Ordering, Re-Sizeable BARs, Atomic Operations, Transaction Processing Hints, Optimized Buffer Flush/Fill, Latency Tolerance Reporting and Dynamic Power Allocation. The Cadence PCI Express 3.0 IP has already been implemented in the recently announced PMC-Sierra 6Gb/s SAS Tachyon protocol controller.

To learn more about the Cadence Design IP for PCI Express Gen3 IP, please come back next week to see the PCI Express Gen3 IP video of the demonstration.

Stella Murphy