Sathishkumar Balasubramanian Blog

Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

Sathish Bala — Fri, 29 Mar 2013 16:00:00 GMT

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face are in SoC level verification and seamless analog/digital implementation. Cadence has been addressing these challenges for the last few years with its focus on mixed-signal solutions. Cadence's Mixed-Signal Methodology book has garnered tremendous interest from the worldwide mixed-signal design community.

In order to cater to the design community in North America, we will present a series of Mixed-Signal Tech on Tours to showcase and address mixed-signal challenges and show how Cadence's mixed-signal solutions can help deisgners achieve design closure.

In the first series, we are coming to the east coast. Below are the dates and cities for MS ToTs in this series:

Ottawa, Ontario -- April 2, 2013
Baltimore, MD -- April 4, 2013
Chelmsford, MA -- April 9, 2013

You can register for any of these events here.

Key topics that willl be covered include:

Modeling analog behavior with highly effective real number models
Applying assertion-based, metric-driven verification
Verifying low-power intent with dynamic and static methods
Floorplanning and integrating designs in a seamless, OpenAccess-interoperable flow
Analyzing timing and power for complex SoCs to prevent silicon re-spins
Mixed-signal IP offerings from Cadence

To deliver these sessions, we are bringing in experts for each topic to provide excellent technical depth.

In addition to Cadence mixed-signal technologies, we are very pleased to have IBM partner with Cadence to talk about IBM's foundry and services enablement at these events.

Below is the detailed agenda for the first three Mixed-Signal Technology on Tour events at Ottawa, Baltimore and Chelmsford. I hope to meet you at these events.

Sathishkumar Balasubramanian

Agenda

9:00am	Registration and Breakfast
9:30am	Welcome and Opening Remarks
9:45am	- Mixed-Signal (MS) Solution Overview - MS Trends and Challenges - MS Verification Overview - MS Implementation Overview - Verifying Low Power in MS design - Static Timing Characterization for MS Ecosystem
10:15am	- Mixed-Signal Simulation - Performance and Scalability - Use Models and Language Support
10:45am	- Analog Behavioral Modeling - Why Do I Need Modeling? - Real Number Modeling - Model Generation and Validation with Demo
11:30am	- Simulating Embedded ARM Cortex-M0 MS Designs - Trends in Analog Intensive MCU - ARM Cortex-M Introduction - HW/SW Verification Flow with Demo
12:00pm	Lunch Cadence
1:00pm	- Advanced MS Verification - Assertions, UVM-MS and Metric-driven Methodology
1:30pm	- Quick Turn-around Time with Cadence Analog/Mixed Signal (AMS) IP - AMS Interface IP - ADC's, 10G-KR PHYs - Cadence AMS IP Portfolio
2:00pm	- Analog on Top (AoT) MS Implementation Flow - AoT Flow Overview - Virtuoso Floorplanning and Analog Layout - Digital Block Synthesis and Implementation in RC/EDI - Chip Integration and Signoff
3:00pm	IBM Foundry Services and Design Enablement
3:45pm	Break
4:00pm	- Digital on Top (DoT) MS Implementation Flow - DoT Flow Overview - Constraint (Routing) Exchange and Validation with Demo
4:30pm	Wrap-up

"Smart Devices" and How They Affect Your Mixed-Signal SOC Verification

Sathish Bala — Mon, 25 Feb 2013 19:00:00 GMT

We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet' was associated with a PC or Mac. The smartphone revolution has changed how the data is consumed and used by consumers and businesses. For example, with the new line of smart systems, every device or appliance is connected to the Internet to manage their services in a better way with users and other connected devices.

A good example in a B2B segment is the new "SenseAware" device by FedEx. These devices are used by FedEx for individual tracking of packages. The SenseAware devices are compact and power efficient. These devices monitor location, temperature, humidity and air pressure, and communicate in real time to the Internet. The information is accessible to authorized users. Thus, "Internet of Things" is a catchy phrase that has started to play a major influence in making human lives much more productive, easy and profitable.

These smart devices have started taking over the majority of the electronics markets by volume. It is predicted that we will have close to 20 billion of these devices by 2020. Smart devices are predominantly mixed-signal SoCs with analog and digital components on the same die. The key challenge that faces these complex mixed-signal SoCs is in the top level functional verification. This challenge is mainly attributed to the simulation bottleneck that plagues these complex mixed-signal SoCs.

Both the analog and digital simulators have to be run for SoC verification. The complex analog to digital and digital to analog interactions have to be properly accounted for and verified with acceptable coverage levels. However, with the traditional black box approach, there are more chances for functional failures that can result in costly re-spins and result in time to market delays that can be very detrimental to profitability.

To address these verification challenges for mixed-signal SoCs, Cadence offers a complete set of mixed-signal verification solutions for analog-centric as well as digital-centric users. Analog-centric users have successfully been using the Virtuoso AMS Designer solution to apply mixed-signal verification test benches to both transistor-level and AMS behavioral views of cells and subsystems. For the digital-centric users, Cadence has also been successfully enabling customers to adopt discrete real number models (RNM) of analog blocks to allow ultra high-speed verification of mixed-signal SoCs. The key is for designers to recognize the need for their analog and digital teams to work together in both the modeling and verification arenas. It's the only way they can seamlessly verify the operation of their entire mixed-signal SoC.

Real number modeling is a signal-flow based approach that uses real (floating-point, continuous) values to represent current or voltage in discrete time. The most obvious advantage of using RNM for top-level SoC verification is that it runs nearly as fast as pure digital simulation in fast digital simulators such as Cadence's Incisive Enterprise Simulator, which is many times faster than SPICE-based simulation or even analog behavioral modeling. This makes full-chip verification possible for large mixed-signal SoCs. Digital simulation speeds permit nightly, high-volume regression tests. With no analog engines, there are no concerns about convergence errors. In addition to allowing digital simulation speeds, RNM lets designers use digital verification techniques such as assertions, coverage, and metric-driven verification as part of their overall mixed signal SoC verification effort.

Many languages support RNM including Verilog, SystemVerilog, VHDL, e, and Verilog-AMS. Wreal is a native Verilog-AMS language feature that brings the benefits of digital signals into Verilog-AMS. For example, wreal allows real variables on ports. Cadence has developed a Verilog-AMS based RNM solution for customers looking for high performance and reasonably accurate modeling of analog behavior to aid verification of mixed-signal designs. This was implemented using the Verilog-AMS language features while extending them to improve the effectiveness of wreal signals as a way to model analog behavior and signal interactions.

RNM is not, however, a replacement for analog simulation. It is not appropriate for low-level interactions involving continuous-time feedback or low-level RC-coupling effects. Nor is it intended for systems that are highly sensitive to nonlinear input/ output impedance interactions. And, real-to-electrical conversions require some careful consideration. If one is too conservative, there will be a large number of time points. If one is too liberal, there can be a loss of signal accuracy. With the recent introduction of the Cadence Virtuoso Schematic Model Generator for behavioral model generation and Virtuoso AMS Design and Model Validator Cadence is helping designers to extend metric driven verification to the Mixed-Signal world.

If you are interested in learning more about RNM and next generation mixed-signal verification technologies there are several opportunities to interact with Cadence mxed-sgnal verification experts in the next few weeks. At DVCon 2013, you can visit the Cadence booth or participate in various sessions. There is also a dedicated mixed-signal track at CDNLive Silicon Valley in March. It includes sessions that focus on addressing mixed-signal verification challenges using Cadence mixed-signal verification solutions. Finally, the recently released Mixed-Signal Methodology Guide available from Cadence is an excellent resource.

Sathishkumar Balasubramanian

Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitment

Sathish Bala — Tue, 08 Jan 2013 21:19:00 GMT

Cadence holds a leading position in the EDA industry due to its broad product portfolio catering to digital and analog designs and the ever popular mixed-signal designs. With its immense technical and market leadership based on the Virtuoso platform for analog design and Encounter platform for digital design, Cadence EDA products helps designers achieve productivity gains and predictable design closure for today's complex mixed-signal designs.

The focus on mixed-signal solutions has been one of the key objectives for Cadence over the past few years. Last year at the Mixed-Signal Summit Cadence announced the publication of industry's first comprehensive Mixed-Signal Methodology Guide authored by Industry experts and key visionaries from Cadence and its customers. The book helps designers understand the verification and implementation methodologies and addresses key challenges faced by the design and verification teams.

Cadence worldwide CDNLive conferences and Mixed-Signal Tech on Tours have received very positive responses from Cadence customers to provide a platform to learn about Cadence mixed-signal solution offerings and to discuss the various challenges in mixed-signal designs. To further serve our worldwide mixed-signal design community, we have revamped our Mixed-Signal Solutions web page to help designers use the Cadence mixed-signal methodology to address implementation and verification challenges. There are several excellent technical white papers and customer success stories that articulate how our key customers met their objectives with the Cadence mixed-signal solution. The site also includes descriptions of mixed-signal implementation and verification challenges, IP and services, alliances, Resource Library, and recent blog posts.

Click here to visit the Mixed-Signal Solutions web page to learn more about Cadence mixed-signal offerings and the latest design trends.

Sathishkumar Balasubramanian

Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums

Sathish Bala — Thu, 15 Nov 2012 02:00:00 GMT

The recently concluded ARM TechCon 2012, the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event showcased the excellent Cadence-ARM partnership that's helping to bring next generation electronic designs to fruition for our customers.

Cadence had a huge presence at ARM TechCon. On the first day (Chip Design Day) Cadence had two dedicated booths on the floor to show Cadence technologies with ARM based products, from ARM processor cores to 20nm PDKs. To my surprise, the traffic was very heavy throughout the day, with attendees very much interested in the 20nm flow using the Cadence Encounter Digital Implementation System.

The key highlight was that Cadence ran a live, system-level verification demo of a Cortex M0 processor based system. To my knowledge, Cadence was the only vendor with a live demo that demonstrated its confidence and leadership in mixed-signal system level verification. Apart from the Cadence booth, the ChipEstimate.com booth that highlighted Cadence chip planning tools along with the ChipEstimate.com's leading IP portal.

Another key event that increased the visibility of the Cadence and ARM partnership was the press release that was announced for the 14nm Test-Chip with ARM processor and IBM FinFET process technology using Cadence's Encounter Digital Implementation (EDI) system and Virtuoso tools. Cadence also had more sponsored sessions than any of the competitors to talk to the ARM design community about various design topics and challenges. I personally gave a talk on Mixed-Signal Low Power Implementation of a Cortex-M Series System with a co-presenter from ARM. The session was a standing room only event with a huge response from customers. This response further validated Cadence's focus and leadership in mixed-signal solutions for implementation and verification.

For customers not present at the ARM TechCon 2012, ARM Technology Symposiums at key cities around the world are an excellent opportunity to visit and interact with ARM and Cadence personnel and learn more about advanced Cadence technologies. Cadence is participating in the symposiums listed below with sponsored sessions and a Cortex-M Mixed-Signal Demo at the Cadence booth. To conclude, Cadence and ARM have had excellent partnership and collaboration in 2012 and Cadence is looking forward to continuing on this success in 2013 and beyond.

The schedule for ARM Technology symposiums is listed below.

05 Nov 2012	ARM Technology Symposium 2012 - Bangalore	Bangalore, India
20 Nov 2012	ARM Technology Symposium 2012 - Seoul	Seoul, Korea
23 Nov 2012	ARM Technology Symposium 2012 - Hsinchu	Hsinchu, Taiwan
26 Nov 2012	ARM Technology Symposium 2012 - Shanghai	Shanghai, China
28 Nov 2012	ARM Technology Symposium 2012 - Beijing	Beijing, China
30 Nov 2012	ARM Technology Symposium 2012 - Shenzhen	Shenzhen, China

Sathishkumar Balasubramanian

Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership

Sathish Bala — Fri, 19 Oct 2012 16:00:00 GMT

A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled "TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design Infrastructure, Spanning Custom/Analog, Digital and Mixed-Signal Design." This press release emphasizes that TSMC's 20nm reference flow is not only for digital design using Encounter Digital Implementation (EDI), but is also for custom/analog design using Virtuoso, as well as sign-off using Encounter Timing System (ETS) and Physical Verification System (PVS).

This press release clearly validates Cadence's leadership in not just digital design, but also in analog design and more importantly the complex low-power mixed signal design that is prevalent in the marketplace. This is mainly due to the explosive growth of smartphones and intelligent electronic appliances. The majority of today's designs are true mixed -signal designs where there is an equal emphasis of analog and digital content in a single system-on-a-chip (SoC).

Cadence's "mixed-signal on top" Implementation solution is perfectly tuned to target these designs. Cadence's mixed-signal on top flow integrates the industry-leading Virtuoso platform for analog design, and the EDI platform for digital implementation, providing a seamless implementation methodology.

The second item that caught my attention is an ARM blog post titled 'Blurring the Analogue/Digital design frontier' written by Thomas Ensergueix, CPU Product Manager, ARM. He talks about an ARM-Cadence Cortex M0 Demo. This demo focuses on designing ARM's M0 based system based on the Cortex-M System Design Kit (CMSDK) using Cadence's mixed signal solution with an end to end implementation and verification flow.

On the implementation front, Thomas talks about the seamless integration of Virtuoso and EDI platforms through OpenAccess to tackle the true mixed-signal design featured in the Cortex M0 demo. The demo also features low power implementation and verification, which are natively supported using the Common Power Format (CPF). Finally, the simulation is done using the CPF-aware AMS Designer Simulator.

On the mixed-signal verification front, Cadence's Schematic Model Generation (SMG) and Analog/Mixed-Signal Design Model Validation flow (amsDmv) help analog designers bring verification into the digital domain. The blog also commends the Mixed-Signal ToT (Tech on Tour) that is offered around the world for its rich content and practical use cases.

Cadence is focused on providing scalable solutions for mixed-signal designs and has recently published the Mixed-Signal Methodology Guide written by industry experts from Cadence and other leading companies. If you're interested in learning more about Cortex M0 mixed-signal demo and Cadence mixed-signal solution offerings, please reach out to your Cadence representative. One of my earlier blogs also covers the ARM Cortex M0 based mixed-signal demo in detail.

Satish Balasubramanian

ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution

Sathish Bala — Tue, 25 Sep 2012 18:00:00 GMT

I recently came across a Wall Street Journal article,"ARM Chases Bigger Slice of Smaller Chips," that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM based microprocessors are clearly dominating the mobile products from smart phones to tablets across Windows, Android and IOS mobile eco-systems. Most of these devices are using ARM based Cortex A series processors, which provide a very delicate balance between good performance and power efficiency requirements.

However, for ARM, the microcontroller market is still untapped, and this is where ARM is planning its next major push. Before we go any further, I would like to elaborate on what a microcontroller is and how it differs from Cortex A-series mobile processors that ARM sells for smart phones.

Block diagram of pressure control system

Most of the ARM based smart phones have ARM microprocessors (Cortex A series) along with memory and graphics circuitry to provide the mobile experience. A microcontroller is a single integrated circuit that contains embedded processor cores, memory and programmable I/O peripherals. Usually microcontrollers perform a custom function tailored to specific applications.

For example, a Fuel Gauge pressure sensor's function is to monitor the fuel pressure and level at real time. Typically on average, a automobile will have close to 30 microcontrollers performing various critical functions. Now, you can imagine the size of the MCU market compared to smart phones in terms of numbers alone.

Key characteristics/requirements for a typical micro-controller are reliability, low cost, and extreme low power requirements.

Microcontrollers based on ARM's Cortex-M family satisfy the above requirements and more. Cortex-M based MCUs are 32 bit wide compared to 8 bit wide micro-controllers available from other vendors. With 32-bit ARM processors, a microcontroller can process complex instructions in a shorter time and can reduce the on-board flash needed in a 8-bit microcontroller. Also, ARM based microcontroller instruction sets are compatible with ARM based Cortex A series processors, and they fit into ARM's huge ecosystem comprised of 30+ RTOS, Cortex MCO software interface standard (CMSIS), and 10+ tool chains.

Cadence has a long standing collaboration with ARM in design and integration of high performance ARM processors using Cadence's expertise in design tools and methodology. At the Design Automation Conference this year, Cadence's mixed-signal solutions group showcased a demo which focuses on the integration of ARM Cortex-M processors into mixed-signal applications using the industry leading Virtuoso analog/mixed-signal design environment. Cadence mixed-signal solutions address typical MCU design challenges like full-chip verification, low power design, and reduced area, and enables first-silicon success.

Demo system block diagram -- adding analog interface to Cortex-M System Design Kit

The demo models a pressure sensitive Fuel Injection system based on the ARM Cortex M0 based system. It shows how to develop the M0 based system and debug across HW/SW and analog/digital boundaries. It starts with ARM's Cortex-M System Design kit and integrates with AMS and RTL peripherals. Design intent is then verified using system level mixed-signal simulation. Finally, the demo uses the Cadence InCyte Chip Estimator for IP selection and initial floorplan to feed in to the implementation tool for the physical implementation.

If you are planning on developing Cortex-M based processors, this demo will demonstrate how Cadence mixed-signal solutions works well with ARM based processors. The Cortex-M Mixed signal demo is currently available on demand. Please contact your Cadence representative to learn more about the demo and Cadence mixed-signal solutions.

Satishkumar Balasubramanian

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Sathish Bala — Mon, 27 Aug 2012 13:00:00 GMT

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored by Pierluigi Daglio and Marco Carlini from STMicroelectronics that has garnered a lot of interest from the verification community.

Metric-driven verification is the norm for digital designs. But, we can extend this concept to analog/mixed signal designs. Analog/mixed signal verification in the context of full chip verification can achieve a respectable coverage level without compromising on performance levels of digital verification. This can be accomplished by using more robust and abstract analog behavior models such as Real Number (RNM) models using Verilog-AMS wreal as an example. RNM models are also provided in VHDL and System Verilog extensions as well.

Typically, analog verification is based on detailed transistor level simulations run using SPICE-level simulators in a bottom-up flow. Digital verification is based on a top-down approach and has a uniform verification plan using the Universal Verification Methodology (UVM). This metric driven approach uses coverage-directed random stimulus generation and supports multiple verification languages. However, with the trend towards complex mixed-signal SoCs, analog and digital verification cannot afford to stay isolated from one another.

To address the growing verification challenges in today's mixed signal designs, engineers have been using mixed-signal co-simulation. With this approach, the analog behavior models are modeled using Verilog-AMS or VHDL-AMS languages. Mixed-signal simulators are available to then simulate the analog portion using the analog solver and digital portion using a digital event driven simulation engine. But, this approach has 2 key disadvantages.

1. The performance bottleneck of this co-simulation is still governed by slow transistor level analog simulation models. In today's complex digital-centric mixed-signal SoCs, achieving satisfactory coverage level in a reasonable amount of time is an impossible task.
2. The expertise required to write efficient analog behavioral model is hard to come by. A badly written behavioral model can cause huge performance degradation.

Newer approaches to using RNM to model continuous analog behavior in discrete digital models are gaining a lot of traction. The wreal language extension in Verilog-AMS offers the best trade-off between performance and accuracy, and thus helps analog designers achieve acceptable coverage levels. This performance gain is achieved by using fast digital simulators like Incisive Enterprise Simulator to replace extremely slow mixed-signal solutions.

In addition to performance gain, RNM models introduce a metric-driven verification approach as well as assertions to analog/ mixed-signal designs. With assertion-based verification, top-level verification coverage levels can be managed to the specifications as desired.

Cadence has further extended wreal beyond the Language Reference Manual limitations for more effective usage, and come up with flow that is unique and efficient. Apart from supporting wreal extensions in its verification offerings, Cadence is now pioneering key technologies that will make the use of RNM adoption easier for the verification teams.

Here are two new methodologies that are needed to accelerate the metric-driven verification approach for mixed signal designs:

To overcome the inefficiencies in creating models, the process of generating RNM models from schematic design input needs to be automated. This addresses the very important problem of writing RNM models for analog portions.
A streamlined flow is needed to validate the wreal models against the representative analog design. This automated flow will compare the simulation results from RNM and analog design (transistor-level) and provide pass/fail statistics. Once verified, these RNM models are then qualified to be used in a full chip verification flow.

A typical mixed-signal verification flow using RNM consists of the following:

Automated RNM model generation from schematics
Automated RNM model validation using a streamlined approach.
Metric-driven verification approach using Incisive Enterprise Planner and Verification Cockpit
Coverage closure and overall verification plan management using Specman/Specman-AMS

To learn more about this topic, please see the following whitepapers:

Solutions for Mixed-Signal SoC Verification

Mixed-Signal Design Challenges and Requirements

You can listen to an audio recording of the STMicroelectronics EDA360 Theater presentation (June 5, 4:00 pm) and view the slides here.

Sathishkumar Balasubramanian