Qi Wang Blog

Mixed-Signal Technology Summit in Japan Provides Technology Updates

QiWang — Thu, 29 Nov 2012 20:00:00 GMT

Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management ICs. Most such designs are mixed-signal designs and hence the demand for technologies and innovations in this area is very high.

Since we had our first Mixed-Signal Technology Summit in San Jose in September, we received a lot of positive feedback on the event as it provides a good forum for designers and Cadence experts to share knowledge and inspire innovation on a very specific subject. As a result, Cadence held a similar event in Japan (right) on Nov. 29 in Shin-Yokohama. The event was quite successful with more than 70 attendees from various companies in local areas. In this one day event, Cadence provided the latest technology updates for mixed-signal verification and implementation. In the meantime, we had four partners jointly present with us to demonstrate the importance of the ecosystem to support the fast-changing requirements on mixed-signal designs.

Matlab: MathWorks’ presentation focused on importance of linking system level with IC design. In close collaboration with Cadence they showed how Simulink is used to create a bridge from system design in Matlab to circuit design in Virtuoso® Analog Design Environment and Virtuoso AMS Designer. Particularly for mixed-signal design, it is important to preserve models from the system level to the circuit design level to ensure common specifications are met at SoC level. MathWorks and Cadence worked together to use some of most popular Matlab functional models for mixed-signal designs (like ADC, PLL, Power Switch, RF) in Virtuoso AMS Designer simulators by translating them into C-language models.

ARM: The Cortex-M series of embedded processors become more and more popular in many micro-controller designs targeted for mixed-signal and low power applications. In partnership with ARM, Cadence has developed a demo design to illustrate the ease of mixed-signal SoC verification with software debugging capability using Cadence mixed-signal verification solutions. For more information on this demo project, check out this earlier blog Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums.

TowerJazz: TowerJazz presented the schematic-driven (Analog-on-Top) flow (Go to this link for a video recording of an earlier version of the flow at DAC 2012) for designing power management applications in 180nm and 130nm. The flow leverages Virtuoso as the cockpit and uses the OpenAccess database to integrate digital blocks implemented in Encounter Digital Implementation System. TowerJazz provides a mixed-signal PDK to enable smooth interoperability between Virtuoso and Encounter for improved productivity in floor-planning and chip integration.

Cliosoft: Mixed-signal projects are becoming more and more complex, and consequently data management is becoming mandatory to enable smooth collaboration among analog and digital designers. Cliosoft presented the integration of their data-management tools into Virtuoso, validated in collaboration with Cadence-Japan.

There was a very similar event in Taiwan earlier this week and there will be a smaller one in Korea this Friday. For more information on the Cadence mixed-signal solution, go to the newly constructed website for more technical information and customer success stories.

Qi Wang

Recent Events Show That Customer Interest in Mixed-Signal Remains High

QiWang — Tue, 30 Oct 2012 13:00:00 GMT

The well attended Mixed-Signal Technology Summit last month really demonstrated the tremendous interest our customers have in learning new methodologies and techniques for mixed-signal designs. I would like to share some interesting data points based on a survey from the attendees of the event. Among the close to 200 attendees, 73% were designers with analog centric design experiences. However, about 24% of them declared they were mixed-signal designers. It is very clear that mixed-signal design activities are very high and the expertise base is expanding quickly.

When asked about top technology challenges, more than two-thirds selected mixed-signal verification as the number one challenge. Designers are definitely looking for solutions in the verification space to address the ever-increasing challenges of mixed-signal verification at both the block level and the SoC level. On the implementation side, about one-third of the attendees said that the sharing of data/constraints between the analog and digital environment is their top challenge. With the increasing popularity of the OpenAccess based design methodology, I believe we will see significant improvements in this area going forward.

The survey ended at a high note, showing that more than 80% of the attendees would like to come back to such an event in the future, a clear indication of sustainable high interest. The whole event was recorded and we will put it on our website very soon.

Jess Chen (Qualcomm) accepted an award for his contribution to the Mixed-Signal Methodology Book at the Mixed-Signal Technology Summit

We saw similar patterns in other regions as well. Recently we completed a series of Mixed-Signal Tech-on-Tour seminars in the EMEA area. Seven cities were visited in less than two weeks and we had over 250 attendees in total. Two interesting recent blogs covered these events well. One was by Thomas Enserguiex from ARM on “Blurring the Analogue/Digital design frontier”. The other one was by Mladen Nizic from Cadence, in a blog post at the ARM Community titled “ARM and Cadence Team up on Embedded ARM Cortex-M Mixed-Signal Design Solution”. In fact the demo described in this article is one of the most interesting presentations of these seminars. I would also like to thank Thomas and ARM for jointly presenting the demo at all locations.

If you are interested in this demo and you are attending ARM Techcon this week, look for a joint presentation by Thomas and Mladen on Thursday Nov. 1^st at 10:30am. For engineers in Asian regions, we will also have similar events in Taiwan, Japan and Korea very soon. I will not be surprised if we see the same level of interest from those regions as well. Qi Wang

Mixed-Signal Gets Clear Message in China

QiWang — Tue, 10 Jul 2012 23:47:00 GMT

While most of my colleagues in the US were taking a nice break during the July 4^th week, a small group of people including me was on the road for a mixed-signal Tech-on-Tour in China. There was some debate internally on whether designers in China would be interested in such a topic. What we had experienced last week was a clear (not mixed) signal from the IC designer community in China that they are hungry for knowledge in this area, and they want technologies to help them design mixed-signal chips.

The trip was quite hectic, -- 3 cities in a week. It started from Beijing on July 2^nd, then Shanghai on July 4^th and finally Shenzhen on July 6^th. I was particularly worried about the attendance on the first day. The Euro Cup 2012 (Soccer) final game started at 3 am local time, and I know how strong the attraction of this game is for people over there, including myself. I felt relieved when I saw a fully packed seminar room with most attendees arriving on time. I was particularly impressed by the focus and commitment of those attendees, as people were talking notes and asking questions throughout the seminar.

After Beijing, we went on to Shanghai where the designer interest for mixed-signal just blew me away. We had to close our registration site early due to reaching the maximum capacity. The seminar was held in the new Cadence office site in Shanghai within the Kerry Business Center. The training room can accommodate 100 people, but we had more than 120 people come. The room was packed with no standing room! In addition to the great seminar, I was also impressed by the convenience of having many restaurants right below the office. I wish I could have tried them all, but I only had two days there and I had to move to Shenzhen for the last stop of the trip.

The Shenzhen seminar was comparable to the Beijing one in terms of attendance but we had some people came from Hong Kong as well. Overall, the total attendance of the China tour was more than 200 from many different companies. One highlight of this series was the joint presentation with ARM on the use of MCUs in mixed-signal design, and how the Cadence solution makes it easier for designers to design, verify and implement Cortex-M based mixed-signal designs. In fact, the Segment Marketing Manager of ARM in Shanghai, Lifeng Geng, was with us for all three seminars and gave a presentation on embedded processor-based design for mixed-signal applications and the advantages of Cortex-M series from ARM.

We wrapped up the whole series quite smoothly and the team was happy with the turnout. I would have been in a great mood to start a new week except for my miseries on the way back home. I was stuck at the Shenzhen airport for seven hours while waiting for my flight to Shanghai to take off. I felt lucky to arrive in Shanghai in time for the flight to SFO via Tokyo, but the flight from Shanghai to Tokyo was delayed for three hours and the flight from Tokyo to SFO left without me.

Not everything was so bad though. I bumped into Lifeng at the Shenzhen airport as we were both stuck there, even though we were on different flights. We really did not have time to get to know each other at the seminars due to the busy schedule. This incident gave us some good time to chat aboiut technology, work and life, and get to know each other better. I finally got back home on Sunday and I'm thinking about taking the high speed train in China next time.

Qi Wang

Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to Reality

QiWang — Tue, 19 Jun 2012 16:42:00 GMT

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed-signal designs. One main objective of this seminar series is to bring the awareness of the need for a design methodology change to the broad mixed-signal designer community worldwide. The event was very successful and you can find some previous blog coverage here:

M/S Technology on Tour Blog - Model Validation and Assertion Based Verification

Is China Ready for Next Generation Mixed-signal Design?

Analog/Mixed-Signal Behavioral Modeling - When to Use What

Recently, Cadenced announced a new series of worldwide Mixed-Signal ToT events. What’s new this time compared to what we delivered one year ago? One major shift in this new series is that we will focus more on how to deploy the new methodologies into real designs, rather than the methodology itself. Many of the methodologies we had been promoting over the past a few years have become more and more mature with support from EDA tools in production.

In fact, Cadence recently announced the pending availability of a Mixed-Signal Methodology Guide later this summer and showcased the preproduction copies at DAC 2012. To demonstrate that some of the mentioned methodologies are ready for deployment for production designs, we will include four tool demos in this seminar. Depending on the availability of R&D presenters and regional requirements, some or all of the following demos will be shown:

Mixed-signal low power verification demo: CPF aware mixed-signal simulation for designs with power management features, automatic CPF macro model generation for custom or mixed-signal blocks, and application of formal methods for SoC low-power verification.
ARM Cortex M0 demo: Mixed-signal simulation of a Cortex M0 based fuel tank pressure control system using Verilog-A and wreal models for analog components with software debugging capabilities.
Architecture level design exploration demo: Using Cadence Incyte Chip Estimator to explore different IPs in a mixed-signal design to make architectural level decisions for best PPA tradeoff.
Mixed-signal implementation using OpenAccess based interoperability demo: OA based interoperability between Virtuoso and Encounter to enable an integrated physical implementation flow for analog centric mixed-signal designs.

The Mixed-signal ToT starts with a seminar in Taiwan on June 21 and will be expanded to many other different regions worldwide throughout the rest of the year. If you are interested in having the event in your region, please send your request to Kristin@cadence.com.

Qi Wang

What’s Hot for Mixed-Signal At DAC?

QiWang — Thu, 31 May 2012 20:00:00 GMT

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved with for mixed-signal, as well as the latest updates on tools and flows support.

1. Tutorial on Analog and Mixed-Signal Design at Advanced Process Nodes (jointly by TSMC, Freescale, Cadence). Time: Monday June 4^th 8:30 AM - 10:30 AM, repeated at 11:30 AM - 1:30 PM, and again at 3:30 PM - 5:30 PM. Location: 306 (Moscone Convention Center)

2. Luncheon on Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design. Time: Monday June 4^th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)

3. Luncheon on Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs (jointly by ARM, NXP, Cadence). Time: Tuesday June 5^th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)

4. The pre-production release of the industry's first mixed-signal design methodology book, Mixed-Signal Design Methodology Guide. Time: Monday June 4^th - Wednesday June 6^th. Location: Cadence Booth #1930.

5. A demo on applying the latest mixed-signal verification methodology to a design using the Cortex-M0 in an ultra low power application. Time: Monday June 4^th - Wednesday June 6^th. Location: ARM Booth #1414, #802.

6. A floor demo of new tool capabilities to verify low power intent of a mixed-signal design from an analog design environment (Virtuoso) by leveraging digital tool capabilities (Conformal and Encounter). Location: Cadence Booth #1930.

7. Four exciting customer and partner presentations on mixed-signal design in the Cadence EDA360 Theater at Booth 1930:

Monday June 4^th 2:00PM by TowerJazz on AMS Flow for Power Management Designs. (Also in TowerJazz Booth #1105 throughout the conference.)
Monday June 4^th 3:00PM by Maxim Integrated on high-performance, low power ADCs designed in Cadence Mixed-Signal Flow
Monday June 4^th 5:00PM by GlobalFoundries on 28nm Production Ready AMS Reference Flow. (Also in Global Foundries Booth #303 throughout the conference.)
Tuesday June 5^th 4:00PM by ST on mixed-signal verification

8. Addressing Mixed-Signal Functional Verification Challenges using Virtuoso Multi-Mode Simulation. Time: Monday June 4^th 12:00PM-1:00PM, Tuesday June 5^th 2:00PM-3:00PM, Wednesday June 6^th 9:00AM-10:00AM. Location: Cadence Demo Suite #2 at Booth 1930.

9. Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs. Time: Monday June 4^th 3:00PM-4:00PM, Wednesday June 6^th 4:00PM-5:00PM. Location: Cadence Demo Suite #2 & #3 at Booth 1930.

10. Boosting Productivity and Reducing Turnaround Time with an Integrated Mixed-Signal Physical Implementation Flow. Time: Tuesday June 5^th 9:00AM-10:00AM, Wednesday June 6^th 4:00PM-5:00PM. Location Cadence Demo Suite #2 at Booth 1930.

If you are still confused, there is only one way out - go to the Denali Party by Cadence. I wish everyone a fun time at DAC!

Qi Wang

Cadence To Release the Industry's First Mixed-Signal Methodology Book

QiWang — Sat, 26 May 2012 13:41:00 GMT

The new era of “Internet Everywhere” creates a whole new spectrum of applications, ranging from health care, automotive, to entertainment and cloud computing, which demand more and more mixed-signal and low power designs. In fact, mixed-signal applications have become one of the fastest growing segments in the electronics and semiconductor industry.

Traditional mixed-signal designs treat the analog and digital designs as two independent tasks. It has become clear in recent years that such a design methodology will not be able to meet the challenges of current and future advanced mixed-signal designs. For example, on the verification side, mixed-signal designers are facing increasing difficulties in design and verification of complex mixed-signal SoCs, even though there are continuous improvements in the performance of analog and mixed-signal simulation tools. Without a comprehensive mixed-signal verification methodology, first-silicon success will be in jeopardy, which will in turn hurt the profitability of the companies.

On the implementation side, the technology challenges imposed by advanced nodes and tighter integration between analog circuitry and digital control logic demand that designers adopt a methodology to enable seamless analog and digital co-design to meet tape-out schedules and reduce design costs. Such a methodology change has been talked about in the industry for several years, but until now there has not been a complete reference book to document such methodologies and show how they can revolutionize mixed-signal designs.

A new book, Mixed-Signal Methodology Guide, will be released by Cadence in this summer and will meet these requirements. The book is co-authored by mixed-signal design experts from Cadence as well as experts from the designer community. Find out more on www.cadence.com/msmguide. A preproduction release of the book will be featured at DAC 2012 in the Cadence booth #1930.

Qi Wang

What is Digitally Assisted Analog Design?

QiWang — Mon, 30 Apr 2012 23:47:00 GMT

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels.

Unfortunately, compared with the advancement of digital designs over the past decade, the state of art analog design is significantly lagging behind. For example, the throughput of microprocessors doubles every 1.5 years while it takes three times longer to achieve the same advancement for analog designs. Another big roadblock for analog designs is the power consumption. According to Boris Murmann, professor at Stanford University, the equivalent digital gate count in terms of power consumption for a 10-bit ADC at 0.13 um is about 100K, and this number grows almost exponentially for larger ADC and modern advanced nodes.

A new circuit design technique, digitally assisted analog (DAA), delivers a promising solution to address the performance and power challenges to further expand the scope of analog designs to meet today's application requirements. Let's use a simple ADC to explain the concept of DAA:

Figure 1 shows a conventional ADC and Figure 2 shows a DAA style ADC. In Figure 2 a conventional, high performance, power consuming ADC is replaced by a very simple, low-power ADC, followed by a digital post-processor to apply corrections to the output to achieve the same accuracy as the conventional ADC. Compared to the conventional ADC, the DAA ADC has a significant benefit in terms of power and area.

In addition, DAA style designs are easier to port to advanced nodes since majority of the computation task will be performed by the digital post-processor which typically demonstrates an even larger advantage in power, performance and area (PPA) at advanced nodes. With the increasingly wide usage of embedded processors, such as the ARM Cortex-M series, designers can achieve additional benefits in terms of productivity and flexibility thanks to the great software capability of such processors.

The above example just illustrates one specific approach for DAA circuits. In general, in DAA circuits, the assisting digital logic is used to monitor analog performance through the different stages of the operation and to adjust parameters of the analog circuits (such as bias, resistance, capacitance) through calibration loops to meet overall design objectives.

We have seen significant advancements of DAA designs in recent years from the design community, and its proliferation signifies a new era of mixed-signal design. By replacing more and more analog circuitry with digital counterparts to achieve the ever more aggressive PPA targets, we foresee an explosion of new mixed-signal design starts. As a result, the industry is demanding a true mixed-signal design methodology for design, verification and implementation to meet the requirements of such design styles. In the follow-up blogs, we will talk more about how the Cadence mixed-signal solution is best positioned to meet such new mixed-sign design challenges and how you can learn more by joining us at DAC.

Qi Wang

CDNLive! -- The Other Side of the Low Power Design Techniques

QiWang — Thu, 29 Mar 2012 21:34:00 GMT

In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with state retention, dynamic voltage frequency scaling (DVFS), body biasing, and multi-bit flip-flops. Even though each technique can contribute some degree of power savings, not everyone is aware of the challenges and risks associated with each technique. During the Q&A session of the presentation, Annis revealed some interesting back-door facts that can provide some insights into these challenges and risks.

When asked about the challenges about multi-bit flip-flops, Annis brought up the following point. Dual or quad flops will deliver some significant dynamic power savings on the clock tree -- however, the benefits are marginalized when the bits go beyond four, except for highly structured data path logic. The biggest challenge of this technique is in physical implementation where routing congestion may be introduced due to the large cells. Designers may find that more than 90% of the flops need to be implemented with multi-bit flops to achieve the best power and timing.

Back biasing is a simple idea but it certainly has its own challenges. You need some extra routing for the bias supplies, but they tend to be much easier than the traditional power grid design because they carry very small amounts of current. However, to generate negative voltages for the NMOS biasing, you need a charge pump on chip, which by itself is very expensive in terms of silicon area and power!

To avoid this, designers can use reverse bias at the ground connection of NMOS. However, the challenge of doing this is that it requires a ground level shifter, which calls for a new IP design and new methodology for level shifter insertion and checking. How many people ever think about the need for a ground level shifter?

Finally, Annis brought up the importance of new design methodologies for low power mixed-signal designs because of the increasing popularity of low power design techniques in mixed-signal designs. There was another interesting presentation covering this subject in CDNLive! and we will cover it in a future blog post.

Lesson learned? There is no free lunch! Before you decide to use a low power design technique, think twice about the associated challenges and overall costs in terms of power, performance and area. The above presentation will be available soon for CDNLive! attendees from the Cadence CDNLive! site.

Qi Wang

Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

QiWang — Wed, 07 Mar 2012 21:29:00 GMT

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area stands out is mixed-signal design. There are more than 10 presentations with specific focuses on mixed-signal design challenges, and how Cadence tools and flows were used to solve those challenges. Here is a list of related papers in different categories with a list of keywords to highlight the technical contents:

Mixed-signal verification

Real Number Model (RNM) Model Development and Application in Mixed-Signal SOC Verification by LSI on Tuesday
- Real number modeling/wReal, mixed-signal SoC simulation, metric driven verification
AMS Simulation of full duplex USB interface using strength modeled Connect Modules by Texas Instruments on Tuesday
- Mixed-signal SoC simulation, strength modeling, custom connect modules
SPEF/DSPF Parasitic Stitching in Post-Layout Analog and Mixed-Signal Simulation by Cadence on Wednesday
- AMS simulation, parasitic extraction, Spice/Fast-spice
An Efficient Phase-Locked Loop Noise Simulation Using APS & ViVA by Nvidia on Wednesday
- PLL simulation, Jitter/noise analysis, Virtuoso® Power System (VPS)
Verilog-AMS Verification of ADC Soft IP cores by Missing Link Electronics on Wednesday
- AMS simulation, Verilog-AMS, Spice
High Performance, Interoperable Real Number Models for Mixed-Signal Verification by Silicon Labs on Wednesday
- Real number modeling/wReal, mixed-signal SoC simulation, metric driven verification, Virtuoso ADE

Mixed-signal implementation

IC 61 and EDI 10.1 Inter-Operability Flow, Features and Benefits by Maxim Integrated Products on Tuesday
- Open Access/OA, unified analog/digital database, analog/digital interoperability, Encounter® Power System (EPS)
Case Study of Complex High-Speed Mixed-Signal Chip Integration at 40nm by Intersil on Tuesday
- Analog/digital interoperability, digital-on-top methodology
Substrate Noise Analysis and Wide Metal Extraction for Power MOS embedded LSIs by Renesas on Wednesday
- Substrate noise analysis (SNA), wide-metal extraction, QRC

Ecosystem and technology partners

GLOBALFOUNDRIES 28nm Analog & Mixed Signal Production Ready Flow by Global Foundries on Tuesday
- AMS reference flow, 28nm, advanced nodes
AMS Reference Flows for Advanced TSMC CMOS Processes by TSMC on Wednesday
- AMS reference flow, 28nm, advanced nodes, silicon stress, yield
From 6 Days to 6 Minutes: Accelerating Mixed-Signal Design Verification by Orora Design Technologies on Wednesday
- Advanced node, PVT and process variations, mixed-signal SoC simulation, AMS IP integration

What's Hot/What's Cool

A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP by Rambus on Tuesday
- Power gating, low power mixed-signal designs, CPF, Conformal® Low Power (CLP)
Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification by Cadence on Wednesday
- Power aware AMS simulation, CPF, power smart connect modules, CPF generation from Virtuoso Schematic Editor (VSE)

Of course, do not miss the keynote speeches given by executives from ARM, TSMC and Cadence. Go to CDNLive! SV 2012 for more information. See you there next week!

Qi Wang

Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

QiWang — Tue, 28 Feb 2012 14:22:00 GMT

The China Annual Creativity in Electronics (ACE) Awards was established to recognize individuals, companies and technologies that have made profound impacts in the overall China electronics industry each year. Joining with the industry prestigious names like ARM and TI, Cadence Virtuoso AMS Designer won the 2012 Best EDA product award. Five candidates were nominated for this award including Cadence. The award was presented to Cadence at the 17^th IIC China Conference in Shenzhen on Feb. 23, 2012.

AMS Designer is a mixed-signal simulation tool for the design and verification of analog, RF, memory, and mixed-signal SoCs. It is recognized as the most mature mixed-signal simulation tool by the fast-growing electronic designer community around the world. However, that is not the main reason for winning this award. As stated by the mission of this award, AMS Designer was selected as the winner for its recent innovations in areas like wreal (real number) modeling, simulation support for SoC mixed-signal verification, and power aware simulation for mixed-signal designs with power management features. AMS Designer has demonstrated productivity gains and additional verification capabilities in product design.

Congratulations to the Cadence China Team and the AMS Designer team!

Qi Wang