https://community.cadence.com/search?q=*%3A*&category=blog&users=231933&sort=date%20desc&Redirected=trueen-USTelligent Community 12https://community.cadence.com/cadence_blogs_8/b/ip/posts/intel_1920_s-atom_2d00_based-tunnel-creek-soc-with-integrated-pcie-interface-opens-new-era-for-embedded-developersMon, 19 Apr 2010 21:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266037Denali Blog/cadence_blogs_8/b/ip/posts/intel_1920_s-atom_2d00_based-tunnel-creek-soc-with-integrated-pcie-interface-opens-new-era-for-embedded-developers0One of the most ignored Intel announcements of recent memory must be Doug Davis’ early disclosure at IDF (China) on April 14 (see the hour-long keynote video here ) of the company’s new Atom-based Tunnel Creek, an SOC specifically designed for embedded applications. Intel’s Atom processor, a relatively low-powered implementation of the “Intel Architecture,” has been taking the low-end notebook and netbook world by storm. Atom processors also work well and have been rapidly adopted in the embedded world when the embedded product’s block-diagram resembles a PC. However, smaller embedded systems can’t adopt the multichip, chipset-style design of PCs. Many smaller embedded systems require even fewer chips for cost-effective implementation. Enter Intel’s Tunnel Creek, which sports four x1 lanes of PCIe in addition to the Atom processor core; memory, audio, and video controllers; and an LPC block. The simple addition of a flexible PCIe interface means that embedded designers can gluelessly add a variety of different chips to the Tunnel Creek SOC to create embedded designs with minimal BOMs. Figure 1: Intel Tunnel Creek block diagram What can you connect to a PCIe interface that would be useful in an embedded design? Here are just a few ideas that immediately come to mind: An ASSP with a PCIe interface. In the same talk where he disclosed Tunnel Creek, Davis also mentioned that Intel will be developing more than one application-specific I/O hub for specific use with Tunnel Creek. In addition, there are many other likely candidates already on the market such as advanced video/graphics controllers from companies such as nVidia and fast Ethernet controllers from companies such as Realtek. An FPGA. Both Xilinx and Altera offer FPGAs with integral PCIe interfaces. Imagine the ability to gluelessly graft an FPGA directly to an Intel Atom-based SOC. Tunnel Creek should be able to do that. An SSD. You can get PCIe-based SSDs that provide more performance than SATA- or SAS-interfaced SSDs because the PCIe interface is more efficient for high-speed I/O than disk-centric interface protocols. Why add an unneeded disk controller to the mix? Your own ASIC. Intel and TSMC announced earlier that the Atom core would be available to select customers as an ASIC/SOC core. Perhaps you don’t have the production volumes needed to qualify as a select customer for that program but you’d still like to avail yourself of Intel’s processor architecture because of the immense pool of existing software, the many available operating systems for the x86 architecture, and the broad development tool support. Tunnel Creek gives you a way of doing so using a standard processor-based SOC that will likely be produced in fairly high volumes. For lower production volumes, a 2-chip embedded design may well be the most economical. If these possibilities excite your inner design muse, then start bothering Intel to see when you can get your hands on some Tunnel Creek samples.https://community.cadence.com/cadence_blogs_8/b/ip/posts/apple-ipad_3a00_-no-lpddr2_3f00_Fri, 09 Apr 2010 19:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266036Denali Blog/cadence_blogs_8/b/ip/posts/apple-ipad_3a00_-no-lpddr2_3f00_0Guest Blogger: Marc Greenberg, Technical Marketing Director By now it seems that anyone with an engineering degree has probably read 2 or 3 teardown reports on Apple’s iPad. Few that I have seen so far talk about the DRAM memory subsystem -- and that could be because the DRAM was hidden on top of Apple’s A4 processor. Chipworks.com has torn down Apple’s A4 processor package and reports that the DRAM subsystem consists of two Samsung LPDDR1 1Gbit memories in package-on-package (PoP) configuration. The PoP allows for the DRAM to sit on top of the application processor and the whole thing has been marked on top with Apple’s A4 logo. There’s a great cross-sectional photo of the PoP system showing the A4 processor underneath and the two DRAM dice on top. It’s no secret that the iPad has a substantial amount of MLC NAND flash, but the interesting thing for me was Apple’s continued reliance on first generation Low-Power DDR1 (LPDDR1) technology instead of latest-generation LPDDR2. LPDDR1 technology was introduced in 2003 making this one of the oldest technology standards in use in the iPad. Several applications processors already support LPDDR2: - ST-Ericsson U8500 - ">Freescale i.MX508 - TI OMAP4 - Broadcom BCM2763 - Samsung S5PC100 Plus a bunch of others that we at Denali know about but which are not public yet. The specific DRAM in use in the iPad appears to be a Samsung K4X1G323PE according to this die photo . According to the part decoder , we can see this is a 1Gbit X32 4 bank LPDDR1 device with 1.8v IOs. Samsung’s Mobile DDR (LPDDR1) product list indicates that the maximum speed of operation of this die is 200MHz (DDR400). Even though LPDDR1 was introduced in 2003, the 1Gbit LPDDR1 parts are a relatively recent introduction, and the mask date code on the die photo is September 2008. Relying on 1.8V signaling, LPDDR1 has higher operating voltage than DDR3 (1.5v), DDR2L (1.5V), DDR3U (1.2xV) and LPDDR2 (1.2v). LPDDR1 also has the lowest maximum operating frequency of any of the DDR DRAM technologies commonly in use today (DDR2, DDR3, and LPDDR2). LPDDR1 does have lower standby power than any of the DDRx technologies however, surpassed only by LPDDR2. LPDDR1 definitely has its place in applications that don’t need all the LPDDR2 bandwidth and which also need less memory capacity and low standby power. But for a mobile computing-intensive device like the iPad, LPDDR2 would have been an obvious choice. Among the benefits of LPDDR2 are that LPDDR2 offers lower voltage operation (and thus less power), more flexible power management modes, fewer package pins (less costly packages), and higher frequency of operation (more bandwidth) in comparison to LPDDR1. LPDDR2 is specified for up to 533MHz/DDR1066 operation and new designs are commonly specifying up to double the LPDDR1 frequency. LPDDR2 also has the unique property of supporting Non-Volatile Memory (NVM) such as Phase-Change Memory (PCM) on the same bus as LPDDR2 DRAM. This LPDDR2-NVM offers similar performance to DRAM but with less operating power and near-zero standby power and also offers faster system boot and resume from suspend times. The question is, why did Apple not choose the latest generation LPDDR2 parts for the iPad? It could be a couple of reasons. They may not have been able to source 600,000 LPDDR2 dice in time for the launch. The LPDDR2 parts may be at too much of a cost premium. It could have been a hang-over from the iPhone. Or there could be a marketing answer: Apple may have designed the A4 to work with LPDDR1 or LPDDR2 technology. That would allow a later version of the iPad to use LPDDR2 to provide longer battery life and more performance -- enough for multitasking, perhaps? Whatever the case may be, LPDDR2 is an available option on high-end application processors and is ready for all kinds of new designs. Denali has offered LPDDR2 memory models since the early part of 2008 and was making customer deliveries of Denali’s Databahn LPDDR2 memory controllers at the end of 2008. Today, Denali offers high-performance and low-power memory controllers and PHYs for any combination of DDR1, DDR2, DDR2L, DDR3, DDR3L, DDR3U, LPDDR1, LPDDR2-DRAM or LPDDR2-NVM. Find out all the latest information on DRAM technology at Memcon, July 28th in Silicon Valley: www.memcon.com Thanks, Marchttps://community.cadence.com/cadence_blogs_8/b/ip/posts/ddr3_2f00_ddr2-price-crossover-reachedTue, 06 Apr 2010 15:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266035Denali Blog/cadence_blogs_8/b/ip/posts/ddr3_2f00_ddr2-price-crossover-reached0Guest Blogger: Marc Greenberg, Director, Technical Marketing The day is finally here - DRAMExchange.com quoted that the session average price of 1Gbit DDR3-800 parts on April 2nd was $3.03 while 1Gbit DDR2-800 was $3.04. Only DDR2 memory manufacturers will be celebrating... you should realize that this point has been reached because of rising prices on DDR2 to meet the DDR3 prices, not because of falling DDR3 prices. DDR3 has been holding relatively steady in the $2.50 to $3.00 per gigabit range over the last year, while DDR2 prices for 1Gbit have risen from around $1.00 a year ago to over $3.00 today. Denali were originally projecting that the DDR2/DDR3 price crossover would happen sometime in 2009 and here it is in the second quarter of 2010. We have a pesky recession to blame for the delay - in the depths of the recession, some 512MBit DDR2 parts were sold for $0.35 and the DDR2 price remained depressed for longer than predicted. Thanks to the recovery, people are buying PCs again, and many are still using DDR2. What does this mean for you? Well, I should start by saying that this is the *first* price crossover. Prices tend to cross over 2-3 times during the lifetime of the product. As new DDR3 capacity comes on-line, DDR3 prices may drop. As new DDR3 products come on-line, prices may rise. As old DDR2 capacity is turned off, DDR2 prices may rise. As old DDR2 products are retired, DDR2 prices may drop. For the near-term, if you are designing a product where the performance of DDR2 is sufficient, you should plan on supporting both DDR2 and DDR3 in your product to allow you to take advantage of whichever part is cheapest at the time of manufacture.https://community.cadence.com/cadence_blogs_8/b/ip/posts/what_1920_s-on-the-horizon-for-nand-and-dram_3f00_Tue, 02 Feb 2010 20:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266034Denali Blog/cadence_blogs_8/b/ip/posts/what_1920_s-on-the-horizon-for-nand-and-dram_3f00_0Young Choi , Guest Blog for Denali Software January is a time where lots of planning and forecast are made, with high hopes usually. Semiconductor memory industry, after several years of prolonged downturn, finally started to see some glimpses of recovery lately. Prices are improving, product migrations happening, new process node migration providing production efficiency and hopefully more profitability to the manufacturers. The information and data that UBM TechInsights has been collecting on commodity DRAM and NAND Flash products clearly show how semiconductor memory industry has been improving their efficiency measured in terms of Mbit per mm2. For commodity DRAMs, the latest 40 nm class DRAM products show their efficiency of 34Mbit per mm2. When compared to the previous 50 nm class DRAM, 40 nm class shows over 40% improvement. When cost per bit matters the most, 40 nm class DRAM will clearly provide the much needed cost advantage to those manufacturers who have this technology. For those who don’t, they need to find a better way of securing their profitability. When innovation and investment are the name of the game, the gap between the haves and have-nots are obvious, and hence, there is constant movement of joint ventures and merger and acquisitions to create economies of scale. Recent movement of Micron and Elpida, with their respective partner companies in Taiwan, is a clear sign of this. Perhaps later in 2010, we might be able to see the first 4F2 cell based commodity DRAM products. While some DRAM manufactures still have products with 8F2 cell, new 4F2 cell designs combined with smaller geometry would deepen the gap between DRAM makers. For NAND industry, the trends have been staggering. Introduction of 30 nm class products certainly has contributed to the higher efficiency of commodity NAND Flash products for sure. For NAND, luckily three-bit per cell (X3, TLC or 3-bit MLC) and four-bit per cell (X4, or 4-bit MLC) also helped push the envelope further beyond the lithographical limit in terms of bit density (Mbit per mm2). While all of the major NAND manufacturers (Samsung, Toshiba/SanDisk, Intel/Micron and Hynix) have announced their three-bit per cell and/or four-bit per cell NAND products, there are still some concerns about their reliability and performance. This is reminiscent of the times when MLC (two bit per cell) based NAND products were first introduced. The industry and the market had managed the reliability and performance issues successfully and MLC had become the mainstream NAND technology in many data applications. One can expect that the same would happen to three- and four-bit per cell NAND technology, eventually. While the past history or performance of the two key commodity memory technologies, DRAM and NAND, has been impressive and even remarkable, the future has a lot of uncertainties. To help us understand what to expect in the future, the presentation which was given by Kinam Kim at Samsung can be a good reference. This was also published on the Semiconductor International website . A patterning limit chart is shown below: Of course, patterning limit is not the only obstacle to achieve more efficient DRAM and NAND products. There are many other technical challenges for DRAM cell, storage capacitance, isolation, leakage, reliability, floating gate vs. charge trapped flash, double patterning, immersion lithography, so on and so forth. What about new technologies to make DRAM storage cell a thing of past? What about 3D memory? It appears as though the semiconductor memory industry is following the curves shown above (fairly closely so far). The 40 nm class DRAM products and 30 nm class NAND Flash products that were announced in 2009 are the proof. The real test within the industry will come in 2010. Will we see 30 nm class DRAM in 2010? How about 20 nm class NAND Flash? It remains to be seen but some early signs seem pretty promising. It’s January, a month of high hopes and expectation and a lot of planning for another year. Let’s hope for the best of the semiconductor memory industry in 2010. PS: 2010 is a New Year for us as a company, too. Semiconductor Insights, which has been a leader in providing technical intelligence and intellectual property professional services to the semiconductor industry is now called “UBM TechInsights”. For various DRAM and NAND Flash analysis reports (process analysis, circuit analysis and waveform analysis/functional testing) on the latest 40 nm class 1Gbit DDR3 SDRAM, 30 nm class 32Gbit MLC NAND Flash, 30 nm class 32Gbit Three-bit per cell NAND Flash, 40 nm class 32Gbit Three bit per cell NAND Flash, please visit UBM TechInsights’s Open Market Reports page .https://community.cadence.com/cadence_blogs_8/b/ip/posts/the-evolving-enterprise-ssd_3a00_-gartner_1920_s-forecastsMon, 25 Jan 2010 23:15:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266033Denali Blog/cadence_blogs_8/b/ip/posts/the-evolving-enterprise-ssd_3a00_-gartner_1920_s-forecasts0By Steve Leibson for Denali Software The appearance of SSDs into the storage arena is rapidly altering the way large-scale, enterprise-class storage systems are built. Gartner Principal Analyst Sergis Mushell discussed some of these changes at the recent Storage Visions 2010 conference held in LasVegas. Mushell focused on how the introduction of SSDs into the enterprise-class storage device market was reshaping foundation concepts in terms of form factors and interfaces. Mushell started by discussing form factors and projected the graph in Figure 1, which forecasts unit sales of enterprise-class SSDs by form factor: Figure 1: SSD distribution by form factor (Gartner) The first thing to note about this graph is the unit-growth forecast for enterprise-class SSDs shown at the top of Figure 1, from 281,000 units in 2008 to 5.3M units in 2013. That’s a 20x increase over a 5-year period and that’s healthy growth is attracting new and existing storage vendors into the enterprise-class SSD market. Next, notice the relatively rapid decline in the use of 3.5-inch, enterprise-class SSDs. Although these drives constituted the bulk of the enterprise SSD market in 2008, Mushell's chart predicts that 3.5-inch SSDs will become a mere sliver of the market in 2013. At the same time, shipments of 2.5-inch, enterprise-class SSDs appear to stabilize at approximately half of the market. The big percentage growth forecast is for board-mounted SSDs either as PCIe expansion cards or as plug-in DIMMs--not really drives at all. These forecasts are consistent with three industry trends. First, the unrelenting application of Moore’s Law doubles NAND Flash capacity about every 18 months, so volumetric requirements for the same storage capacity shrink accordingly. Hence the decline of the relatively large 3.5-inch form factor. (Old-timers in the storage industry might crack a smile at the idea that 3.5-inch drives are “large.”) Second, there’s no particularly good reason why SSDs should be packaged in form factors that are based on the requirements of mechanical rotating storage (hard disk drives, HDDs). Existing HDD form factors are artifacts of platter-size choices and the actual dimensions represent a logical physical progression from 8-inch and 5.25-inch HDDs down to 3.5- and 2.5-inch drives over several decades. Server designers often find these existing HDD form factors to be troublesome. SSDs can assume any convenient or odd form factor because they’re entirely electronic and made of ICs. They initially adopted HDD form factors to allow easy, drop-in replacement of existing HDDs but the use of HDD interfaces is really just another anachronism, as the rapid forecast growth of PCIe-based and DIMM-based SSDs suggests. Which leads to the third trend and the next graph Mushell displayed, shown in Figure 2: Figure 2: SSD distribution by interface (Gartner) This graph forecasts market share for the enterprise-class SSD market by interface type. Note the dominance of Fibre Channel SSDs in 2008, which is consistent with a disk-replacement strategy. Fibre Channel has dominated enterprise-class storage thanks to its high transfer rates but that dominance is ending for both HDDs and SSDs as faster SAS and SATA interface standards appear. Figure 2 forecasts a rapid decline in shipments for SSDs with Fibre Channel interfaces, which predicts that the percentage of enterprise-class SSDs shipped with Fibre Channel interfaces will plummet from nearly 70% of all enterprise-class SSD shipments in 2008 to virtually nothing in 2013. According to this forecast, Fibre Channel’s reign washes away in three waves. The SATA (serial ATA) interface represents the first big challenger to Fibre Channel’s dominance, followed by SAS (serial attached SCSI), and finally by PCIe, which isn’t an HDD interface at all. SAS and SATA HDD interfaces have been pressed into duty as SSD interfaces for at least two logical reasons. First, these interfaces have become dominant because of their widespread use for all HDD classes, not just the enterprise class, which means that the storage industry has developed a tremendous infrastructure to support these two HDD interfaces. That infrastructure includes everything from driver, OS, and database software; to drive testers; to cables, connectors, and built-in chipset support. In any market, broad infrastructure support and the correspondingly reduced implementation and support costs constitute powerful compatibility incentives that drive vendors cannot ignore. Second, as HDD manufacturers enter the SSD fray either by developing their own SSD architectures and designs or by buying SSD vendors outright, the use of HDD interfaces on SSDs presents the appearance of a unified product line to customers. Left alone to their own world of storage, existing drive vendors with established HDD product lines have no strong need or wish to differentiate SSDs based on interface type and prefer to offer either type of storage to their customers as plug-compatible alternatives. Established drive vendors’ predisposition to support and maintain legacy HDD interfaces opens the door wide for new SSD vendors that do not have legacy HDD interfaces to support. As discussed in a previous blog entry , it’s possible to develop SSD architectures that easily outperform HDD interfaces simply by increasing the number of parallel NAND Flash channels in use. It’s not possible to perform the same trick with HDDs. To get higher data rates from HDDs, manufacturers can: Spin the disks faster--but at 15,000 RPM, enterprise-class HDD platters are already under severe mechanical stress. Increase the number of read/write heads that can be active simultaneously--which constitutes a radical, substantial, and costly architectural and electronic change to HDD design. Add a second servo actuator with another set of read/write heads and another set of read/write electronics--which is completely out of the question from an economic perspective. Consequently, some SSD vendors are beginning to use faster interface standards that are not constrained by disk-centric assumptions that have been baked into standard HDD interfaces including even the latest versions of SAS and SATA. PCIe is a good example of such an unconstrained interface. A 16-lane, Generation 2 PCIe interface provides 8 Gbytes/sec of throughput (much more than SAS or SATA) and a 16-lane, Generation 3 PCIe interface provides 16 Gbytes/sec of throughput. These substantial throughput rates underlie Gartner’s forecast for the eventual decline of all HDD form factors and HDD interfaces in SSD applications. Related Information : Why the Solid State Drive Market is Poised for Growth Mr. NAND's Wild Ride: Warning -- Surprises Ahead! Does MLC flash belong in enterprise SSDs?https://community.cadence.com/cadence_blogs_8/b/ip/posts/ssd-interfaces-and-performance-effectsMon, 25 Jan 2010 23:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266032Denali Blog/cadence_blogs_8/b/ip/posts/ssd-interfaces-and-performance-effects0By Steve Leibson for Denali Software IDC ’s Research Director John Rydning and Micron ’s Director of SSD Marketing Justin Sykes tackled the merging abilities of fast enterprise-class SSDs and evolving disk interface standards, particularly SATA 6G (also called SATA 6.0) and USB 3.0, while speaking on a panel about the technology of storage during the Storage Visions 2010 conference held early this year in Las Vegas. Rydning spoke first and he compared and contrasted two new external disk-interface standards, namely USB 3.0 and eSATA 6.0. These standard disk interfaces improve on their predecessors. USB 3.0 maximum data rates are 3.2 to 4.8 Gbps versus USB 2.0’s 480 Mbps--a 6.7x to 10x boost in theoretical I/O performance. SATA 6.0 and eSATA 6.0 essentially double the theoretical maximum data rate of SATA 3.0 and eSATA 3.0 from 3 Gbps to 6 GBps. Consequently the new SATA 6.0 and eSATA 6.0 interfaces are theoretically faster than the new USB 3.0 interface just as SATA 3.0 and eSATA 3.0 are faster than USB 2.0. The SATA and USB standards seem to be in lock step with respect to adoption rates according to Rydning. He showed comparison graphs that forecast increasing adoption rates for both SATA/eSATA 6.0 and USB 3.0, with some minor amount of adoption in 2010 and about 50% market penetration for each interface by the year 2012. To aid this transition, laptop makers have started to build eSATA interface ports into laptops. This is not a particularly difficult feat because most motherboard chipsets include several SATA ports so implementing an eSATA port for such a machine is a matter of adding an eSATA connector to the laptop motherboard. For desktop and enterprise-class server systems, adding an eSATA port requires little more than a SATA extension cable that connects the motherboard SATA connector to an eSATA connector mounted on a metal expansion-card bracket or a case bulkhead because SATA ports are plentiful on most desktop and server motherboards. Rydning also pointed out that officially, eSATA connectors supply no power to the external SATA drive but connector manufacturers have developed an “unofficial” hybrid eSATA/USB 2.0 connector that allows a properly designed cable to tap into the co-located USB port’s 5V power while simultaneously coupling the eSATA disk-interface signals to the external drive. Sykes’ panel presentation corroborated Rydning’s and provided some important test data to reinforce some of Rydning’s points and to make new ones. First, Sykes presented a historical chart showing the uneven throughput progress for SCSI and ATA disk interfaces as they evolved into the SAS (serial attached SCSI) and SATA (serial ATA) interfaces. SCSI/ATA/SAS/SATA disk interface data rates over time (Micron Technology) The graph shows that the SCSI disk interface led in throughput until both SAS and SATA interface standards hit 3 Gbps around 2005. With the development of a 6 Gbps standard in 2008, the SAS interface pulled ahead of the SATA interface and will remain in the lead even with the development of the new SATA 6.0 specification. Sykes then showed a different sort of performance graph for an existing MLC (multi-level cell) SSD using SATA 3.0 and SATA 6.0 interfaces: MLC SSD performance with SATA 3.0 and SATA 6.0 interfaces The graph shows that sequential reads for this particular SSD benefit greatly from the faster interface although the read speed does not double with a doubling of the interface transfer rate. This result indicates that the SATA 3.0 interface definitely limits this SSD’s read performance. Although the SSD’s random read performance benefits some from the faster disk interface, the SSD’s sequential and random write performance essentially gains nothing from SATA 6.0. These figures could lead you to the wrong conclusion, so take care in your interpretation. What the above figures do show is that the drive being tested was designed and optimized for the SATA 3.0 interface. In other words, the number of NAND Flash channels implemented in the tested drive is sufficient to support the SATA 3.0 data rate. Slapping a faster interface on this existing SSD architecture doesn’t produce a substantally faster SSD. To fully exploit the faster performance abilities of the SATA 6.0 interface, SSDs need more internal NAND Flash channels to boost internal read/write parallelism. That’s what Sykes’ next graph depicted: Boosting NAND Flash channels increases SSD performance to SATA 6.0 rates (Micron Technology) Increasing the number of NAND Flash channels implemented in an SSD substantially increases the SSD’s read and write speeds (using either multi-level-cell or single-level-cell NAND Flash devices). In fact, the theoretical performance of SSDs that support 16 or 32 active NAND Flash channels greatly exceeds the bandwidth of 6-Gbps disk-interface standards, which means that the SAS and SATA disk-interface standards will need to evolve even further to keep pace with future SSD developments.https://community.cadence.com/cadence_blogs_8/b/ip/posts/ssd-and-hdd-economic-forecast_3a00_-analyst-jim-handy-speaks-outMon, 25 Jan 2010 23:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266031Denali Blog/cadence_blogs_8/b/ip/posts/ssd-and-hdd-economic-forecast_3a00_-analyst-jim-handy-speaks-out0By Steve Leibson for Denali Software If you’re waiting for solid-state drives (SSDs) to overtake hard-disk drives (HDDs) as the storage device of choice in computers, servers, and consumer devices then Objective Analysis ’ Jim Handy has a message for you: It’s not happening any time soon. Handy’s been following storage trends for many years. He’s tracked the pricing trends of HDDs for a while and SSDs for their short but dynamic life. Based on his presentation at the recent Storage Visions 2010 conference in Las Vegas, here’s what Handy forecasts: Courtesy of Objective Analysis (www.objective-analysis.com) The cost/Gbyte for HDDs is roughly 20x lower than for SSDs and Handy expects that relationship to be stable for the next 20 years. Sure, the cost/Gbyte will decrease for both types of storage device, but HDDs will remain the low-cost leader for high-capacity storage. These predictions are built on some “basic truths”: HDD capacity doubles every year or two The minimum price for an HDD seems to have bottomed out at $50 NAND Flash device capacity also doubles every year or two When NAND Flash stops scaling (see the previous Denali Memory Report blog post “The End of NAND Flash as we Know It: Micron’s Dean Klein and Samsung’s Tony Kim Look at Life After Flash” ), some other non-volatile semiconductor memory will come along to continue the cost/Gbyte trend for SSDs These raw numbers are fascinating, but the implications for storage consumers and marketers are even more interesting. For example, Handy asked the question “What can you do with $10 of NAND Flash memory now and what will you be able to do with it in twenty years?” He answered that question with the following graph: Courtesy of Objective Analysis (www.objective-analysis.com) Today, you can store about a thousand songs on $10 worth of NAND Flash memory. You can store perhaps one or two standard-definition (DVD-quality) movies or two HD (Blu-ray quality) movies. As NAND Flash capacities rise, you’ll be able to store more music and more movies for that same $10. Around the year 2026 or 2027, said Handy, you’ll be able to store the entire iTunes music catalog--all 10 million songs--on $10 worth of NAND Flash. That information nugget suggests that there will someday be consumer-class devices that will ship pre-loaded with every song you might ever want and that you’ll merely pay a fee to unlock the songs that you want to hear. Don’t believe it? Well, back in the year 2000, the music companies didn’t believe they’d be selling songs by subscription instead of quaint plastic discs called CDs. Now CD sales are way down and iTunes rules the roost with downloadable music. Then Handy asked a similar question about HDDs: What can you do with a $50 HDD? Here’s the graph he showed to answer that question: Courtesy of Objective Analysis (www.objective-analysis.com) Today, you can store more than 100,000 songs or 100 DVD-quality movies on a $50 HDD. By the year 2017, you’ll be putting the entire iTunes catalog, all 10 million songs, on that same HDD. By the year 2025, you’ll be able to fit the entire Internet Movie Database ( www.IMDB.com ) movie catalog--500,000 films--on one $50 HDD. By then, once again, you may be buying a consumer product preloaded with every movie ever made and simply paying a fee to watch the movies you want. Handy claims that people will eventually collect movies on hard disk as they do now for music. Currently, people buy or rent DVDs and Blu-ray discs rather than keep them in HDD storage but eventually media storage will be so inexpensive that even movies will disappear comfortably into the maw of a $50 HDD. A subsequent panel of teenager media users underscored that point at Storage Visions 2010. The young panelists described their current media-consumption habits. Unlike their parents, they never buy music CDs unless giving them as gifts. They download all of their music. However, they currently do want physical DVDs and Blu-ray discs. Their children probably won’t.https://community.cadence.com/cadence_blogs_8/b/ip/posts/the-end-of-nand-flash-as-we-know-it_3a00_-micron_1920_s-dean-klein-and-samsung_1920_s-tony-kim-look-at-life-after-flashThu, 21 Jan 2010 17:21:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266030Denali Blog/cadence_blogs_8/b/ip/posts/the-end-of-nand-flash-as-we-know-it_3a00_-micron_1920_s-dean-klein-and-samsung_1920_s-tony-kim-look-at-life-after-flash0By Steve Leibson for Denali Software Today, NAND Flash is king of the semiconductor memories in terms of cost per bit, a position it has held since 2004 or 2005. Consequently, NAND Flash serves as the technology driver for semiconductor processing--a position previously held by DRAM, processors, and FPGAs. The top NAND Flash semiconductor vendors are currently fabricating NAND Flash memories using 3x nm lithography (34nm for Intel and Micron, 30 nm for Samsung). By some technology estimates, there are now only two generations left in the life of NAND Flash as we know it today. At the current pace of NAND Flash generational development, two generations equals 36 months. After that, NAND Flash device capacity will clearly stall unless some new development changes the fundamental design of the NAND Flash semiconductor memory cell. That's not just alarmist talk for the purpose of controversy. One of the people making such claims is Micron's Dean Klein, Vice President of Memory System Development, who delivered these warnings in a keynote at Storage Visions 2010 held earlier this month in Las Vegas, just before CES. The Incredible Shrinking NAND Flash Memory Cell (From the keynote presentation by Micron’s Dean Klein) Some of the looming NAND Flash problems involve the inability of smaller-geometry Flash memory cells to safely handle the high programming voltage (25V) needed to induce electron tunneling, memory-cell crosstalk, parametric degradation of dielectrics at shrinking geometries (layers are now just a few atoms thick), and the fact that NAND Flash cells are already so small that the presence or absence of fewer than 200 electrons on the floating gate makes the difference between a digital zero and a one. Because of these growing problems, said Klein in his keynote, it will be very difficult to employ semiconductor process geometries smaller than 20nm for existing NAND Flash memory cell design. Klein then took one step back from the brink by noting that people previously said NAND Flash could not break through the 40nm barrier but obviously it did. Semiconductor process and design wizards found ways to overcome those limits and those same wizards are searching for ways to overcome the present problems, but there is not yet enough visible progress to believe that a solution is imminent said Klein. One possible path to a solution is to employ 3D or vertical NAND Flash cell stacking, which would double chip capacity without shrinking the memory cell size. If successful, 3D stacking could add another two NAND Flash generations and postpone the need for a NAND Flash replacement technology for five to eight years according to Klein. NAND Flash vendors will use 3D stacking if it proves sufficiently practical, but only if it's practical. In the end, semiconductor vendors always take the path of least resistance, said Klein, and there are candidate technologies that promise non-volatile alternatives to NAND Flash. Klein listed MRAM (magnetic RAM), FRAM (ferroelectric RAM), PCM (phase-change memory), resistive RAM, and crosspoint memory as candidate replacement memory technologies. Again taking a step back, Klein then stated that all of these replacement memory technology candidates currently have warts but his personal pick for the eventual winner is PCM. Micron isn't the only semiconductor vendor staring down the loaded barrel of the NAND Flash scaling problem. In a one-on-one interview just prior to Klein's keynote, Samsung's Flash Marketing Director Tony Kim said much the same thing. Going to smaller NAND Flash geometries is becoming very difficult said Kim. Vendors are investigating different materials and designs for the NAND Flash memory cell’s floating gate, different cell architectures, 3D stacking, and multi-level cells (storing more than one bit per physical memory cell). However semiconductor technologists can see that time is growing short, there is an end to the technology, and so they're all seeking a high-volume semiconductor technology that will overthrow the current king of non-volatile memory, NAND Flash.https://community.cadence.com/cadence_blogs_8/b/ip/posts/the-flash-factor-for-consumer-devices_3a00_-will-nand-flash-and-hard-disk-storage-coexist-or-fight-to-the-death_3f00_Wed, 13 Jan 2010 23:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266029Denali Blog/cadence_blogs_8/b/ip/posts/the-flash-factor-for-consumer-devices_3a00_-will-nand-flash-and-hard-disk-storage-coexist-or-fight-to-the-death_3f00_0By Steve Leibson for Denali Software If you spend a lot of time reading and thinking about solid-state drives (SSDs), you may have gotten the impression that NAND Flash storage is at odds with hard-disk storage--that it's a winner-take-all situation. In his keynote at last week's pre-CES Storage Visions 2010 conference in Las Vegas, storage analyst Tom Coughlin dispelled that notion with some cogent slides and some insightful analysis. Coughlin founded the Storage Visions conference; he's the chairman of the annual Flash Memory Summit ; and is the author of Digital Storage in Consumer Electronics published by Newnes Press in 2008. According to Coughlin’s free companion White Paper Flash & HDD -- Symbiosis, or Survival of the Fittest (published under his Objective Analysis market-research banner), Flash-based consumer applications such as personal music and video players, digital still cameras, and camcorders actually contribute to additional sales for hard disk drives (HDDs). Coughlin began his keynote remarks with the following forecast slide, which shows the shipped storage capacity for optical disk drives (ODDs), HDDs, and NAND Flash devices from 2006 through 2014. HDDs will still be carrying the bulk of the capacity load by the year 2014 but NAND Flash’s storage share will grow significantly, to 274 exabytes of storage shipped compared to 427 exabytes of storage for HDDs. (One exabyte equals one billion Gbytes.) Note that Coughlin's prediction suggests that 2014 will be the first year that NAND Flash annual shipped capacity will exceed the annual shipped capacity of optical drives. How do these immense numbers arise and where's the symbiosis between HDDs and NAND Flash memory? In his White Paper, Coughlin lists three examples of consumer applications where NAND Flash sales depend on and support HDD sales: digital still cameras (DSCs), personal music and video players (PMPs), and Flash-based camcorders. According to Coughlin's White Paper, the average DSC user shoots an average of 549 photos per year and the average photo size is 4.7 Mbytes. That's roughly 2.6 Gbytes of photos per DSC user per year that needs storage. DSC and camera phone sales are rising at 5% per year, the average image size as measured in Mpixels is growing at 25% per year, and the number of photos that DSC and camera phone users are generating appears to be rising at a rate of 24% per year. Do the math and you'll find that the amount of storage needed to hold these photographs is increasing at a compound rate of 63% per year, based on Coughlin’s assumptions. As a result, almost two million drives per year will be sold to store digital images in 2014. Couglin notes a similar symbiosis for HDDs with respect to PMPs. He writes that the average PMP owner's music and video storage needs are roughly 3:1 for HDD and PMP storage space. With the average PMP storage capacity now at 4 Gbytes, that's presently 12 Gbytes of HDD storage for each Flash-based playback device. In addition, most downloaded music and video must pass through a PC’s HDD (internal or external) before ending up on the PMP, which makes the HDD's existence that much more critical to PMP use. Again using some simple growth assumptions, Coughlin expects that PMPs will drive incremental HDD sales of 42 million just for music and video storage by 2014. Using similar scenarios, Coughlin predicts that Flash-based camcorders will drive sales of an additional three million HDD sales in 2014 and online (cloud-based) storage for consumer images, video, and music will drive sales of an another incremental two million HDDs in 2014. The total comes to nearly 50 million incremental HDD sales annually--about 5% of total HDD sales--by the year 2014 as shown in the following figure. That’s symbiosis. And what does NAND Flash get from this relationship? Coughlin posits that the availability of inexpensive HDD storage encourages the sale of DSCs, PMPs, Flash-based camcorders, and other Flash-based multimedia consumer products. In the case of camcorders, he goes even further, claiming that a majority of the projected Flash-based camcorder sales “would never be sold if hard drives weren’t available.” That’s symbiosis. “Altogether,” writes Coughlin in his White Paper, “our projected 2.2 exabytes of Flash memory [sales] in 2014 (estimated to be 59% of the total consumer Flash demand) would be significantly smaller if HDDs were not available to support them.” That truly is symbiosis. So if you were thinking that Flash in the form of SSDs and other Flash-based storage arrays were going to kill off HDDs in the near future, Coughlin would strongly disagree. He sees a long, cooperative future ahead for the two technologies and he has published data publicly to back up that claim.https://community.cadence.com/cadence_blogs_8/b/ip/posts/low-power-ddr-options-_2d002d00_-from-the-trenchesWed, 06 Jan 2010 22:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266028Denali Blog/cadence_blogs_8/b/ip/posts/low-power-ddr-options-_2d002d00_-from-the-trenches2by Marc Greenberg, Director of Technical Marketing, Denali Software Momentum for LPDDR2 is building. It's mostly in the mobile space, and it's been in the general area of Handsets, MIDs, and other mobile devices. Both high-end and low-end handset customers are seeking LPDDR2 support, which is interesting since LPDDR2 was initially thought to be a high-end technology. Long-term, LPDDR2 devices are expected in a lot of embedded applications where DDR3 is unsuitable for various reasons. When it comes to building chips today, the LPDDR2 market is still maturing and device availability is just now coming on-line, so chip guys need to hedge their bets by supporting at least one other memory technology, sometimes more. The first hedge for pure handset folks is an LPDDR2/LPDDR1 combo. This allows them to get into a low-power memory with LPDDR1 or LPDDR2 technology, but the performance for this combo is limited by LPDDR1 which has a maximum clock rate of 200MHz (DDR400) and in reality, 166MHz is the popular frequency for LPDDR1. So, this doesn't work for high-end solutions since they are sacrificing performance or would need to deploy a wider interface. The second hedge is DDR2. DDR2 makes a nice combo with LPDDR1/LPDDR2 because the IO voltage of DDR2 is 1.8v, same as LPDDR1, so you don't need a different oxide in the IO if you were already supporting 1.8v for LPDDR1. DDR2 is the low-cost memory leader and available up to 533MHz (DDR1066) today. So the LPDDR1/LPDDR2/DDR2 combo has been popular for most of 2009. Lately, more companies are looking forward at DDR3. DDR3 offers the advantage of a 1.5v I/O and for the most part DDR3 is built on smaller process geometries so uses less power in general. The chart below shows a comparison of different memory technologies at the same throughput. The take-away from this chart is that a 16-bit DDR3 running at 333MHz (DDR667) is about the same power as a 32-bit LPDDR1 running 166MHz(DDR333) so there is equal throughput and similar power usage between DDR3 and LPDDR1. Click to enlarge This is not a completely fair comparison -- there are lots of things not considered: SSTL IOs of DDR3 use a lot more power than the LVCMOS pads of LPDDR1; DDR3 needs termination which uses power; Those 16 extra DQ pins (plus 2 DQ and 2DMs) required for LPDDR1 also use power; LPDDR1 can go into a low power mode more often and more easily; LPDDR1 uses less power in standby; etc... So, let's look at the decision-making process: if I am a high end mobile customer, I need LPDDR2, that much is certain. I probably want to hedge my bets with another memory technology to ensure that I have supply of some memory in case LPDDR2 is expensive or unavailable. If I choose LPDDR1, I need to put down 2X the IO pins for data to get into a part that uses 10% less power than DDR3, remembering that LPDDR1 was first introduced over 6 years ago. Or, I keep the same number of IO pins, use the most mainstream memory for 2010 and beyond (DDR3), and live with 10% more power usage in my memory. Finally, with mask costs and chip development costs being what they are, everyone has an eye on being able to use their chip in more than one application space. Even if the chipset is primarily mobile, with the projected cost of DDR3 being less cost per bit than DDR2 starting in 2010, DDR3 becomes a "must-have" for new chip designs.https://community.cadence.com/cadence_blogs_8/b/ip/posts/guide-to-denali_2700_s-synthesizable-ddr-phyTue, 17 Nov 2009 18:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266027Denali Blog/cadence_blogs_8/b/ip/posts/guide-to-denali_2700_s-synthesizable-ddr-phy0Click on a frame for slideshow view. Enjoy! Databahn DDR-PHY Databahn DRAM Memory Controller IP DDR-PHY.ORGhttps://community.cadence.com/cadence_blogs_8/b/ip/posts/reflections-on-life-and-death-in-the-memory-sector_3a00_--spansion-and-qimonda_2c00_-long-on-technology_2c00_-have-too-few-friends-in-high-place_2400_Wed, 05 Aug 2009 20:24:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266026Denali Blog/cadence_blogs_8/b/ip/posts/reflections-on-life-and-death-in-the-memory-sector_3a00_--spansion-and-qimonda_2c00_-long-on-technology_2c00_-have-too-few-friends-in-high-place_2400_0Hammered by market events, two significant memory suppliers suffer in Chapter 11 of bankruptcy. For one, Qimonda, it is almost over, as its assets are being liquidated just as the DRAM market shows near-life again. For the other, Spansion, the final chapter is yet to be written, but whatever emerges from its Chapter 11 bankruptcy later in 2009, it will likely be a far smaller and less potent player that it was in 2008 and 2007. Its highly regarded NROM/CTF technology, with numerous and far-reaching advantages over the more traditional Floating Gate flash technology, merits hardly a mention in its current survival and reorganization discussion. This essay is a (or should we say, 'another'), discussion of important factors which enable some memory makers to survive while some are forced to withdraw, merge or disappear. It also strikes at the general naviete of calling our beloved 'memory segment' a part of 'the technology sector', when, in times like these, technical prowess plays a distant second, or third role is the quest for survival and success. Ultimately, technology is secondary to timely management right-decision-making, to product portfolio and positioning, to investment and mis-investment, to having a banker's prudence, and to having 'friends in high places', who can keep you on life support until a better day. Companies who considered themselves live-or-die-standalone businesses have mostly died; those who considered themselves de facto arms of government or larger business entities, or parts of 'banking groups', are still around...not well, but not dead, either. Consolidation is nice, but..: Everyone calls for 'industry consolidation', but no one can describe exactly how it happens, and every instance is different from every other one. Even attempts to orchestrate mergers run into resistance. Creditors who have much to gain by tough and realistic decisions to foreclose enterprises, remain passive. Gaining consensus among all interested parties is nearly impossible, so long as anyone has any leverage...and everyone has enough to stall decisiveness and tough choices. It is rarely a matter of two companies waking up one day and saying, "Today I will merge with so-and-so." Independence dies hard, as we have seen in the nearly-a-year-long shotgun (or BB gun, in this case) consolidation that has so far failed to combine ANY of Taiwan's four DRAM makers (or six, if Inotera and Rexchip are counted...or 10, if one includes Taiwan's technology partners Elpida, Hynix, Micron, and Qimonda). While partnerships have been made and other alliances have been broken, precious little 'consolidation' (and those only piecemeal and ragtag) have happened in ways that improve the industry’s efficiency and the survivability of its players. The foremost two casualties of the present memory downturn who, so far, appear to have taken the biggest hits, are NOR/NVM maker Spansion, and the residual of Siemens-Infineon's memory group, Qimonda. Both have market and technical roots that are decades old...Spansion was a "Junior Intel" in EPROMs as long ago as the mid-1970s, as they were in Fast SRAMs and MPUs. Siemens, almost always a solitary outpost for EuroDRAMs, put its DRAM stake in the ground about the same time. So, it's been 30+ years for each of them. Each has had ups and down over the long haul and many 'cycles', but neither Qimonda nor its predecessors when it was a part of Siemens or Infineon, was ever the market leader that Spansion was, in NOR flash, until it finally cried "Uncle" for protection from its creditors. Indeed, it was not until the mid-1990s that Infineon showed its independence and original contributions in DRAM technology, until then relying mostly on licensed designs and technologies from Toshiba, IBM and Mitsubishi. In 2007, before the memory downturn grabbed hold, Spansion was a $2.5B NOR flash player, and top of the game in the wireless space, with more than 35% share of the NOR flash market. Qimonda was the #3 DRAM maker, with revenues of more than $4.1B., with more than 14% of the DRAM market and a strong G-DRAM market position. What counts, or seems to count, in today's market : Whatever their market standing, however, they have both been remarkable assemblages of technical talent in a world that is steadily moving to one of "Right Management Makes Right", easy access to friendly capital, and little mistakes with big consequences. Taking one's eye off the ball for so much as a few minutes can spell disaster...and in this business, many lethal balls are in the air, in surprising places, at all times. Still, that Powerchip and ProMOS, or even Hynix...each with far less technical talent that Qimonda and Spansion (IMHO)...can out-survive these companies tells us something about what it takes to stay alive in the economic downdraft and onslaught we have faced this round. The "Technology Sector" might rightly be named the "Friendly Banker Sector", as that seems more to determine who lives and who dies. Investment timing and asset management count for a lot, and preemptive cash flow actions count for a lot. Low cost manufacturing is important, as always. Pricing leverage with key customers, to avoid the intense pricing in the commodity market spaces has counted for a lot this time. Technology counts for something, but is not the be-all and end all of success. At the end of the day, management's appreciation for, and response to, the pending crisis...what they realized, what actions they took, and when they took those actions...has shown itself to be the difference between life and death. Oh, yes, and sadly, who your friends (with money and patience) were and are, was critical. Those who had the capacity to expose huge risks to their shareholders and creditors, and keep spending when all hope was lost, and then, when those pathways were exhausted, go back to their bankers and governments, have consistently dominated the more timid and business-prudent competition. Not that what they ended up with at the other end was 'good'...with its persistent low margins, large-and-larger capital calls for new fabs and new technology, and providing "long-term care" for businesses that they themselves created, but then were forced to suffer with 'until a sunnier day'. Near Death today...Death Tomorrow: Since the early 1990s in memories (and sometimes before that, too), there was no 'sunnier day' ahead for profits that even came close to making up for the losses suffered in such 'survival downturns'. Not even close. The exception, the early-to-mid-1990s, saw a wholesale retreat by Japan from the chip market, leaving a vacuum for anyone to fill, profitably. Since the end of 1995, the 'memory industry' has been a net sinkhole for money, by a wide margin, though some players with some products have sometimes made it a good business. But, even in the industry's good times, the seeds of later destruction were already planted, but had not yet poked through the soil. Good profits were added to outside capital and plowed back into the industry, ensuring a supply glut later on and also, at the same time, that R& D had to be maintained at a high level to cost-reduce to meet those low prices. Wise men (who left) and a very few excellent business men (who stayed competitive) made the right decisions, in retrospect; the vast majority of memory industry players stayed way past closing time, and when the final tally was completed, could only have been deemed failed business ventures. But, if economic theory tells us anything, it says "Do not do this." Let the failures fail, clear the market, free up the resources to make useful product with true EVA--Economic Value Add. Otherwise, the industry will persist in taking two dollars of resources to make one dollar's worth of end product, creditors and shareholders will lose their investments, as the eventual day of reckoning will come.https://community.cadence.com/cadence_blogs_8/b/ip/posts/rethinking-ssds_3f00_Thu, 23 Jul 2009 13:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266025Denali Blog/cadence_blogs_8/b/ip/posts/rethinking-ssds_3f00_0NAND Flash's SSD Vision: Wholesale replacement of HDDs by SSDs in the huge market for PCs and laptops archival storage has gleamed in the eyes of NAND Flash makers ever since Apple kicked the microHDD out of the iPod Mini and made it a SSD/Flash based iPod nano in 2005. Maybe it occurred even before that, but it had not caught the popular fancy, or seemed within reach until it happened with the 4GB or 8GB MP3 players from Apple. Almost instantly, flash makers set their sights on displacing, over time, huge swaths of the market for HDDs in laptops...250M units a year, variously averaging 160GB-400GB each. Over the timeframe of 2004 through the end of 2008, NAND Flash came down in price nearly 100x. Most NAND flash applications fell easily under the sway of MLC NAND, with its lower costs (prices), which were gladly accepted in exchange for its reduced performance and endurance (specs). However, much of the SSD space claimed to need, and depend on, SLC NAND for sufficient specmanship and performance. Still, as in all applications, MLC was steadily improved in its performance, and 'patched MLC' NAND, with advanced software and sometimes hardware improvements, eventually became acceptable for many or most HDD replacements. However, the latest data and analysis from Digitimes [24 Jun 2009: SSD penetration in PC market remains low, Members only] indicates that laptops with SSDs, in 2009, still will be only about 1.5% of total laptop shipments (though Gartner ramps it up to 20% in 2010, but we shall see), and the price of SSDs is most often given as the critical shortcoming amid a host of technical benefits for SSDs, real and perceived: lower operating power, faster reads and writes (easy random accesses), and G-force ruggedness. But, all performance issues aside (which are now 'no news'), it is the SSD pricing that is keeping them away from wholesale adoption in the compute space. While some technical criticisms remain, the most significant limitation is cost or price: Corsair's newest 128GB SSD carries a retail price of $414, against a HDD of similar capacity, for which it's easy to find 160GB HDDs for under $100 (and as low as $35). The Corsair SSD line-up has better performance, to be sure: 240MB/sec reads and 170MB/sec writes. But it will probably take a while for the consumer to understand what that means to him in terms of improved workload processing, impatiently waiting for data, and productivity. Today, one has to ask what this extra $300 might be worth to the user, or how large that class of users who value SSD over HDD, at +$300, might be. Or, is this the BEST place to spend an incremental $300 on a system that costs about $1250 +/- $250, given other software and performance boosters that are available. Adding +25% or so in price is, yes, a significant price uplift for SSD's 'turbo speed' compared to HDD. For sure, some users and applications REALLY need the increased storage speed that SSDs offer. But, most, we think, will likely bide their time and wait for the eventual improvement in the "SSD Value Proposition". Even in the low-capacity drive space, 32-64GB, SSDs are the high-priced spread, by a wide margin. So unless SSD makers can sell the 'consumer benefits' of their product better, the market will be thin for a while. The eternal hope of SSD and NAND Flash makers, that future NAND price reductions will bring HDDs within striking distance of NAND-based SSDs, is offset by the persistent trend in PC/Laptop applications and use, to 'demand' larger and larger capacity disk HDDs...by up to 20%/year in the high volume PC and laptop segments...today 160GB or 250GB, and tomorrow 200-300GB. Overtaking the HDD-in-laptop capacity trend line is a tall order for SSDs: the larger the drive, the more cost advantage HDDs have. Put that on top of the fact that what we have seen 'recently' (the past five years) in NAND price reductions is probably an unsustainable trend, and will have to be slowed down due to technical barriers and the current lack of profitability among NAND makers. Nearly exhausted by running so fast for five years, and sinking so much money into technology and fabs, they have barely come close to the lagging end of HDDs, as they find their capital nearly spent. What we see today in the SSD space, is early adopters, those who REALLY value lower power and better R/W performance of NAND Flash. But so far the price is steep, and a general overtaking of the broader HDD market, at least with pure SSDs, is not in the offing unless something changes pretty dramatically, no matter what the flash price curves look like. If one looks at the average prices of either laptops or desktops in the past 10-15 years, too, it is down-down-down. There is huge resistance to increasing prices for the "Typical System", no matter what the performance, or what the performance improvement is. Sure, there are high-end systems, more costly and with more performance. There is always a spread of users and applications, from ultra-cheap and performance limited, to ultra-expensive and powerful. But it is the Middle Class where the high volume is. Unless SSDs can crack that nut, they will forever be elite specialty customer plays. Changing mindsets: So, with the experience of about five years of talking, designing, building and selling SSDs, we collectively have a greater understanding of what might lie ahead, and/or how apparent barriers to SSD adoption might be overcome. For one, our concept of the "Computer-HDD" market, and its applications, has to be de-homogenized and scrutinized several levels deeper than viewing it as some monolithic construct. There are large groups within the market which will embrace SSDs, while others are too price-sensitive to do so. If corporate IT managers can find a way to keep employees from filling up their computers with home movies, vacation photos and other large GB applications, maybe a desktop computer with a 32GB SSD is plenty for most workers' legitimate business needs. This, however, is contrary to the PC trend of the past 30 years, to 'client empowerment'. But, it is not impossible. Consumers can ask, "What is faster seek time worth, really?" Designers can ask, "Are there interface conventions and legacies that could be circumvented or overcome with some kind of clean-slate, fully optimized flash drive approach?" So far, the Solid State Disk crowd has been thinking totally IN the box...the box made, defined, interfaced, prescribed by nearly 30 years of HDD-in-PC experience, from the time of the PC-XT in the early 1980s: a pure scaled-down IBM System mainframe memory subsystems...MPU-L1-L2-(L3)-DRAM-Disk-(DVD backup). The form factor and interface of SSDs, so far, is to make them drop-in compatible for HDDs, without disrupting the existing system architecture. Surely, the industry can do better than that, given the power and promise of raw NAND Flash's truly disruptive technologies. For a while, it looked like the netbook might be the breakaway from HDD, with something of a clean slate on which to draw hardware and system software from the ground up. But though the market is exciting and fast growing, it has not embraced the SSD in a significant or innovative way. In fact, HDDs hold the high ground in the current crop of netbooks, though we are still a long way from the finish line, as varieties of small "computers" proliferate. So, what form of storage will be adopted in this part of the market it is not a settled issue. Still, for the broad masses of laptops and desktop PCs, a complete SSD solution is probably not within reach any time soon (like, by 2013 or so), though undoubtedly, they will be picked up by early adopters, and those with special workload requirements. Much of the early enthusiasm, and many of the agressive penetration forecasts have been tempered by time, and by the hard market realities. But, all is not lost, by any means. Flash Caches are again in the news : Perhaps a more promising approach is a recurrence of flash-caching , in which a smaller SSD (a booster 'flash array', or HDD cache) with good software, can come close to the performance of a full solid state drive, but with the bulk of the system GB still on the HDD, at far lower cost (or 'average cost/GB') for the total system. This concept first appeared years ago in the early days of SSD-talk, but was quickly dismissed in the clamor to go directly to SSDs. Development, more discussion and market, technical and pricing realities for all competitive products have resurrected talk of HDD caching methods and systems. Today, we understand better, we have better flash-cache products, better hardware and software, and we see the naivete of thinking NAND flash would catch and surpass HDD in overall system cost, for the capacities widely in use in computer hard drives.https://community.cadence.com/cadence_blogs_8/b/ip/posts/nand-forward-price-drops-will-slow-significantlyThu, 16 Jul 2009 23:03:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266024Denali Blog/cadence_blogs_8/b/ip/posts/nand-forward-price-drops-will-slow-significantly0Author's Note and Errata: There were some errors in the forward NAND pricing in the version of this article as it originally went to the web on Thursday evening, July 16, which have now been corrected. We apologize to 'early readers', who may have been confused by some inconsistencies between the text and tables. Future NAND price reductions will be much less than what we have experienced : Users of NAND Flash have become accustomed to annual price reductions of 50-60% over the past five years, built on strong GB demand growth averaging more than 150% per year. However, a conspiracy of events...financial, technical, economic and 'perceptual'...are expected to slow this rate of price decline by up to 90% for the next five years: from 100x price/GB improvement to 10x improvements...or even less. In addition, the industry is definitely facing a point where higher performance NAND will truly cost more per GB than lower performance NAND (endurance, RW speeds, or other valuable metrics), just as SLC NAND costs more than MLC today, but is used only in selected 'cost justifiable' applications. When x3 and x4 cells' share of the market grows, and SSDs gain further traction, a highly-fragmented market is almost a certainty, and the hi-low price spread for various flavors of 'flash' could be as large as 5x, solely on differential costs to produce various performance and endurance feature-sets. In short, the NAND marketplace can be expected to take on a whole new character for the five years out to 2014, as technical progress aimed at cost reduction becomes more expensive and harder to come by, as 'performance degradation remediation' becomes more complex and 'controller-logic-and-software' intensive, as NAND vendors are forced by their managers and shareholding masters to make it a good business, and as new markets cannot develop and expand fast enough to sustain the former GB growth rates. Most of the low-hanging (technical) fruit for NAND cost-reduction has been picked: In the past five years, lithographic shrinks were at first easy to achieve, as NAND caught and then surpassed DRAM as the 'memory process node leader'. The move from 'SLC to MLC' was low-hanging fruit waiting to happen; almost everyone had proven it out in the lab and fab years earlier, and it just took some 'seed crystals' of market competition to precipitate a wholesale transition in the market (exc. Samsung). Sustained high GB growth brought improved scale economies into play, too, as "SG& A and R& D per GB of NAND shipped" declined almost in proportion to GB growth. Also, much progress in price reduction has come at the expense of beating down manufacturers' profit margins to the point that 4Q08 was 'all red for all vendors and all products'. Indeed, 2008 ended on something of a hard stop to all this, with moves to x3 and x4 cells stalled for a variety of technical reasons, and with troubling performance hits, as well. Manufacturers' profit margins were at bare metal levels, or lower. The "One a Year" lithography shrinks, density-doublings and process node migrations are today not always affordable (tight cash and non-existent profits), but also technically more forbidding. Much new technology has to be investigated and mastered..."85-90nm to nom. 40nm" is far easier than "35-40nm to nom. 20-22nm" is expected for 2014 will be. The look ahead, pricing progress: The modest NAND price recovery we have seen in 1Q and 2Q is just a time to rest and regroup, but the eventual resumption of price competition and reductions will be much more measured than formerly. No vendor can afford price reductions of ~50%/year any more; no one is capable of cost reductions of anything close to that. Importantly, many of the iconic personalities who bet on the sustainability of the fast growth investment and R& D strategies of the past period are moved on, in light of stubborn markets, declining profits and huge financial damage in the past year. New NAND demand and markets for growth will also need 'cultivation'...and time: On the demand side, most NAND used today is relatively primitive, compared to its expected technical potential. A vast fraction of the GB used are lodged in applications with modest RW capabilities, tolerance for large innate silicon imperfections and failure rates (then corrected), and limited endurance. This too, was low hanging fruit: camera chips riding the digital camera transition, USB drives to replace 'floppies', audio store for MP3 players...almost all replacing technologies that were well past their prime. These were also 'ready markets' requiring little market development by vendors, thus avoiding a time-consuming and irregular growth path. It will not be so easy going forward, and the huge price down strides made by NAND in the 2004-09 era are not likely to be matched. One has to look no further than SSDs, to get a feel for the difficulties and costs, the hit and miss, as well as the technical, standard-setting and price-performance roadmaps that have to be argued, developed, applied, rejected or modified for new and sophisticated markets to develop. It is a slow and painstaking development process. In addition, current and forecast prices always attract new applications; if one stifles the outlook, it may stifle the energy seeking new places to take advantage of "Sea Change Pricing" that has been a part of the NAND Marketing Call for many years. Historical NAND prices, 1Q 2004 through 4Q 2008 $/GB 1Q04 1Q05 1Q06 1Q07 1Q08 4Q08 All NAND 147.80 40.81 23.97 8.00 4.53 1.62 Est. SLC % 95 50 40 20 6 4 "in best of worlds", SLC price is 2x that of MLC, though it has varied widely over the past several years (see Denali BLOG articles) Industry's perpetual efforts to cost reduce, and demand diversification, will drive broader product mix: What we see as a still rather narrow line-up of NAND 'performance' capabilities will become a sprawl, as elemental technologies are applied in novel and unique ways to serve diverse markets, having different needs and price points. More bits per cell always (so far, for all vendors and all products) means lower performance. "SLC to MLC" meant endurance dropped by about 10x-20x, from 100K cycles to 5-10K write cycles. For most applications, users would rather have the 'half-price' pricing than the 100K cycles. SanDisk was able to keep performance the same going from x2 to x3, but not without some considerable remediation: productivity went up only 20%, not the expected 50% in bits per mm sq., due to extra 'performance-management' circuitry. Fewer stored electrons per memory bit means more finely tuned sensors, and, almost invariably, more die area, reduced performance and more build cost. In addition, SanDisk seems, a year later, to be the only company with x3 in volume production, and that not even at their most advanced process node, which has deliberately lagged by one node their cutting edge SLC and 2MLC production nodes. And though a move to x4 would give production cost benefits comparable to those gained when the industry moved lockstep from SLC to MLC in 2004-6, it is no slam dunk technology, by any means. Tight R& D budgets, resulting from huge operating losses for the past year, will not make anything easier. It is not likely, or even not possible, for all NAND vendors to have fully developed their "nom 22nm x4" technology in 2013/14. No chance. Today, the line up looks as shown in Table 2, NAND Makers lithography, MLC status: Estimated NAND Makers' Technology Status, Mid 2009: Hynix 48nm (65%); 41nm (35%), no x3 in market Samsung 51nm (20%); 42nm (70%); 30nm (10%), MLC but no x3 in market Toshiba/SanDisk 43nm (35%), x3; 32nm (65%) MLC IMFT 34nm MLC (90%+), no x3 in market note: percentages refer to fraction of wafer starts at that process node Bold guesses: NAND price outlooks : If NAND prices "today" (using 12/31/08 as 'today') are nom. $2/GB for MLC, then by the close of 2013, we expect to see a smattering of x4 NAND, with severely constrained performance, with best-NAND pricing of about 50-60 cents/GB. SLC and "SLC level performance", needed in some applications, is denied the benefits of the move to more bits per cell, since device performance is too compromised using today's design methodologies, so the $4.00/GB+ for SLC of today maybe declines to less than $1.25/GB by year end 2013, with progress coming largely from litho node moves, making some allowance for moving to sustainable profit margins and better cell constructs and continuing improvements in scale economies. Estimated NAND prices, 1Q 2009 through 4Q 2013 $/GB 1Q09 1Q10 1Q11 1Q12 1Q13 4Q13 SLC 4.00 4.00 3.00 2.10 1.45 1.20 MLC 2.00 2.00 1.40 0.95 0.60 0.50 x4 NA NA NA 0.50 0.32 0.26 (or lowest perfomance grade) In fact what we have seen in much of the NAND flash market pricing is a thinly concealed compression of vendors' Gross Margins, coupled with a capacity of chip designers to 'engineer out costly features, performance', which today's NAND end-markets can easily do without...'defining down demand' attributes...and replacing what in retrospect can be viewed as "Cadillac NAND" with "Tinplate" or "Plastic" NAND, at far lower costs to build but fully adequate for most of today's needs. Full priced SLC was shipped in 2004, because there was no half-price MLC. Once MLC became available, it was found to be 'good enough' for 'almost all' applications. But it is not at all clear if x3 and x4 performance, without significant costly 'performance remediation' WILL be 'good enough for those same uses. Consequences and impacts of price slowdown : This "Sea Change Pricing Model" moving to a new "Change of Heart Pricing Model" can be expected to cause major changes in the industry's view of end markets, vendor investment expectations, competition and potential market consolidation. Importantly, huge NAND price reductions in the past five years have enabled SSDs to barely make a dent in HDDs into PCs; with declines slowing, how does that change our thinking about the outlook for SSDs? This will be the subject of our next BLOG, next week.https://community.cadence.com/cadence_blogs_8/b/ip/posts/low_2d00_power-memory-subsystems-imperativeFri, 10 Jul 2009 14:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266023Denali Blog/cadence_blogs_8/b/ip/posts/low_2d00_power-memory-subsystems-imperative0The figure below was put forth at the recent Denali MemCon, in a speech by Samsung's Dr. Sylvie Kadivar. Memory and Memory Subsystems (MSS), long accused of being the bottleneck to higher system performance, and 'throttling' the MPU with their high latencies and addressing limitations, now finds itself also as the "bad boy of power consumption." Other server system elements have made great strides in power reduction, but at the end of the day, memory 'owns' more of the system power consumption than any other system element. Server Farms, recently a sign of 'advanced internet evolution', are now in the Stink Pen insofar as energy consumption is concerned. And though steps are underway to reduce power of the MSS, after all is said and done, 'It's the Memory Subsystem, Stupid'. For most memory designs, too, cost reduction (= die size reduction) remains their foremost objective, though, to be sure, power has moved closer to the top of the design objectives list over the past few years. For the 50nm node products, the main benefit appears to be productivity: moving from 65nm to 50nm, plus the evolving benefits of superior designs, give 2x the die/wafer and more performance. Ceteris paribus , however, power comes down only fractionally, unless the 65nm design was 1.5V and the 50nm was 1.35V. The tools for reducing power consumption among memories, with some liabilities for performance and build cost, are understood, though many possibilities also lie in wait. Reducing operating voltages, as has been the mode recently, is pure goodness; the high-performance speed bins still seem within reach; the user gets 20% power saving, almost for free...x2 to get the power savings for reduced air conditioning and assorted system build costs. But, one might ask, if this is such low hanging fruit to go from 1.5V to 1.35V, why not go one more step without a pause, to 1.2V, and get double the benefit? And, even 1.2V does not seem to be any other than an 'industry convention'. Systems with 1.0V or even 0.9V have also been demonstrated in test vehicles, and seem fully achievable...though maybe not productionable for all the end markets that DRAMs serve. Should more finely-segmented arrays be an option that goes back on the table, to reduce power? For complex server DIMMs, with 36 to 72 chips on each of them, is there a place for 'intelligent design', and more informed and advanced control of the elements that make up DRAM power consumption...refresh, chip and array select, power-down modes? Mobile MSS power issues/concerns: In phones, and in the larger mobile segment, one of the great forces trying to squeeze DRAMs out, comes from the power-concern side: Swapping NVM/PCM for DRAM makes for nonvolatility AND fast read-write. The MSS (meaning, in this case, LP DRAMs + NVM) constitutes up to 30% of standby power consumption in mobile phones, so it is a big hit on talk time, and makers are 'motivated' to get the power down or out. Laptops and Desktops: Though LP DRAMs of sorts have been around for many years, we know of no laptop computer which uses them. The memory subsystem is not the power hog it is in phones, and the savings by using 'LP' DRAMs over PC DRAMs, is not enough to justify more MSS cost with higher prices DRAMs and 'LP' DIMMs. However, we have seen in just the past six months, an early and quick take-up of DDR3 DRAMs in laptops, highlighting their lower power capability. Some of this is 'green marketing' to concerned buyers, but the power savings are real, though perhaps of little consequence in terms of battery life. BUT, laptop interests, which now make up more than half of PC unit shipments, and their low-cost cousin, netbooks, may be the force that tips the DRAM voltage discussion in favor of a quick move to 1.35V and then 1.2V DRAMs. What's not to like? For desktops, cost is paramount and they are almost all plugged into the wall. But, so as they have wagged the DRAM tail for so long, maybe they are about to lose control of the DRAM voltage or LP feature roadmap, be hoist by their own petard , and eventually have to make do with 'what the other guys define, and make'...as others so long have had to dance to their fiddle. With netbooks being the fastest growing computer segment, by a wide margin, and something of a tabula rasa as far as legacy system design constraints, maybe the Netbook marketplace will entice new DRAM lower power technical developments which then will migrate UP into laptops and PCs. With 20M+ units a year, and +2GB per system, maybe DRAM vendors will try for power differentiation in new and innovative DRAM and MSS designs. Servers: Server DIMMs, historically pushing the chip-density and DIMM density envelopes, pose the microelectronic version of what the server owner reads on his utility bill. Around the server industry today, 8GB and 16GB DIMMs are the new bleeding edge, and even if they use the newer DDR3 DRAMs, or better still, DDR3L, servers are still rather huge power consumers, constraining system design, mandating larger power supplies, heating and cooling, fans airflow, 'hot spots', etc. IBM Goes from 'Bipolar' to 'CMOS' in early 1990s, dislocates people, fabs and technology roadmaps: Maybe I am reminded of an anecdote I first heard when I went to IBM in 1995. Until IBM decided to reform its chip business in the early 1990s, and let loose of its 'backward' ways, all the close-in and high-speed system caches were bipolar...lagging the merchant industry's embrace of CMOS over HS bipolar which occurred as much as a decade earlier. But, in addition to the fab process problem, letting loose of all its bipolar capacity in Fishkill, NY (vacating Dutchess County, NY, as it closed down and eventually refit its fab to run CMOS), the major complaint came from the board designers, who had gone to great lengths to 'handle the bipolar power problem'...heat sinks, fans, intricate thermal analyses, limitations of chip layout density on the boards...system cost and performance constraints. This kind of problem the 'memory industry' faces today; whether there is a simple "bipolar-to-CMOS" solution so close at hand as there was in the early 1990s for IBM, remains to be seen, but seems not probable. More likely, the solution will be piecemeal, and made up of many evolutionary changes over a long period of time. In servers, FB DIMMs was a start three or four years ago, to attack the limited address capability of Registered DIMMs and, for sure, some things were learned along the way. But FB DIMMs had no traction, and a limited following, and were subsequently replaced by better (and denser) R DIMMs..and been wholly replaced by a separate discussion for the follow-on generation of server DIMMs, so called Load Reduced (LR) DIMMs. FB DIMMs was maybe the last 'technical challenge' that was pure performance-driven, with little regard for power, which eventually came back to bite them in the AMB. But the power problem, so long pushed aside in favor of 'more performance', is real, it is here, and it will get worse before it gets resolved.https://community.cadence.com/cadence_blogs_8/b/ip/posts/denali-memcon_3a00_--huge-hit-in-a-tough-marketWed, 08 Jul 2009 14:40:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266022Denali Blog/cadence_blogs_8/b/ip/posts/denali-memcon_3a00_--huge-hit-in-a-tough-market0Denali's 2009 Edition of MemCon, its Annual Storage and Memory-Only Conference held 22-24 June in the Hyatt Regency Hotel in Santa Clara, drew approximately 1150 attendees over three days. After Monday's Denali 'Product Tutorial and Training Sessions', which drew more than 250 attendees, the formal MemCon presentation sessions followed on Tuesday and Wednesday, with nineteen presentations and four panel sessions filling the two days, from 9am until past 6pm. Fortunately for the memory industry, signs of recovery have been apparent for about the last two or three months, so there was reason for business optimism. But, no matter how much the profits and headcount of Silicon Valley's corporations have been impacted during this worst-ever downturn, new ideas and technical advances just keep on coming. This year's theme, "Beacons of Innovation", was apropos , and MemCon brought new products and technologies to the fore, and improved understanding to more mature discussions and products. Now nearly forty years old, the 'semiconductor memory industry' is hardly maturing. The industry's future, the technical and standards roadmaps, and the issues are as hotly debated as ever they were, albeit at line geometries that are 100 or 1000 times smaller, and costs that are 100 or 1000 times larger. And, we should add here, risks that are also 1000 times larger. In chips, everything scales up, or scales down! The full MemCon agenda can be found at www.denali.com/memcon My favorite take-aways and impressions: SSD talk; still talk: The topic of SSDs has been a mainstay at Denali's MemCon for about four years, often viewed as the Next Big Thing and market driver for NAND Flash. Indeed, one might surmise that SOME substantial fraction of the est. $35B invested in NAND manufacturing capacity in 2005-08 was exactly for the purpose of supplying that market demand. But with still weak take-up of SSDs from netbooks, to laptops through desktops, and onward to the enterprise market, the bloom is off the rose more than a little, to hear what most speakers were saying: the message is still positive, but manufacturers are clearly disappointed with the size and commitment to today's bona fide "SSD" business level, and probably tomorrow's SSD market outlook. NAND prices are still way too high compared to HDDs, despite declines of 50-60% per year for those same past five or so years. No sooner than one technical 'whattabout' raises it head, and is resolved, than another shows up to again retard the significant adoption of SSDs in the top-to-bottom computer line up. To the rescue, to continue the march to improved storage performance economics, come more improved caching systems (see Denali CTO Mark Gogolewski's talk), more software tools and a better understanding of system 'usage models', which get more out of less. This evolutionary process, without huge leaps into the SSD unknown, nor buy-in of fast evolving, expensive and (some say) unproven technologies, is making the transition to total solid state both more measured, but also less risky. Still today, big unknowns still lie ahead for SSDs (or, as it were, the 'known unknowns' like "what will be the cost, and performance impact of x4 cells and sub-25nm processing?), just as the industry probably under-appreciated the issues it would face in displacing a significant fraction of those HDDs that were in computers, from the vantage point of back in 2004 and 2005. Performance NVM market: In fact, even though ONFI has been here for several years, and toggling for only slightly less, the high speed NAND flash market is still in its infancy. It is still viewed as having undiminished promise to deliver NAND and SSD bandwidth in multiples of what is widely available today. Ed Doller, in his kick-off keynote, showed a slide of today's NVM applications, dominated today by NAND, in which a huge fraction of the GB lodged in low-performance end of the spectrum: USB cards, DSC chips, Compact Flash, MP3 players. No wonder they can use x3 cells, with sometimes 10K or even 1K write cycles endurance. There remain strong believers in a high-end promise of the fundamental NAND technology, which includes the vast majority of NAND-based SSDs, as well as heretofore unrecognized applications. Indeed, much of the Performance NAND effort today is truly pathfinding and technology development, and every week brings a new product announce which sets a new high standard for R/W performance, endurance or cost-performance. All in all, 'Performance NAND' is just getting started, with standards, technical capabilities, and applications all evolving lock-step to exploit what is widely felt to be NAND's huge performance and low-cost potential.. Almost from the beginning, no matter how much the talk was of HDD/vinyl/tape displacement markets, it was recognized that the "NAND-market-fitting" exercise would be comprised of developing its core technical promise, concurrently with developing applications that can project those technical benefits into a product that the market would buy. There has been a constant back-and-forth between NANDers, saying "Here's what we can offer, what we can do"...and users who were seeking to define their uses, and refine their spec and performance needs, to match those of the silicon suppliers. The devil is in the details: Heading down that same 'spec' and 'performance capability' road, we also heard in Numonyx, EasyCo and others' talks, that software and improved system design can deliver significant improvements in NAND endurance, bandwidth and RW performance...only it is not here yet, and faces an uncertain market--more of the NAND 'Double Do' Problem: what can the silicon do and what does the application need. These are very much two moving targets, with the entire industry trying to sort it out. These several talks posited a new lever that the designer could pull for system performance improvement: delving into the exact details of how the device was to be used, or was being used...'usage models'...and applying more system and silicon knowledge to take advantage of unique features of the application or the silicon. Repeat after me: Market Fragmentation is coming...or maybe not: If I heard the words "Fragmentation of Product Mix" once, I heard it a hundred times in the course of MemCon. The market needs a more diverse mix of DRAMs and NAND flash to best serve its technical needs and low cost requirements. For markets which place huge pressures on commoditizing their constituent products, and 'terminate with prejudice' any attempt to add bells and whistles, this is a new froce that has to be reckoned with...and we can only wait to see where it comes down. It does not appear that gravity can pull the pieces together, either for NAND or for DDR3 DRAMs. New products, and new applications of available flash and DRAM technology, will appear and be accepted or rejected by the market. For DDR3 DRAMs it is now, PC DDR3 and DDR3L(V) for 'low voltage', which, instead of the Standard 1.5V, can be 1.35V and maybe eventually 1.2V), plus Low Power DRAMs...LP DRAM, Mobile DDR and LP DDR2, plus Graphics DRAMs (or G DRAMs). For NAND, the SLC of 2004 has become MLC and now soon x3 from some vendors; most expect an eventual x4 cell that can store four bits, with yet t.b.d. performance and cost for the 'degraded sockets'...and another shoot out the top for HS NAND flash: toggle of ONFI interfaces and roadmaps. Efforts to pull all these contradictory and conflicting trends together, to reduce the product set to a small number of parts, are being thwarted by application trends that need either low cost or high performance, to nearly the exclusion of the other characteristic. All of that is just my 'tip of the iceberg'. There's much more on the Denali MemCon website, www.denali.com/memcon, which has PDFs of all the presentations, actual webcasts of some presentations (with audio), and a MemCon Community website with discussion links to like-minded attendees and others interested in the discussion and topic of this year's MemCon. Again, we'd like to thank our Platinum Sponsors, Samsung and Rambus, our Gold Sponsor, Numonyx, and our Silver Sponsors, EasyCo, SanDisk and SPMT. We'd also like to thank our track sponsor and Conference Partner, Web-feet Research for their support. We know how scarce funds have been since the fall financial meltdown, and appreciate their continued support.https://community.cadence.com/cadence_blogs_8/b/ip/posts/ddr3-drams-update-in-june-2009Mon, 29 Jun 2009 13:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266021Denali Blog/cadence_blogs_8/b/ip/posts/ddr3-drams-update-in-june-20090Abstract: DDR3 DRAMs, after a long period of floundering about, wondering 'when they would happen', have gained much traction in the marketplace in the past six months. With new efficient and high-performance DDR3 designs in production at all major DRAM makers, they are clearly on their way to "PC DRAM Domination", though today they are still only about 20% of total DRAM shipments. The DDR2-to-DDR3 Rubicon is crossed, though many uncertinaties lie ahead as the industry simultaneously moves through its painful consolidative phase, desperate to restore profitability, and to 50nm processing, across-the-board efficient 6Fsq cells and a hit-and-miss transition to uniform 1.35V operation by all vendors in all applications by the end of 2010. Today's DDR3 take-ups in PCs are 'incrementally faster, definitely lower power'...and are appearing in 2Q's genration of laptop product line refreshes, more than in desktop systems. Power, low power, is increasingly a co-equal driving force for DDR3 adoption. What has changed since late 2008: As late as 3Q and 4Q08, DDR3 DRAMs could only be found in high-end game PCs, where they were attractive for their higher performance, and where the market could support their higher prices. In early fall, DDR3 DRAMs still cost 2x-4x DDR2, though admittedly, DDR2s were at something of an all time historical low of 60 cents. Today, DDR2 prices have come up a lot, and are now in the $1.05-$1.20 range for 1Gb ($9 or $10 for 1GB DIMM), closing the gap from the bottom. But newer DDR3 designs have also reduced the earlier die-area disadvantages, thus reducing production costs. And DRAM makers seem to have decided, 'If we are shipping $1 with every 1Gb DRAM, it might as well be a DDR3 DRAMs, which has a future...and that Taiwan's price bombers do not have yet to any appreciable degree.' At the crossover speeds, DDR2 800/1066 and DDR3 1066, prices are very close to one another. At DDR3-1333, there is a mixed and sometimes significant premium for DDR3 compared to slower DDR2s, which, if the history of DDR1 and DDR2 pricing is any guide, will be whittled down to nothing in a few quarters' production and use. DDR3-1600 is still not found in any PCs that we have seen...but for DDR2, recall DDR2-533 was kicked off 3Q04, DDR2-667 took up 1Q06, and DDR2-800 was really a 'post-mid-2008' phenomena (and still growing, displacing -667s) Low Voltage DDR3: Last year, the industry devised an alternate Low Voltage Roadmap for DRAMs. The standard DDR3 spec called for 1.5V operation, which had been decided nearly a decade ago. The low voltage roadmap agreed on last year calls for a 1.35V option, designated DDR3L, which saves about 20% in power (subject to many other considerations and conditions, of course). But most vendors can hit the performance spec even with this reduced voltage, so it is expected to be adopted widely; all major DRAM makers have 1.35V product and roadmaps; Samsung and Micron announced DDR3L server DIMMs and SO DIMMs a few days ago, for (almost) everyday applications...and it is only a matter of time before "L" comes to dominate DDR3 production. There is also an even more agressive 1.2V discussion and emerging DDR3 (or DDR4) spec, but it is still too remote to forecast the timing and extent of adoption...but the preponderance of heat-spreaders on DDR3 DIMMs should give some indication of where the power problems lie. DRAM makers have consistently been able to produce the top speed grade at high yields, for DDR1 (>-400 to -600) and DDR2 (>-800/1066 to -2100), so they have wisely been reducing the operaing voltages, for 'green considerations' without compromising premium sales. For users, this "L" roadmap is 'free' power reduction. Off the charts, too: While the DDR3 specs are -800, -1066, -1333 and -1600, an additional bin at -2133 is under discussion...mostly aimed at PC makers. However, there is a vibrant market for gamers and overclockers, which offers many other variations...-1800, -2000, and Elpida's fastest-to-date, 2.5GHz 'technology showpiece'. These varieties may calm down in the next twelve months, as the -2133 spec moves forward for affirmation. For most vendors, DDR3 will really take of with their nom 50nm DDR3 designs, which will be hugely productive (die/300mm wafer) and could be DRAM maker's ticket to profitability in 2010.https://community.cadence.com/cadence_blogs_8/b/ip/posts/unity_2700_s-new-cmox-memory-technology-appears-on-horizonFri, 19 Jun 2009 21:20:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266020Denali Blog/cadence_blogs_8/b/ip/posts/unity_2700_s-new-cmox-memory-technology-appears-on-horizon0Summary: Unity Semiconductor has come forth recently with a new candidate for Storage Class Memory technology, CMOx, which uses metal oxides as the data storage medium, and changing the presence of those oxides by application of an electric field. CMOx looks promising, cost-competitive with the roadmap potentials for existing silicon NVMs, high-enough performance, and scalable to under 20nm. But we are still two years from seeing something close to first production material, at densities and possible costs that will enable us to really check the early returns and expectations, against realities. For now, we can only stay tuned. The Company: Unity has 42 employees, with a wide range of semiconductor pedigrees from Inmos, Micron, Fairchild, Ramtron, Simtek, and AMD. It is headed by Darrell Rinerson, formerly an Executive at Micron Technology, who with two others founded the company in 2002. Darrell is the lead patent developer listed on most of the patent plaques lining the entry hall of the companies' Sunnyvale facility. Now seven years old in development, and with a total of $75M in three rounds of funding, Unity is confident enough in its technology and roadmap to start talking to manufacturing partners, as it concurrently moves product and technology development from 'proof of concept' to 'characterization' and something close to 'production-readiness' over the next two years. Should this technology pan out in a way close to what early analyses and tests have indicated is possible, at equivalent process nodes, CMOx can be expected to have 4x the density of NAND flash, 5x the write speed of NAND, and require little in the way of special processing flows. Compared to MLC NAND's 2F2 cell size, CMOx's is merely 0.5F2, and it has no transistor to limit extreme scaling. Though still two years away from production-readiness' CMOx memories are being positioned as something of 'The Mother of All Storage Class Memories' that are taking aim at sockets where conventional silicon cannot reach for price or performance reasons. Conceivably, CMOx could even replace HDDs, and expand markets into heretofore unidentified markets, applications and products. These are 'Great Expectations', to be sure, and a long road to travel between today's 64Mb test vehicle, now undergoing characterization in Unity's labs, and its 64Gb device, scheduled to be available in 1H11. Novel manufacturing process flow: With the Unity CMOx storage cell technology innovation, other important business and manufacturing decisions can change. For one, for the first several masking layers, Unity's wafers can effectively use a standard bulk CMOS process, at a back generation process node, for the FEOL. They can buy common 90nm processes wafers for their CMOx memory feedstock. These 'pre-uncommitted memory arrays' are then transferred to a more state-of-the-art BEOL, for the metal oxide and metal layers, and deposition and building of the actual storage features. 'Go to market'...how, exactly? Furthermore, in the midst of today's memory meltdown, Unity is very interested in its own go-to-market model, and intent on devising a method of taking its product to market without creating the overly-commoditized bloodbath we have seen for more than a year in DRAMs and NAND flash. For this, their 'plan of record' today is to join forces with an existing memory manufacturing partner, and have limited production sufficient to service that market that can use the superior performance of CMOx (at a price, to be sure). Of course, they will have to weigh carefully the option of reducing prices and broadening the market...but this decision will have to wait until the product itself is fully characterized and the existing and potential 'high value niches' better understood. Unity is convinced that broad licensing of CMOx would collapse the market into a food-fight, and leave everyone with nothing, as it has, periodically, for traditional DRAM and NAND flash licensing programs almost since the industry's inception. Licensing, adoption, production: evidence and options: To add some perspective to this problem, specifically that of the owner of a potentially valuable "Memory IP", it is worthwhile to see other ways of 'going to market'. These days, Pure IP Developers are denigrated in some quarters as being 'patent trolls', leaches and worse. They 'make' nothing, and are viewed as riding on the backs of those who do make products. Historically, IP developers made products that demonstrated the value of their IP, and got paid in product profits. Sometimes 'secret sauce' of proprietary but undisclosed and unpatented technolgies, remained out of view for years from competitors. But, especially among the industry's early founders, broad cross-licensing took place, and no one was denied access to any other technical developments in their field, though license and royalties flowed continuously. That started to change in the mid-1980s with a huge TI patent offensive against DRAM makers, and was turned on its head entirely with the founding of Rambus in 1990s, who was the first pure-play IP company in the industry. The conundrum is that however much the IP costs, the cost use it in a DRAM/memory/semiconductor product, and take it to market, is far greater, with today's $3B memory fabs and established channels to customers. A standalone IP developer has to find a manufacturing partner to bring his ideas to life in the marketplace, and to profitabliity. And, even if one has an allegedly superior capability, it is no guarantee of a big money stream, and there is never any guarantee that it is 'forever.'. Rambus DRAMs have demonstrated superior performance to standard DDR1-2-3 for more than a decade now, but have not enjoyed significant take-up in the market, and have thrust Rambus themselves into a never-ending sea of lawsuits...which pariah status Unity seeks to avoid. There are, of course, instances of sustained significant technical leadership and profitability from time to time in the semiconductor memory business, but, as all the players have the same basic tool box (or, sandbox, since its silicon), eventually Intel loses its HS 1K and 4K SRAM monopoly to Hitachi, Inmos and AMD; Samsung loses its 8M WRAM monopoly to DDR1 and wide IO, Standard G DRAMs and IBM loses its UHS SRAM sales leverage with customers Sun and HP, (sustained at $140/8M unit for years) to Samsung, and then GSI (though other factors were at work there, too.) System manufacturers are highly adept at working around costly components in their systems (see "History of RL DRAM"), as are the thousands of engineers working on new materials and methods at working around what appear to be an insurmountable patent position. Wang Labs x9 SIMM patents, earning them a cool $90M in the early '90s, became worthless with the onset of x32/x36 DIMMs. CDMA technology from Qualcomm is a non-memory example, with which they have generated a significant monopoly profit stream AND widespread adoption for many years, though not without a battle at every juncture. Rambus, Wang Labs and sometimes Qualcomm (and formerly, TI) have engendered some intense bad feelings in the industry by the way they 'exploited' their IP...which they feel is just getting paid for their technical contributions, "and if you don't like it...' Balancing what some would call 'IP greed' with market needs and 'ability to pay' is a hard act to manage, as we have seen many times. Broad licensing and cross licensing of IP has been the common industry practice since its earliest days; good for the consumer, but maybe not for the IP holders or other intermediaries, who cannot differentiate their products. Unity's manufacturing partnership plan is their way of limiting access to their technology, bringing production only to a level of a manageable market presence that shows good profitability in those applications that can appreciate CMOx unique capabilities. Once the show hits the road in 2011, we will see how well this works. (Saifun faced a similar quandary when they developed NROM technology...be an IP company or build a fab? This was discussed in an early DMR article.) . The Challenges Ahead: This looks like a promising technology worth watching. Only more time and more development and characterizations, and more critical evaluation in real-life applications, will tell us if CMOx is as good as it now looks. Many other technologies looked good for a while, but ran into cost, scalability, or performance challenges that could not be successfully overcome. MRAM was all the talk 3-4 years ago, but has given way to Phase Change Memories (PCMs) today as the most talked-about heir apparent to the extensible silicon roadmap on scaled NAND flash. With technical roots, and claims of Universal Memory Domination dating back at least to the early 1980s, Numonyx informs us in a press release from last December that they shipped the industry's first PCM memory for revenue in 4Q08. In addition, the Status Quo is not standing still; silicon NAND marches on, downward in cost, towards and beyond 30nm processing by the time the first CMOx 64Gb device is shipped in 2011. But if these claims come anywhere close to standing up under two more years of development and scrutiny, CMOx's domain will extend far beyond where we see silicon NVMs applied today...'cheaper and faster' is a hard to beat combination.https://community.cadence.com/cadence_blogs_8/b/ip/posts/taiwan-agonistes_3a00_-why-taiwan-should-demote-drams_2c00_-and-agressively-expand-its-foundry-dominance-insteadThu, 18 Jun 2009 15:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266019Denali Blog/cadence_blogs_8/b/ip/posts/taiwan-agonistes_3a00_-why-taiwan-should-demote-drams_2c00_-and-agressively-expand-its-foundry-dominance-instead0Taiwan Cannot Shake Attraction for DRAMs, Marches Down Same Path as Many Others Before Them Abstract: Taiwan wants to be a big player in DRAMs, which we believe is a losing proposition and a strategic mistake, not only for Taiwan but for all DRAM makers. They should embrace their strengths and domination of the worldwide foundry business, repurpose some of those DRAM fabs to make next generation logic, and expand their design and logic foundry franchises. They have much more to lose in foundry than they have to gain in DRAMs...in fact, DRAMs is a sinkhole for money and has been for more than a decade. In the current climate of industry consolidation, megafabs and hegemony for large markets, and the move to fablessness as a superior business model, it is not even an open question which path is better for Taiwan: Foundry logic trumps DRAMs, now and forever. Taiwan Wants to Make DRAMs After a very tough year-long DRAM market that began in the waning days of 2007, we are now well into the next phase...a more than nine-month agony emanating from Taiwan as is searches for DRAM relief in a variety of proposed consolidation arrangements among the island's DRAM makers. The "Powers That Be" in Taiwan, want to own their own DRAM IP and designs, to consolidate operations to reduce redundancies in design and development, to gain scale, and be large enough and tough enough to compete (mainly) with the Koreans. DRAM market leader Samsung and side-kick and rival Hynix, which own about 30% and 18% of the DRAM business, respectively, each makes more than ALL of Taiwan's DRAM makers combined: Powerchip, Nanya, ProMOS, Winbond, Rexchip and Inotera, plus or minus some allowance for Taiwan-based DRAM production which is owned by and built for non-Taiwanese DRAM makers (namely, Micron (JV Inotera) and Elpida (Powerchip and JV Rexchip), now that Qimonda is out of play). Taiwan has set for itself a formibable goal, from a weak position today, in a very tough and unforgiving market. DRAM makers, worldwide, lost about $20B in the 2001-03 aftermath of the dot.com bubble bursting, and have lost another $30B this cycle, from late 2007 though the middle of 2009. Taiwan's DRAM makers themselves have lost about $1B per quarter for the past six quarters (see table below), and hold huge amounts of debt, said to be in the vicinity of US$14B. When the 'profit' numbers for 2Q09 are tallied, another $1B will be gone forever. And, despite a long time coming in discussion, no firm plan seems to have emerged from the Taiwan Memory Corp., except to anoint Elpida with the title of "Taiwan's DRAM IP Savior", to plan to invest about US$300M for a 10% stake in Elpida to bolster its cash position, and to merge ProMOS into the larger TMC/Elpida entity. What this may mean for long-time Elpida partner Powerchip and its Rexchip JV, is not said, but likely they are automatic members of Club Elpida. Details in the public domain are scarce and it is truly a moving target, but clearly it is much more modest in scope than that which was proposed last fall, which had a scale that was rumored to be as high as US$6B in available funding. We will not know for sure, until there is a formal announcement, and maybe not even then, as huge uncertainties are sure to exist about the arrangement. What we do know is that it is now about nine months since conversations began, nothing has happened except Taiwan's DRAM makers have kept capacity on line, continued to make DRAMs, and lost another $3B. The Koreans are the dominant DRAM players today. With their unique corporate culture, with huge financial resources at their disposal and a gambler's penchant to go 'all in', alone, make them formidable. Add to this their incumbent's advantages, their market position, their product set, design skills, manufacturing capacity, technology and experience, and one can see that they are way ahead of Taiwan in many important measures of market success. If history is any guide, they would probably not be dislodged without a large and expensive fight. "Last Man Standing" takes on a whole new meaning when Koreans are in the market. Samsung's Greatness: Samsung makes twice as many DRAMs as all of Taiwan, owns most of their own DRAM technology (self-developed since Yong Park designed their 256K on Old Ironsides Drive in Santa Clara in 1984), has many DRAM designs in production, concurrently, down to the 40nm node as technology-proving vehicles. They are the driving force in JEDEC in both the NAND flash and DRAMs standards bodies, have a broad and profit-protective portfolio of LP DRAMs (50% share), Dense Server DIMMs (80% share?), and are the G DRAM market leader (>50% share). They are the original Market Creator and Market Leader for NAND flash, with a relatively stable 40% share, and a competitive #3 (belatedly) to Spansion and Numonyx in NOR flash, which remains a $5B business even in 2008. Samsung has led and dominated every memory market they participated in, for as long as they wanted. Furthermore, for Samsung, it would probably be a bad business decision to chase more than ~35-40% share of these huge, highly commoditized markets, susceptible to 'price dumping' by DRAM and NAND minions at home and abroad, and general production gluts (as in 'today'). Below-cost prices may hurt Powerchip a lot, but will impact Samsung, whose share is 10x larger, way more, in absolute if not relative terms. And, there has always been a "suicide bomber" in every DRAM downturn since 1979...they kill themselves, to be sure, but take as many innocent bystanders with them, who are too close to the explosion. The recent trend to "Pure Memory Players" exacerbates this potential: "We will not exit memories gracefully, if and since that is the only thing we have." Few memory makers have ever 'reinvented themselves'; most died of low prices and high losses. With high shares in all major memory markets, Samsung may not grow its memory share more from today, but will improve its memory profitability; for growth, they will have to find greener pastures and still-unfamiliar markets. Now, add in Hynix, which, by itself, is also about as large as all of Taiwan DRAM makers combined, and who is forever in the thrall of its bankers, anxious to see their investment pan out. Given their apparent willingness to throw good money after bad, and firm in the belief (or so it seems) that all that money invested can again turn green...if the competition gives up first. Unlike Taiwan, as well, Hynix has some good differentiated DRAMs, used in graphics and LP Memory applications...plus NAND flash. Hynix by itself, a distant second in all things memory to Samsung, is still out of reach for Taiwan. Taiwan, on the other hand, gets hand-me down processes from their partners, six months after development (IBM, Qimonda then Micron to Nanya, Qimonda then Hynix to ProMOS, Mitsubishi then Elpida to Powerchip, Qimonda and self-developed to Winbond), are centered in the sights of commodity DRAMs (having only a small fraction of differentiated DRAMs), and minimize their development costs by paying for technology transfers ahead of time. We believe that Taiwan, in focusing on strengthening its DRAM capabilities to fend off Korean DRAM dominance, is placing a bad bet, and the wrong bet. The world does not need another DRAM maker, it needs some substantial DRAM capacity taken off line, and restrained DRAM investment going forward. After two strong DRAM GB growth years, of 90% and 70% Y/Y in 2007 and 2008, respectively, 2009 promises to be a bust in terms of DRAM demand growth: pundits are calling it 20-30% Y/Y, the worst in a decade. Reductions in wafer starts are the only way to keep DRAM GB growth down that low for a year, as the steady and 'inertial' yield improvements, scheduled die shrinks and winnowing out back die versions naturally leading to more than 35-40% bit growth without adding a single wafer. Competitively, as well, Samsung is just too big, too entrenched, and too far ahead for Taiwan to compete with head on. Samsung Electronics is a huge $60B/year electronics business, with high market share and profitable positions in mobile phones and LCD panels, both of which can feed their chip business with whatever it takes to dominate the business. Rightly or wrongly, 'fairly' or 'unfairly', this is an important aspect of Korean corporate culture that must be reckoned with. Hynix' 'family and sponsors' will stop at nothing to stay afloat, as we saw in the 2001-03 dot.com bubble aftershock. If Taiwan wants to do battle with Samsung/Hynix/Korea, they should do it in foundries, logic and manufacturing logistics, and high-value add designs...where they have a head start and a huge advantage...vs. their 'fire and forget, huge commodity' mentality that permeates most memory makers' way of thinking and doing business. Sure, it will/would be a good story if Taiwan were to win and establish a sustainable (and profitable) DRAM position. The story would be great: "'The Comeback Kid', How Taiwan's DRAM Business Rose from the Ashes to Become a World Leader"...but what if they lose?...and why not apply themselves in an area where 'Victory' and 'Success' are far more likely, and aligned more with their current strengths and market trends? Samsung's Foundry Possibilities : Further and finally to this argument, Samsung, The Memory Guy, took 40nm Xilinx FPGA business away from UMC within the past six months, and was reported sniffing about in Taiwan's foundries for skilled employees to hire away. (see relevant footnote on Samsung DRAM offensive, ca. 1990, below). Although Samsung's System LSI business and 'other' have languished in ignominy for a decade, they show sparks of excellence, and know that they cannot overtake Intel (or grow their sales and profits much more) by relying only on memories. They have been a part of the IBM-led Common Technology Platform roadmap development consortium for many years; they have their own developing ASIC group, and take in foundry (in addition to Xilinx, noted above.) Their System LSI Group is running about $2B a year...a pittance by Samsung memory standards, but it would easily rank in the Top 20 in world chip sales by itself. Taiwan's Strengths, Taiwan' Exposure and Taiwan's Opportunity: Why "Taiwan" would want to challenge Samsung, or Korea, in DRAMs, is a question that has not been satisfactorily answered in the discussion so far. But a more important way to look at the problem is to ask, "What are Taiwan's strengths and what are its opportunities?" As we discussed in an earlier BLOG , Taiwan is more of an entrepreneurial culture, against the large Chaebols ('authoritarian' family-owned businesses) of Korea. It is more democratic in decision-making, and less prone to be run by diktat, as the Korean companies are. In Taiwan, there are fewer cozy government-banking-corporate tie-ins than there are in Korea, or than there are in Japan...which tie-ins have some competitive advantages when played against smaller, and more disassociated entities such as are found in Taiwan. Anyone can play in a market with the Koreans, but they play at their own peril, and usually with huge disadvantages in the power that can be asserted in a market, seemingly without regard to profit or damage potential. Though there is a fine line between 'thinking long term' and investing foolishly, somehow Korea manages to make it work. American driveways filled with Kias and Hyundai Sonatas attest to their perseverance and skill. To see Taiwan's strengths, one has to look no further than TSMC and UMC, the #1 and #2 pure-play foundries, with 50% and 15%, respectively, of the worldwide foundry business. TSMC had sales of more than US$10B in 2008; UMC had sales of more than US$3B in 2008. This is the Glory of Taiwan, and it is right in the path of perhaps the most important trend in the industry today, 'fablessness for finer line geometries'. It is these next-generation processes that are increasingly expensive to develop by oneself, and will drive more and more companies to lean on foundries as the industry moves forward to advanced process nodes, in the coming years. In the Industry's Consolidative Phase, Fablessness is Fabulous. As process development costs hockey stick up at 65nm and then 45nm and 32nm, as fab costs approach $3B per megafab, the drumbeat of fab-lite, fablessness and 'mere' design houses, resonates more loudly...and more profitably. While outsourcing of chip manufacturing is said to be in the vicinity of 20% of total chip sales in 2008, an increasing fraction of the industry's profits are to be found there...far from the idle fabs, rusting with depreciation as NAND and DRAM demand lulls, far from those huge capex budgets which strangle the higher-value-add design programs that form the value proposition in end systems into which they are sold, and shut off the profit stream of the whole of the silicon food chain. Fablessness also takes one far from the specialty processes that require constant attention to maintain competitiveness, against products and markets which are forever morphing, and/or wanting to morph into other markets, process requirements and functionalities. This is a huge exposure to a smaller producer...to develop a one- or two-generation process roadmap, then abandon it. This is the accelerating wave of the coming industry recovery, as high-value logic, ASIC and SoC implementations make Intelligent Designs more production-justifiable and more valuable to everyone in the silicon food chain, than 'mere' bulk bits' (sold at a loss, to be sure). With the current industry 'pause', painful as it is, Taiwan now some slack time to rethink its mission, to take stock of its available resources and skills and reset its industry direction. Through its leading foundries, it is uniquely positioned to become even more dominant in the next stage of industry evolution. Sinking more money into DRAMs is a fool's errand, that will bring good to no one. Footnote for Consideration: Samsung DRAM Offensive, ca. 1990 Samsung (as "TriStar"...its corporate/family logo) came on the DRAM scene in about 1983, after being the best Korean 'regional semiconductor player' for many years. With great fanfare, LG Goldstar, Hyundai (incarnate in the US as "Modern Electrosystems"), and Samsung all joined hands and jumped in to the world chip business. Not being shy, soon thereafter, Samsung declared its goal to become the #1 Chipmaker by the year 2000. Well, not quite, and not quite yet. But recall that this declaration was made when Intel was about #10 in the industry rankings, behind five Japanese (NEC, Hitachi, Mitsubishi, Fujitsu, Toshiba), TI and Motorola, and two Europeans (Philips, Siemens = Infineon). But, barely were the Korean's feet wet when the Tsunami of 1985 hit, and forced major retreats and reconsiderations by all three companies. On the surface, they retreated to more traditional corporate names: "TriStar" reverted back to "Samsung Semiconductor", and "Modern Electrosystems" became, nce more, "Hyundai Semiconductor". And, "Goldstar" stayed the same, at least for a while. They continued progressing on the technology front, but their big day only came when the Japanese Meltdown began in the early 1990s, leaving a huge market void...a DRAM void...to be filled with Korean DRAMs. Toshiba, Hitachi and NEC rode the end-of 1980's wave, but Samsung, with more money and more nerve, was in hot pursuit. When Toshiba showed signs of faltering in 1990, and whose 4Mb DRAM was not the market leader that their 1Mb had been, Samsung came into play with a vengeance. Throwing down the gauntlet, Samsung hired the Top Guns from right from under Toshiba America's (TAEC) nose: Keith McDonald, TAEC's Director of Sales, Mark Ellsberry, the TAEC VP of Memory Marketing, and Mike Crawley, the TAEC Director of Distribution and Sales Reps, all came over to work for Samsung. Within a year, these three had a huge impact on improving the Samsung image to its customers, brought immense experience to reshape Samsung's DRAM business into the market leader it is today. As soon as 1992 came in, Samsung had risen to the top of the (DRAM) heap, and became the market leader, never to be headed off. Where each generation of DRAM had had a different market leader from 4K to 4M, Samsung has led every generation since.https://community.cadence.com/cadence_blogs_8/b/ip/posts/the-great-escape_2c00_-part-ii_3a00_--how-these-companies-exited-the-dram-businessThu, 28 May 2009 14:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1266018Denali Blog/cadence_blogs_8/b/ip/posts/the-great-escape_2c00_-part-ii_3a00_--how-these-companies-exited-the-dram-business0Case Histories of Significant DRAM Market Withdrawals : This article continues our earlier discussion about the same topic from last week, entitled "...Part I." It includes highlights of the most significant departures from the DRAM business over the past two decades, and describes, in broad terms, the experience of these DRAM makers in the market, historically and the events that led to their departures. In some cases, details relevant to today's 'prospective DRAM players' are noted, as well as some of the 'behavioral attributes or special situations' that make these cases noteworthy. We have found, in preparing this discussion, that the internet provides a wealth of (undigested) fact and opinion about each of these companies; what is discussed below is believed to be accurate, but not comprehensive by any means. There is much to be gleaned from these "DRAM exit" histories that is useful for any company, but especially useful to companies that find themselves with large exposures in commodity products, in tumultuous times and in volatile markets. The exits are not always (or ever) clear, but there is quite a range of outcomes from situations that might outwardly look much the same...managing the exit can make a world of difference in the financial impact. What constitutes 'the business' or 'the assets' varied widely from case to case, and, as one can see, not all 'exits', in retrospect, were at all optimized given the options faced. Case History #1: UTC sells Mostek division to Thomson...to SGS Ates, which shuts it down: Mostek was founded in about 1968, out of TI, and located right down the road near Dallas. Like TI, they were a vital force in the early DRAM business during the 1970s, and made many valuable technical contributions (See subsequent Mostek IP licensing discussion, below). They were the original 'Standalone Memory' company, dominated by DRAMs, though they did have some small positions in SRAMs, Zero power SRAMs (which also spun out competitors like Benchmarq), EPROMs and Mask ROMs. They were also innovators in communications chips and were a Tier II player in MPUs. But forever and always, DRAMs was their glory. In 1979, in a fit of 'we MUST be in the semiconductor business' that swept over the industry, Mostek was bought by United Technology Corp. (UTC) for $345M, on the flimsiest of pretexts that their Carrier Air Conditioning equipment would eventually need to join the micro-electronics age. (Yes, I know, this sounded just as flaky then as it does today. But it was a good indication of UTC's naivete, which eventually factored into Mostek's demise.) The decision looked very smart, as Mostek rode the semiconductor and DRAM up-cycle in 1979-80, making the UTC buyers look like geniuses. The 1981-82 downturn caused some significant distress, financial and emotional, and showed cracks in UTC's commitment. The next cycle, running from 1982 into 1984, restored their confidence. But 1985's crash brought huge pains to Mostek. They had been a very significant DRAM play, having about 11% share in a DRAM market whose power and market share was far more widely dispersed that today's concentration. But continued losses and incredibly low DRAM prices brought pain and suffering and showed UTC that they had placed the wrong bet, and that 'the chip business, and DRAMs in particular' was a different kind of business than their other mainstream businesses, such as jet aircraft engines, elevators and air conditioners. In mid-1985, after a major upheaval within UTC, UTC's management decided to unload their Mostek Division, which they did at a bargain basement price of about $105M to the French electronics concern, Thomson CSF. This was a painful and decisive action; the sale took place at the bottom of the industry's worst-to-date cycle when asset prices were rock bottom. (Gaining compensation for "IP" licensing was not a recognized business activity...profit center...yet, until TI pioneered in 1986-87. But Thomson was decisive, UTC took their several hundred million dollars worth of lumps, and moved on. Mostek struggled under the management of Thomson for a while, weathering one layoff after another as the downturn dragged on for years. It was then combined with SGS-Ates in 1987, to make what is now ST Microelectronics, or STM. STM did two things: They shut down what remained of Mostek's position in DRAMs, but saved and used its Texas facility, along with small product lines like specialty SRAMs. More importantly, someone then said, "Let's take a look at Mostek's patent portfolio", which had been kept in some kind of locked drawer for a good while, and they found valuable DRAM and other memory IP, which netted STM about $450M over the course of the next few years, in license fees from other DRAM makers and downstream players. In several stages, from the onset of the 1985 DRAM crisis (which also took down Intel and Inmos, as well a convinced a number of small DRAM dabblers to "cease and desist."...ITT, National Semi, ATT, Fairchild and AMD...and more), UTC-Thomson-STM-Mostek went from 11% DRAM market share to 0%, putting about 10,000 workers out on the street, and costing a few hundred millions of dollars of losses to whoever owned the company at the time. Then STM made it all up with their "DRAM IP closet" discovery and licensing initiative. STM also bought Inmos in 1989, with its DRAM and SRAM designers (and Transputer MPU), and fabs in Colorado and UK, and remained competitive in SRAMs for a while longer. STM was the "Great Semiconductor Consolidator" of the era, and did so quite profitably. They liked memories, too, but only from a distance, and only as something that periodically depressed other company's share and asset prices, and gave ST huge benefits upon acquisition. Indeed, except for a modest position in Slow SRAMs and Mask ROMs in the early 1980's Video Game bubble, STM themselves stayed out of commodity memories almost entirely, until 1987, when they joined the EPROM fray, which product line they retained even through the morphing of EPROM business to NOR flash in the early 1990s, which they only a year ago, merged into Numonyx. Case History #2: Intel's Painful Exit, 1985: Along with TI, Mostek, and some Japanese efforts (Hitachi and NEC, mostly) Intel did more to develop the early DRAM marketplace during the 1970s than anyone. Always strong on technology and weak on low-cost manufacturing ("Intel could not ship an empty package for $5 if they had to."), they were frequently first to the new generation of DRAM, locked up key accounts, then retreated or coasted once the higher-volume, lower-cost manufacturing set moved in. During the cyclical upturn through 1984, Intel maintained about a 4-5% DRAM market share, but they were already on the retreat when the market turned south in the waning days of 1984. Here, again, Intel had (prematurely, it turned out) tried to muscle the DRAM market over to CMOS versions, as an innovative and leadership specialty part ("I have seen the future, and it is CMOS"), in place of the historic NMOS at the 64K to 256K densities; It was a right technology direction, but one generation too soon: The 256K mainstay DRAM remained NMOS, though Vitelic and NMB made scads of money selling 256Mx1 CMOS DRAMs as parity DRAMs for x9 DIMMs populated with CMOS 1Mb DRAMs in 1988-90. (This departure episode is very well covered in Intel Founder Andy Grove's book, "Only the Paranoid Survive". Soon, CMOS took over at the 1Mb generation with the rise of Toshiba, but without Intel. Case History #3: Inmos Swept up by STM, vanishes from DRAMs, 1987 Inmos was something of an Anglo-American Intel near-look-alike, and certainly carried forward their memory mantle. They had strong technical teams, good DRAM designers, top flight high-speed SRAMs, and their own 'Transputer', an 'MPU' that was way ahead of its time, but which failed to gain traction in the market. The memory design team was in Colorado Springs, where the memory products were centered; the MPUs were done in Bristol, Wales, UK, and had their own fab there. Inmos was beaten up badly in the 1985 downturn, and a new Government in England forced the sale of the Government stake as a part of its privatization program. Thorn-EMI (yes, the record company) picked up the Inmos option, and became a significant IP holder of Inmos DRAM and SRAM patents. But the patents were about all that survived the turmoil of the late 1980s, the fabs were abandoned, the staff cut loose, and eventually Inmos was sold to, and rolled up into ST Microelectronics in 1989. Case History #4: LG Shotgun Wedding, "Married" to Hyundai, 1999 Not unlike what we have seen in Taiwan in the past decade, and emphatically, today, "Everyone wants to make DRAMs", and when the Koreans entered the chip business in a big way in the early 1980s, they were no different. Samsung was the best-established from the start, and after licensing Micron's 64K DRAM, everything thereafter was home grown. Hyundai and Lucky-Goldstar (to be LG Semi) relied heavily on licensed designs and technologies until their own in-house capabilities were adequate. All three companies rose up in the rankings during the 1988-89 shortage and benefited from the Japanese Stall (Lost Decade) as the industry rolled into the 1990s, gaining huge market share in DRAMs in 1992-95. But the market fall-off, and the ensuing Asian Financial crisis in Korea in the late 1990s sent shudders throughout the Korean electronics business. Many industries were 'rationalized' at the point of a gun by bankers and government. Samsung gave up its nascent automobile business. A government-forced marriage combined LG Semi and Hyundai into a single DRAM company in 1999, renamed it "Hynix", and combined all technical assets and once-disparate process roadmaps to merge 18 months hence (about 2000/01) in a common technology view and product set. LG Semi disappeared; even LG's creditors had a hard time finding someone in the new Hynix organization to pay them. It was rough running for a while, and not without casualties. But the worst was yet to come: Barely settled down, Hynix emerged right on the cusp of the 2001-03 industry downcycle, which caused more than $25B in memory industry losses. The new Hynix was a mainstream DRAM maker, but also had some positions in SRAM and ROMs. But even by 2000, virtually all memory of LG Semi had vanished into the larger and more powerful Hyundai operation. "We are not alone!:" LG Semi was not the only DRAM casualty in the 1998 downdraft. With 1998 industry-wide DRAM sales of $14B generating a loss of $12B, TI's new management decided to pack it in, selling their operation to Micron. And Japan, after a very tough decade of receding influence and declining market share, began their prolonged march to the exit with the spin out and establishment of Elpida from NEC's and Hitachi's DRAM operations, both market leaders a decade earlier in the "K" densities, about which we'll have more to say below. Case history #5: TI sells DRAM operations to Micron, 1998: TI was one of the most important DRAM pioneers back in the 1970s, but like all US companies, steadily gave up ground to the Japanese, one DRAM generation after another, during the 1980s. The downturn of 1985 pressed them severely, and resulted in their 'Muscular IP Defense and Licensing Strategy', launched in 1986-87, and which netted them more than $2B is licensing fees and royalties over the next decade, as their seminal DRAM patents were licensed to all comers. But the 1998 DRAM market blitz, again driving huge TI losses, and a sudden change in TI's Top Management brought on by the sudden death of TI Icon and CEO, Jerry Junkins a year or so earlier, led to their 'Creative DRAM Escape'. Even today, this exit sets the standard for a comprehensive and non-lethal departure from a fierce and unforgiving market. This allowed TI to leave behind major risky market positions and cash requirements, and bring the New TI organization to life in other areas that had been neglected for years, an altogether too common situation in DRAM companies...feed the beast to starve the babies In 1998, TI sold its DRAM operation to Micron for cash and stock. This was the most successful exit, from a financial point-of-view, that the DRAM market has ever experienced. TI gave up its DRAM business, gave Micron a ten-year holiday on TI DRAM IP (just now expired in early 2009). TI unloaded its DRAM fabs in the US and Italy, its share of TECH JV in Singapore, and its DRAM JV with Kawasaki Steel (KTI) in Japan, plus an empty fab in the Dallas area. TI had just signed on Samsung and Toshiba for ten-year DRAM royalty bearing license deals in 1998, too, and though they gave up a substantial flow (~5% of sales) from Micron, it was much smaller an assured income loss than what they retained from other DRAM makers. Micron assumed the debt to the Italian government that dated back to the establishment of the Avezzano fab, and gave to TI a boatload of Micron stock (which was trading at about $20 at the time) in payment for TI's fab assets. TI then loaned Micron enough money to get a head start on moving the fabs to the Micron 0.21um process node. Micron made huge gains in share price and DRAM market share in the next two years, and easily paid back the debt. TI proceeded to liquidate the shares over the next few years, as well, at prices sometimes as high as $90+ (Micron's 2000 peak share price was $94.50...it's now selling in the $4.50-$5.00 range.) In doing this deal, TI kept a good cash flow from the extensive patent portfolio, actually had a capital gain on the sale of about $100M, cleared huge assets and liabilities off their balance sheet (turning them into cash and stock), washed their hands of a painful 25-year voyage in DRAMs...and caught the 'mobile phone wave' with their newly-invigorated DSP and analog circuits operations. TI never would have risen to be the #3 or #4 chipmaker they were in 2008, with DRAMs in their product portfolio. Indeed, they would more likely have followed Mostek and Inmos into the grave or consolidation with a healthy and rich suitor. Case History #6: Hitachi-NEC merge to make Elpida, 1999: After watching their DRAM market share peak in the late 1980s at about 70%+, Japanese DRAM makers then watched their prospects steadily wither away in the aftermath of their own stock bubble's bursting. After more than a decade of 'can't do anything wrong' and steady gains across most market segments, inside and outside chips and electronics, the Nikkei Stock Index dropped from more than 40,000 in 1989, to under 10,000 in the worldwide recession of 1990-91. Market share, investment and Japanese confidence followed in like retreats. During the DRAM run-up in 1992-95, which it reached a still-record $40B in DRAMs, Japan's DRAM makers, with huge problems at home, excessive caution and facing the SIA's Trade Warriors at every step, gave up ground to Korea. When 1998 brought the then-worst-ever DRAM market and its losses about matching total sales, NEC and Hitachi decided to spin out and combine their respective DRAM units, which they did by the end of 1999. The parents, properly, gave the kids a head start: DRAM technology rights, some legacy DRAM fabs and designs and capital to get running. Against a stiff headwind in 2001-2, they finally aligned their products in a uniform process, and launched their new E-300 fab. NEC and Hitachi held majority stakes in the new Elpida venture, but gradually liquidated large portions over time. Also in 2003, Mitsubishi, which had remained as a standalone Japanese DRAM maker, joined Elpida. Recently, Elpida has been anointed the IP 'Provider of Choice' for Taiwan's Memory Company (TMC) initiative, but the fact that the venture remains stalled, and the company remains cash constrained, leaves Elpida in a still-precarious position. As Japan's sole DRAM maker today, they command some special attention with Japanese bankers and within the industry; how deep the pockets are of those 'interested parties' remains to be seen. Case History #7, IBM Micro exits DRAMs, 1999: Despite having 'one of their boys'...Robert Dennard...invent the DRAM in 1968, from the very start at IBM there was always a 'business vs. technology' conflict about being in the DRAM business. IBM made DRAMs from the earliest DRAM days for their internal systems, which parts were not wholly compatible with Industry Standard (I.S.) DRAMs. This gave IBM systems some performance advantages, they thought, but made them price non-competitive in times when oversupply in the larger merchant market drove DRAM prices below manufacturing costs. Internal price benchmarking made the Natives look bad against 64Ks for 50 cents in 1985, and $6-8 1Mb in 1990-91. IBM's coming out into the merchant market in 1993 leveled the playing field, and forced I.S. DRAM product designs that could be used both inside IBM, and sold to the merchant market. Some systems inside IBM still used proprietary DRAMs, custom specs or unique packages. But the Microelectronics Division now had the larger merchant market to sell to, so scale was no longer limited by internal DRAM demand. This disagreement dipped below the surface during the initial DRAM upturn 1993-5, when even IBM's DRAM Gross Margins rose close to 70% in the waning days of 1995. But there were still currents of "Strategic Confusion of Purpose" that were happening concurrently all along. DRAMs were starved for prime development resources, they sold off a DRAM fab in Germany in 1994, they were shackled by confused cost accounting methodologies that obscured DRAMs' true profit contribution, and DRAMs were frequently used to fill fabs, and make up for the ASIC businesses' difficulty in launching its own Merchant ASIC business. The mainstay of the DRAM operation was a Triad formed of IBM, Siemens and Toshiba in 1993, which used the trench cell to build a common 16M DRAM platform that reached production in about 1994. IBM played the lead, and engineers from all three companies led the charge at IBM's Essex Junction plant, and at the R& D and Development line in Fishkill NY. From this, each company also used its own production facilities to make and sell DRAMs to the merchant market. IBM and Siemens shared a DRAM manufacturing operation in France, and in spring of 1996, a JV production facility was announced between IBM and Toshiba at Manassas VA. The timing could not have been worse for this venture, Dominion Semiconductor, which started DRAM production in about the middle of 1997. The DRAM business was good until the last days of 1995, but prices dropped fast in early 1996. As the internal strategic battle went on within IBM, both the French JV and Old Dominion continued to cautiously ramp DRAMs. Neither was sufficient scale to get down the cost curve, IBM's reluctance to commit to DRAMs hindered their ability to shrink designs, build market share, or be anything but a 'Summer DRAM Maker'. Their share, which was about 7% in 1993-94, drifted steadily downward towards 2-3% as they equivocated. All systems were paused in 1998, and in 3Q99, they finally pulled the plug, wrote-off assets and withdrew from their Siemens and Toshiba JVs; France was shuttered and converted to logic, and the ownership of Dominion was transferred to Toshiba, which continued to make DRAMs. IBM's 1998 licensing of DRAM technology to Nanya was transferred to Siemens, which relationship continued until Qimonda's recent filing for Bankruptcy protection. Overall, IBM took charges of more than $1.2B at the time, which, when added to operating losses for 1996-99, totaled more than $2.5B from the end of 1995. Case history #8: Toshiba sells DRAM operation to Micron, 2002: Toshiba was the DRAM market leader at the 1Mb generation in the late 1980s/early 1990s. Like most Japanese DRAM makers, they had mixed-to-down results during the 1990s, hampered by cash shortages and a 'failure of confidence' in the early days of the "Lost Decade". In 1993, after falling somewhat behind the pack (notably Samsung), they formed a DRAM development venture, Triad, with IBM and Siemens with most development centered at IBM's facilities in the US. In 1996, they formed Dominion Semiconductor, a DRAM production JV with IBM located at an IBM site in Manassas VA; this was their only chip production facility outside Japan since an early 1980s Silicon Valley acquisition. They continued to run DRAMs in their Japanese fabs and at Dominion through the 2000 upturn, and the business was good. Process technology was advanced from 0.25um to 0.21um and touched 0.18um in production in all facilities. But their extremely strong position in the emergent NAND flash market, and their persistent difficulty keeping their Dominion fab current and up to scale, led them to seek out Micron as a buyer in late 2001 (downturn). This deal was closed in early 2002; the NAND flash wafers and production, which has begun to displace DRAMs in Dominion, were moved to Flash Alliance fabs (Toshiba and SanDisk JV) in Japan. DRAMs, which used the IBM-Toshiba trench DRAM, were at first continued at Dominion for about a year, but then halted and the facility was idled while it was retooled for 300mm wafers, the Micron process flow, and a more advanced technology node. Toshiba's production of NAND continued its ramp in Japan, profitably, and Toshiba escaped relatively free after some modest write downs and one-time charges. Micron, on the other hand, spent some considerable time and money getting the Dominion fab into production in their own technology. Of Micron's acquisitions of TI, Qimonda-Inotera and Toshiba DRAM operations, this was likely the least successful, in terms of high cost and difficulty aligning the process flow with their own product. Toshiba, once rid of a 'foreign fab' and their DRAM business, went on, with their technology and fab partner SanDisk, to NAND greatness. Of course, once Hynix and IMFT joined the NAND hunt and ramped up production, along with Toshiba's own overly ambitious investment plans, glutted the NAND market in 2008 and made it...as bad as DRAMs!.