Denali Blogs

Intel’s Atom-based Tunnel Creek SOC with integrated PCIe interface opens new era for embedded developers

Denali Blog — Mon, 19 Apr 2010 23:52:41 GMT

One of the most ignored Intel announcements of recent memory must be Doug Davis’ early disclosure at IDF (China) on April 14 (see the hour-long keynote video here) of the company’s new Atom-based Tunnel Creek, an SOC specifically designed for embedded applications. Intel’s Atom processor, a relatively low-powered implementation of the “Intel Architecture,” has been taking the low-end notebook and netbook world by storm. Atom processors also work well and have been rapidly adopted in the embedded world when the embedded product’s block-diagram resembles a PC. However, smaller embedded systems can’t adopt the multichip, chipset-style design of PCs. Many smaller embedded systems require even fewer chips for cost-effective implementation.

Enter Intel’s Tunnel Creek, which sports four x1 lanes of PCIe in addition to the Atom processor core; memory, audio, and video controllers; and an LPC block. The simple addition of a flexible PCIe interface means that embedded designers can gluelessly add a variety of different chips to the Tunnel Creek SOC to create embedded designs with minimal BOMs.

Figure 1: Intel Tunnel Creek block diagram
What can you connect to a PCIe interface that would be useful in an embedded design? Here are just a few ideas that immediately come to mind:

An ASSP with a PCIe interface. In the same talk where he disclosed Tunnel Creek, Davis also mentioned that Intel will be developing more than one application-specific I/O hub for specific use with Tunnel Creek. In addition, there are many other likely candidates already on the market such as advanced video/graphics controllers from companies such as nVidia and fast Ethernet controllers from companies such as Realtek.
An FPGA. Both Xilinx and Altera offer FPGAs with integral PCIe interfaces. Imagine the ability to gluelessly graft an FPGA directly to an Intel Atom-based SOC. Tunnel Creek should be able to do that.
An SSD. You can get PCIe-based SSDs that provide more performance than SATA- or SAS-interfaced SSDs because the PCIe interface is more efficient for high-speed I/O than disk-centric interface protocols. Why add an unneeded disk controller to the mix?
Your own ASIC. Intel and TSMC announced earlier that the Atom core would be available to select customers as an ASIC/SOC core. Perhaps you don’t have the production volumes needed to qualify as a select customer for that program but you’d still like to avail yourself of Intel’s processor architecture because of the immense pool of existing software, the many available operating systems for the x86 architecture, and the broad development tool support. Tunnel Creek gives you a way of doing so using a standard processor-based SOC that will likely be produced in fairly high volumes. For lower production volumes, a 2-chip embedded design may well be the most economical.

If these possibilities excite your inner design muse, then start bothering Intel to see when you can get your hands on some Tunnel Creek samples.

Apple iPad: no LPDDR2?

Denali Blog — Fri, 09 Apr 2010 21:57:37 GMT

Guest Blogger: Marc Greenberg, Technical Marketing Director

By now it seems that anyone with an engineering degree has probably read 2 or 3 teardown reports on Apple’s iPad. Few that I have seen so far talk about the DRAM memory subsystem -- and that could be because the DRAM was hidden on top of Apple’s A4 processor.

Chipworks.com has torn down Apple’s A4 processor package and reports that the DRAM subsystem consists of two Samsung LPDDR1 1Gbit memories in package-on-package (PoP) configuration. The PoP allows for the DRAM to sit on top of the application processor and the whole thing has been marked on top with Apple’s A4 logo. There’s a great cross-sectional photo of the PoP system showing the A4 processor underneath and the two DRAM dice on top.

It’s no secret that the iPad has a substantial amount of MLC NAND flash, but the interesting thing for me was Apple’s continued reliance on first generation Low-Power DDR1 (LPDDR1) technology instead of latest-generation LPDDR2. LPDDR1 technology was introduced in 2003 making this one of the oldest technology standards in use in the iPad.

Several applications processors already support LPDDR2:
- ST-Ericsson U8500
- Freescale i.MX508
- TI OMAP4
- Broadcom BCM2763 - Samsung S5PC100
Plus a bunch of others that we at Denali know about but which are not public yet.

The specific DRAM in use in the iPad appears to be a Samsung K4X1G323PE according to this die photo. According to the part decoder, we can see this is a 1Gbit X32 4 bank LPDDR1 device with 1.8v IOs. Samsung’s Mobile DDR (LPDDR1) product list indicates that the maximum speed of operation of this die is 200MHz (DDR400).

Even though LPDDR1 was introduced in 2003, the 1Gbit LPDDR1 parts are a relatively recent introduction, and the mask date code on the die photo is September 2008. Relying on 1.8V signaling, LPDDR1 has higher operating voltage than DDR3 (1.5v), DDR2L (1.5V), DDR3U (1.2xV) and LPDDR2 (1.2v). LPDDR1 also has the lowest maximum operating frequency of any of the DDR DRAM technologies commonly in use today (DDR2, DDR3, and LPDDR2). LPDDR1 does have lower standby power than any of the DDRx technologies however, surpassed only by LPDDR2.

LPDDR1 definitely has its place in applications that don’t need all the LPDDR2 bandwidth and which also need less memory capacity and low standby power. But for a mobile computing-intensive device like the iPad, LPDDR2 would have been an obvious choice. Among the benefits of LPDDR2 are that LPDDR2 offers lower voltage operation (and thus less power), more flexible power management modes, fewer package pins (less costly packages), and higher frequency of operation (more bandwidth) in comparison to LPDDR1. LPDDR2 is specified for up to 533MHz/DDR1066 operation and new designs are commonly specifying up to double the LPDDR1 frequency.

LPDDR2 also has the unique property of supporting Non-Volatile Memory (NVM) such as Phase-Change Memory (PCM) on the same bus as LPDDR2 DRAM. This LPDDR2-NVM offers similar performance to DRAM but with less operating power and near-zero standby power and also offers faster system boot and resume from suspend times.

The question is, why did Apple not choose the latest generation LPDDR2 parts for the iPad? It could be a couple of reasons. They may not have been able to source 600,000 LPDDR2 dice in time for the launch. The LPDDR2 parts may be at too much of a cost premium. It could have been a hang-over from the iPhone. Or there could be a marketing answer: Apple may have designed the A4 to work with LPDDR1 or LPDDR2 technology. That would allow a later version of the iPad to use LPDDR2 to provide longer battery life and more performance -- enough for multitasking, perhaps?

Whatever the case may be, LPDDR2 is an available option on high-end application processors and is ready for all kinds of new designs. Denali has offered LPDDR2 memory models since the early part of 2008 and was making customer deliveries of Denali’s Databahn LPDDR2 memory controllers at the end of 2008. Today, Denali offers high-performance and low-power memory controllers and PHYs for any combination of DDR1, DDR2, DDR2L, DDR3, DDR3L, DDR3U, LPDDR1, LPDDR2-DRAM or LPDDR2-NVM.

Find out all the latest information on DRAM technology at Memcon, July 28th in Silicon Valley: www.memcon.com

Thanks,

Marc

DDR3/DDR2 price crossover reached

Denali Blog — Tue, 06 Apr 2010 17:19:53 GMT

Guest Blogger: Marc Greenberg, Director, Technical Marketing

The day is finally here - DRAMExchange.com quoted that the session average price of 1Gbit DDR3-800 parts on April 2nd was $3.03 while 1Gbit DDR2-800 was $3.04.

Only DDR2 memory manufacturers will be celebrating... you should realize that this point has been reached because of rising prices on DDR2 to meet the DDR3 prices, not because of falling DDR3 prices. DDR3 has been holding relatively steady in the $2.50 to $3.00 per gigabit range over the last year, while DDR2 prices for 1Gbit have risen from around $1.00 a year ago to over $3.00 today.

Denali were originally projecting that the DDR2/DDR3 price crossover would happen sometime in 2009 and here it is in the second quarter of 2010. We have a pesky recession to blame for the delay - in the depths of the recession, some 512MBit DDR2 parts were sold for $0.35 and the DDR2 price remained depressed for longer than predicted. Thanks to the recovery, people are buying PCs again, and many are still using DDR2.

What does this mean for you?

Well, I should start by saying that this is the *first* price crossover. Prices tend to cross over 2-3 times during the lifetime of the product. As new DDR3 capacity comes on-line, DDR3 prices may drop. As new DDR3 products come on-line, prices may rise. As old DDR2 capacity is turned off, DDR2 prices may rise. As old DDR2 products are retired, DDR2 prices may drop.

For the near-term, if you are designing a product where the performance of DDR2 is sufficient, you should plan on supporting both DDR2 and DDR3 in your product to allow you to take advantage of whichever part is cheapest at the time of manufacture.

What’s on the Horizon for NAND and DRAM?

Denali Blog — Tue, 02 Feb 2010 23:15:55 GMT

Young Choi, Guest Blog for Denali Software

January is a time where lots of planning and forecast are made, with high hopes usually. Semiconductor memory industry, after several years of prolonged downturn, finally started to see some glimpses of recovery lately. Prices are improving, product migrations happening, new process node migration providing production efficiency and hopefully more profitability to the manufacturers.

The information and data that UBM TechInsights has been collecting on commodity DRAM and NAND Flash products clearly show how semiconductor memory industry has been improving their efficiency measured in terms of Mbit per mm2.

For commodity DRAMs, the latest 40 nm class DRAM products show their efficiency of 34Mbit per mm2. When compared to the previous 50 nm class DRAM, 40 nm class shows over 40% improvement. When cost per bit matters the most, 40 nm class DRAM will clearly provide the much needed cost advantage to those manufacturers who have this technology. For those who don’t, they need to find a better way of securing their profitability. When innovation and investment are the name of the game, the gap between the haves and have-nots are obvious, and hence, there is constant movement of joint ventures and merger and acquisitions to create economies of scale. Recent movement of Micron and Elpida, with their respective partner companies in Taiwan, is a clear sign of this. Perhaps later in 2010, we might be able to see the first 4F2 cell based commodity DRAM products. While some DRAM manufactures still have products with 8F2 cell, new 4F2 cell designs combined with smaller geometry would deepen the gap between DRAM makers.

For NAND industry, the trends have been staggering. Introduction of 30 nm class products certainly has contributed to the higher efficiency of commodity NAND Flash products for sure. For NAND, luckily three-bit per cell (X3, TLC or 3-bit MLC) and four-bit per cell (X4, or 4-bit MLC) also helped push the envelope further beyond the lithographical limit in terms of bit density (Mbit per mm2). While all of the major NAND manufacturers (Samsung, Toshiba/SanDisk, Intel/Micron and Hynix) have announced their three-bit per cell and/or four-bit per cell NAND products, there are still some concerns about their reliability and performance. This is reminiscent of the times when MLC (two bit per cell) based NAND products were first introduced. The industry and the market had managed the reliability and performance issues successfully and MLC had become the mainstream NAND technology in many data applications. One can expect that the same would happen to three- and four-bit per cell NAND technology, eventually.

While the past history or performance of the two key commodity memory technologies, DRAM and NAND, has been impressive and even remarkable, the future has a lot of uncertainties. To help us understand what to expect in the future, the presentation which was given by Kinam Kim at Samsung can be a good reference. This was also published on the Semiconductor International website. A patterning limit chart is shown below:

Of course, patterning limit is not the only obstacle to achieve more efficient DRAM and NAND products. There are many other technical challenges for DRAM cell, storage capacitance, isolation, leakage, reliability, floating gate vs. charge trapped flash, double patterning, immersion lithography, so on and so forth. What about new technologies to make DRAM storage cell a thing of past? What about 3D memory?

It appears as though the semiconductor memory industry is following the curves shown above (fairly closely so far). The 40 nm class DRAM products and 30 nm class NAND Flash products that were announced in 2009 are the proof. The real test within the industry will come in 2010. Will we see 30 nm class DRAM in 2010? How about 20 nm class NAND Flash? It remains to be seen but some early signs seem pretty promising. It’s January, a month of high hopes and expectation and a lot of planning for another year. Let’s hope for the best of the semiconductor memory industry in 2010.

PS: 2010 is a New Year for us as a company, too. Semiconductor Insights, which has been a leader in providing technical intelligence and intellectual property professional services to the semiconductor industry is now called “UBM TechInsights”.

For various DRAM and NAND Flash analysis reports (process analysis, circuit analysis and waveform analysis/functional testing) on the latest 40 nm class 1Gbit DDR3 SDRAM, 30 nm class 32Gbit MLC NAND Flash, 30 nm class 32Gbit Three-bit per cell NAND Flash, 40 nm class 32Gbit Three bit per cell NAND Flash, please visit UBM TechInsights’s Open Market Reports page.

The Evolving Enterprise SSD: Gartner’s Forecasts

Denali Blog — Tue, 26 Jan 2010 02:15:17 GMT

By Steve Leibson for Denali Software

The appearance of SSDs into the storage arena is rapidly altering the way large-scale, enterprise-class storage systems are built. Gartner Principal Analyst Sergis Mushell discussed some of these changes at the recent Storage Visions 2010 conference held in LasVegas. Mushell focused on how the introduction of SSDs into the enterprise-class storage device market was reshaping foundation concepts in terms of form factors and interfaces. Mushell started by discussing form factors and projected the graph in Figure 1, which forecasts unit sales of enterprise-class SSDs by form factor:

Figure 1: SSD distribution by form factor (Gartner)

The first thing to note about this graph is the unit-growth forecast for enterprise-class SSDs shown at the top of Figure 1, from 281,000 units in 2008 to 5.3M units in 2013. That’s a 20x increase over a 5-year period and that’s healthy growth is attracting new and existing storage vendors into the enterprise-class SSD market.

Next, notice the relatively rapid decline in the use of 3.5-inch, enterprise-class SSDs. Although these drives constituted the bulk of the enterprise SSD market in 2008, Mushell's chart predicts that 3.5-inch SSDs will become a mere sliver of the market in 2013. At the same time, shipments of 2.5-inch, enterprise-class SSDs appear to stabilize at approximately half of the market. The big percentage growth forecast is for board-mounted SSDs either as PCIe expansion cards or as plug-in DIMMs--not really drives at all.

These forecasts are consistent with three industry trends. First, the unrelenting application of Moore’s Law doubles NAND Flash capacity about every 18 months, so volumetric requirements for the same storage capacity shrink accordingly. Hence the decline of the relatively large 3.5-inch form factor. (Old-timers in the storage industry might crack a smile at the idea that 3.5-inch drives are “large.”)

Second, there’s no particularly good reason why SSDs should be packaged in form factors that are based on the requirements of mechanical rotating storage (hard disk drives, HDDs). Existing HDD form factors are artifacts of platter-size choices and the actual dimensions represent a logical physical progression from 8-inch and 5.25-inch HDDs down to 3.5- and 2.5-inch drives over several decades. Server designers often find these existing HDD form factors to be troublesome. SSDs can assume any convenient or odd form factor because they’re entirely electronic and made of ICs. They initially adopted HDD form factors to allow easy, drop-in replacement of existing HDDs but the use of HDD interfaces is really just another anachronism, as the rapid forecast growth of PCIe-based and DIMM-based SSDs suggests.

Which leads to the third trend and the next graph Mushell displayed, shown in Figure 2:

Figure 2: SSD distribution by interface (Gartner)

This graph forecasts market share for the enterprise-class SSD market by interface type. Note the dominance of Fibre Channel SSDs in 2008, which is consistent with a disk-replacement strategy. Fibre Channel has dominated enterprise-class storage thanks to its high transfer rates but that dominance is ending for both HDDs and SSDs as faster SAS and SATA interface standards appear. Figure 2 forecasts a rapid decline in shipments for SSDs with Fibre Channel interfaces, which predicts that the percentage of enterprise-class SSDs shipped with Fibre Channel interfaces will plummet from nearly 70% of all enterprise-class SSD shipments in 2008 to virtually nothing in 2013. According to this forecast, Fibre Channel’s reign washes away in three waves. The SATA (serial ATA) interface represents the first big challenger to Fibre Channel’s dominance, followed by SAS (serial attached SCSI), and finally by PCIe, which isn’t an HDD interface at all.

SAS and SATA HDD interfaces have been pressed into duty as SSD interfaces for at least two logical reasons. First, these interfaces have become dominant because of their widespread use for all HDD classes, not just the enterprise class, which means that the storage industry has developed a tremendous infrastructure to support these two HDD interfaces. That infrastructure includes everything from driver, OS, and database software; to drive testers; to cables, connectors, and built-in chipset support. In any market, broad infrastructure support and the correspondingly reduced implementation and support costs constitute powerful compatibility incentives that drive vendors cannot ignore.

Second, as HDD manufacturers enter the SSD fray either by developing their own SSD architectures and designs or by buying SSD vendors outright, the use of HDD interfaces on SSDs presents the appearance of a unified product line to customers. Left alone to their own world of storage, existing drive vendors with established HDD product lines have no strong need or wish to differentiate SSDs based on interface type and prefer to offer either type of storage to their customers as plug-compatible alternatives. Established drive vendors’ predisposition to support and maintain legacy HDD interfaces opens the door wide for new SSD vendors that do not have legacy HDD interfaces to support.

As discussed in a previous blog entry, it’s possible to develop SSD architectures that easily outperform HDD interfaces simply by increasing the number of parallel NAND Flash channels in use. It’s not possible to perform the same trick with HDDs. To get higher data rates from HDDs, manufacturers can:

Spin the disks faster--but at 15,000 RPM, enterprise-class HDD platters are already under severe mechanical stress.
Increase the number of read/write heads that can be active simultaneously--which constitutes a radical, substantial, and costly architectural and electronic change to HDD design.
Add a second servo actuator with another set of read/write heads and another set of read/write electronics--which is completely out of the question from an economic perspective.

Consequently, some SSD vendors are beginning to use faster interface standards that are not constrained by disk-centric assumptions that have been baked into standard HDD interfaces including even the latest versions of SAS and SATA. PCIe is a good example of such an unconstrained interface. A 16-lane, Generation 2 PCIe interface provides 8 Gbytes/sec of throughput (much more than SAS or SATA) and a 16-lane, Generation 3 PCIe interface provides 16 Gbytes/sec of throughput. These substantial throughput rates underlie Gartner’s forecast for the eventual decline of all HDD form factors and HDD interfaces in SSD applications.

Related Information:

SSD Interfaces and Performance Effects

Denali Blog — Tue, 26 Jan 2010 02:13:05 GMT

By Steve Leibson for Denali Software

IDC’s Research Director John Rydning and Micron’s Director of SSD Marketing Justin Sykes tackled the merging abilities of fast enterprise-class SSDs and evolving disk interface standards, particularly SATA 6G (also called SATA 6.0) and USB 3.0, while speaking on a panel about the technology of storage during the Storage Visions 2010 conference held early this year in Las Vegas. Rydning spoke first and he compared and contrasted two new external disk-interface standards, namely USB 3.0 and eSATA 6.0. These standard disk interfaces improve on their predecessors. USB 3.0 maximum data rates are 3.2 to 4.8 Gbps versus USB 2.0’s 480 Mbps--a 6.7x to 10x boost in theoretical I/O performance. SATA 6.0 and eSATA 6.0 essentially double the theoretical maximum data rate of SATA 3.0 and eSATA 3.0 from 3 Gbps to 6 GBps. Consequently the new SATA 6.0 and eSATA 6.0 interfaces are theoretically faster than the new USB 3.0 interface just as SATA 3.0 and eSATA 3.0 are faster than USB 2.0.

The SATA and USB standards seem to be in lock step with respect to adoption rates according to Rydning. He showed comparison graphs that forecast increasing adoption rates for both SATA/eSATA 6.0 and USB 3.0, with some minor amount of adoption in 2010 and about 50% market penetration for each interface by the year 2012.

To aid this transition, laptop makers have started to build eSATA interface ports into laptops. This is not a particularly difficult feat because most motherboard chipsets include several SATA ports so implementing an eSATA port for such a machine is a matter of adding an eSATA connector to the laptop motherboard. For desktop and enterprise-class server systems, adding an eSATA port requires little more than a SATA extension cable that connects the motherboard SATA connector to an eSATA connector mounted on a metal expansion-card bracket or a case bulkhead because SATA ports are plentiful on most desktop and server motherboards. Rydning also pointed out that officially, eSATA connectors supply no power to the external SATA drive but connector manufacturers have developed an “unofficial” hybrid eSATA/USB 2.0 connector that allows a properly designed cable to tap into the co-located USB port’s 5V power while simultaneously coupling the eSATA disk-interface signals to the external drive.

Sykes’ panel presentation corroborated Rydning’s and provided some important test data to reinforce some of Rydning’s points and to make new ones. First, Sykes presented a historical chart showing the uneven throughput progress for SCSI and ATA disk interfaces as they evolved into the SAS (serial attached SCSI) and SATA (serial ATA) interfaces.

SCSI/ATA/SAS/SATA disk interface data rates over time (Micron Technology)

The graph shows that the SCSI disk interface led in throughput until both SAS and SATA interface standards hit 3 Gbps around 2005. With the development of a 6 Gbps standard in 2008, the SAS interface pulled ahead of the SATA interface and will remain in the lead even with the development of the new SATA 6.0 specification.

Sykes then showed a different sort of performance graph for an existing MLC (multi-level cell) SSD using SATA 3.0 and SATA 6.0 interfaces:

MLC SSD performance with SATA 3.0 and SATA 6.0 interfaces

The graph shows that sequential reads for this particular SSD benefit greatly from the faster interface although the read speed does not double with a doubling of the interface transfer rate. This result indicates that the SATA 3.0 interface definitely limits this SSD’s read performance. Although the SSD’s random read performance benefits some from the faster disk interface, the SSD’s sequential and random write performance essentially gains nothing from SATA 6.0.

These figures could lead you to the wrong conclusion, so take care in your interpretation. What the above figures do show is that the drive being tested was designed and optimized for the SATA 3.0 interface. In other words, the number of NAND Flash channels implemented in the tested drive is sufficient to support the SATA 3.0 data rate. Slapping a faster interface on this existing SSD architecture doesn’t produce a substantally faster SSD. To fully exploit the faster performance abilities of the SATA 6.0 interface, SSDs need more internal NAND Flash channels to boost internal read/write parallelism. That’s what Sykes’ next graph depicted:

Boosting NAND Flash channels increases SSD performance to SATA 6.0 rates
(Micron Technology)

Increasing the number of NAND Flash channels implemented in an SSD substantially increases the SSD’s read and write speeds (using either multi-level-cell or single-level-cell NAND Flash devices). In fact, the theoretical performance of SSDs that support 16 or 32 active NAND Flash channels greatly exceeds the bandwidth of 6-Gbps disk-interface standards, which means that the SAS and SATA disk-interface standards will need to evolve even further to keep pace with future SSD developments.

SSD and HDD Economic Forecast: Analyst Jim Handy Speaks Out

Denali Blog — Tue, 26 Jan 2010 02:11:26 GMT

By Steve Leibson for Denali Software

If you’re waiting for solid-state drives (SSDs) to overtake hard-disk drives (HDDs) as the storage device of choice in computers, servers, and consumer devices then Objective Analysis’ Jim Handy has a message for you: It’s not happening any time soon. Handy’s been following storage trends for many years. He’s tracked the pricing trends of HDDs for a while and SSDs for their short but dynamic life. Based on his presentation at the recent Storage Visions 2010 conference in Las Vegas, here’s what Handy forecasts:

Courtesy of Objective Analysis (www.objective-analysis.com)

The cost/Gbyte for HDDs is roughly 20x lower than for SSDs and Handy expects that relationship to be stable for the next 20 years. Sure, the cost/Gbyte will decrease for both types of storage device, but HDDs will remain the low-cost leader for high-capacity storage.

These predictions are built on some “basic truths”:

HDD capacity doubles every year or two
The minimum price for an HDD seems to have bottomed out at $50
NAND Flash device capacity also doubles every year or two
When NAND Flash stops scaling (see the previous Denali Memory Report blog post “The End of NAND Flash as we Know It: Micron’s Dean Klein and Samsung’s Tony Kim Look at Life After Flash”), some other non-volatile semiconductor memory will come along to continue the cost/Gbyte trend for SSDs

These raw numbers are fascinating, but the implications for storage consumers and marketers are even more interesting. For example, Handy asked the question “What can you do with $10 of NAND Flash memory now and what will you be able to do with it in twenty years?” He answered that question with the following graph:

Courtesy of Objective Analysis (www.objective-analysis.com)

Today, you can store about a thousand songs on $10 worth of NAND Flash memory. You can store perhaps one or two standard-definition (DVD-quality) movies or two HD (Blu-ray quality) movies. As NAND Flash capacities rise, you’ll be able to store more music and more movies for that same $10. Around the year 2026 or 2027, said Handy, you’ll be able to store the entire iTunes music catalog--all 10 million songs--on $10 worth of NAND Flash. That information nugget suggests that there will someday be consumer-class devices that will ship pre-loaded with every song you might ever want and that you’ll merely pay a fee to unlock the songs that you want to hear. Don’t believe it? Well, back in the year 2000, the music companies didn’t believe they’d be selling songs by subscription instead of quaint plastic discs called CDs. Now CD sales are way down and iTunes rules the roost with downloadable music.

Then Handy asked a similar question about HDDs: What can you do with a $50 HDD? Here’s the graph he showed to answer that question:

Courtesy of Objective Analysis (www.objective-analysis.com)

Today, you can store more than 100,000 songs or 100 DVD-quality movies on a $50 HDD. By the year 2017, you’ll be putting the entire iTunes catalog, all 10 million songs, on that same HDD. By the year 2025, you’ll be able to fit the entire Internet Movie Database (www.IMDB.com) movie catalog--500,000 films--on one $50 HDD. By then, once again, you may be buying a consumer product preloaded with every movie ever made and simply paying a fee to watch the movies you want.

Handy claims that people will eventually collect movies on hard disk as they do now for music. Currently, people buy or rent DVDs and Blu-ray discs rather than keep them in HDD storage but eventually media storage will be so inexpensive that even movies will disappear comfortably into the maw of a $50 HDD. A subsequent panel of teenager media users underscored that point at Storage Visions 2010. The young panelists described their current media-consumption habits. Unlike their parents, they never buy music CDs unless giving them as gifts. They download all of their music. However, they currently do want physical DVDs and Blu-ray discs. Their children probably won’t.

The End of NAND Flash as we Know It: Micron’s Dean Klein and Samsung’s Tony Kim Look at Life After Flash

Denali Blog — Thu, 21 Jan 2010 20:21:53 GMT

By Steve Leibson for Denali Software

Today, NAND Flash is king of the semiconductor memories in terms of cost per bit, a position it has held since 2004 or 2005. Consequently, NAND Flash serves as the technology driver for semiconductor processing--a position previously held by DRAM, processors, and FPGAs. The top NAND Flash semiconductor vendors are currently fabricating NAND Flash memories using 3x nm lithography (34nm for Intel and Micron, 30 nm for Samsung). By some technology estimates, there are now only two generations left in the life of NAND Flash as we know it today. At the current pace of NAND Flash generational development, two generations equals 36 months. After that, NAND Flash device capacity will clearly stall unless some new development changes the fundamental design of the NAND Flash semiconductor memory cell. That's not just alarmist talk for the purpose of controversy. One of the people making such claims is Micron's Dean Klein, Vice President of Memory System Development, who delivered these warnings in a keynote at Storage Visions 2010 held earlier this month in Las Vegas, just before CES.

The Incredible Shrinking NAND Flash Memory Cell
(From the keynote presentation by Micron’s Dean Klein)

Some of the looming NAND Flash problems involve the inability of smaller-geometry Flash memory cells to safely handle the high programming voltage (25V) needed to induce electron tunneling, memory-cell crosstalk, parametric degradation of dielectrics at shrinking geometries (layers are now just a few atoms thick), and the fact that NAND Flash cells are already so small that the presence or absence of fewer than 200 electrons on the floating gate makes the difference between a digital zero and a one. Because of these growing problems, said Klein in his keynote, it will be very difficult to employ semiconductor process geometries smaller than 20nm for existing NAND Flash memory cell design. Klein then took one step back from the brink by noting that people previously said NAND Flash could not break through the 40nm barrier but obviously it did.

Semiconductor process and design wizards found ways to overcome those limits and those same wizards are searching for ways to overcome the present problems, but there is not yet enough visible progress to believe that a solution is imminent said Klein. One possible path to a solution is to employ 3D or vertical NAND Flash cell stacking, which would double chip capacity without shrinking the memory cell size. If successful, 3D stacking could add another two NAND Flash generations and postpone the need for a NAND Flash replacement technology for five to eight years according to Klein. NAND Flash vendors will use 3D stacking if it proves sufficiently practical, but only if it's practical.

In the end, semiconductor vendors always take the path of least resistance, said Klein, and there are candidate technologies that promise non-volatile alternatives to NAND Flash. Klein listed MRAM (magnetic RAM), FRAM (ferroelectric RAM), PCM (phase-change memory), resistive RAM, and crosspoint memory as candidate replacement memory technologies. Again taking a step back, Klein then stated that all of these replacement memory technology candidates currently have warts but his personal pick for the eventual winner is PCM.

Micron isn't the only semiconductor vendor staring down the loaded barrel of the NAND Flash scaling problem. In a one-on-one interview just prior to Klein's keynote, Samsung's Flash Marketing Director Tony Kim said much the same thing. Going to smaller NAND Flash geometries is becoming very difficult said Kim. Vendors are investigating different materials and designs for the NAND Flash memory cell’s floating gate, different cell architectures, 3D stacking, and multi-level cells (storing more than one bit per physical memory cell). However semiconductor technologists can see that time is growing short, there is an end to the technology, and so they're all seeking a high-volume semiconductor technology that will overthrow the current king of non-volatile memory, NAND Flash.

The Flash Factor for Consumer Devices: Will NAND Flash and Hard Disk Storage Coexist or Fight to the Death?

Denali Blog — Thu, 14 Jan 2010 02:51:10 GMT

By Steve Leibson for Denali Software

If you spend a lot of time reading and thinking about solid-state drives (SSDs), you may have gotten the impression that NAND Flash storage is at odds with hard-disk storage--that it's a winner-take-all situation. In his keynote at last week's pre-CES Storage Visions 2010 conference in Las Vegas, storage analyst Tom Coughlin dispelled that notion with some cogent slides and some insightful analysis. Coughlin founded the Storage Visions conference; he's the chairman of the annual Flash Memory Summit; and is the author of Digital Storage in Consumer Electronics published by Newnes Press in 2008. According to Coughlin’s free companion White Paper Flash & HDD -- Symbiosis, or Survival of the Fittest (published under his Objective Analysis market-research banner), Flash-based consumer applications such as personal music and video players, digital still cameras, and camcorders actually contribute to additional sales for hard disk drives (HDDs).

Coughlin began his keynote remarks with the following forecast slide, which shows the shipped storage capacity for optical disk drives (ODDs), HDDs, and NAND Flash devices from 2006 through 2014. HDDs will still be carrying the bulk of the capacity load by the year 2014 but NAND Flash’s storage share will grow significantly, to 274 exabytes of storage shipped compared to 427 exabytes of storage for HDDs. (One exabyte equals one billion Gbytes.) Note that Coughlin's prediction suggests that 2014 will be the first year that NAND Flash annual shipped capacity will exceed the annual shipped capacity of optical drives.

How do these immense numbers arise and where's the symbiosis between HDDs and NAND Flash memory? In his White Paper, Coughlin lists three examples of consumer applications where NAND Flash sales depend on and support HDD sales: digital still cameras (DSCs), personal music and video players (PMPs), and Flash-based camcorders.

According to Coughlin's White Paper, the average DSC user shoots an average of 549 photos per year and the average photo size is 4.7 Mbytes. That's roughly 2.6 Gbytes of photos per DSC user per year that needs storage. DSC and camera phone sales are rising at 5% per year, the average image size as measured in Mpixels is growing at 25% per year, and the number of photos that DSC and camera phone users are generating appears to be rising at a rate of 24% per year. Do the math and you'll find that the amount of storage needed to hold these photographs is increasing at a compound rate of 63% per year, based on Coughlin’s assumptions. As a result, almost two million drives per year will be sold to store digital images in 2014.

Couglin notes a similar symbiosis for HDDs with respect to PMPs. He writes that the average PMP owner's music and video storage needs are roughly 3:1 for HDD and PMP storage space. With the average PMP storage capacity now at 4 Gbytes, that's presently 12 Gbytes of HDD storage for each Flash-based playback device. In addition, most downloaded music and video must pass through a PC’s HDD (internal or external) before ending up on the PMP, which makes the HDD's existence that much more critical to PMP use. Again using some simple growth assumptions, Coughlin expects that PMPs will drive incremental HDD sales of 42 million just for music and video storage by 2014.

Using similar scenarios, Coughlin predicts that Flash-based camcorders will drive sales of an additional three million HDD sales in 2014 and online (cloud-based) storage for consumer images, video, and music will drive sales of an another incremental two million HDDs in 2014. The total comes to nearly 50 million incremental HDD sales annually--about 5% of total HDD sales--by the year 2014 as shown in the following figure. That’s symbiosis.

And what does NAND Flash get from this relationship? Coughlin posits that the availability of inexpensive HDD storage encourages the sale of DSCs, PMPs, Flash-based camcorders, and other Flash-based multimedia consumer products. In the case of camcorders, he goes even further, claiming that a majority of the projected Flash-based camcorder sales “would never be sold if hard drives weren’t available.” That’s symbiosis.

“Altogether,” writes Coughlin in his White Paper, “our projected 2.2 exabytes of Flash memory [sales] in 2014 (estimated to be 59% of the total consumer Flash demand) would be significantly smaller if HDDs were not available to support them.” That truly is symbiosis.

So if you were thinking that Flash in the form of SSDs and other Flash-based storage arrays were going to kill off HDDs in the near future, Coughlin would strongly disagree. He sees a long, cooperative future ahead for the two technologies and he has published data publicly to back up that claim.

Low Power DDR Options -- From the Trenches

Denali Blog — Thu, 07 Jan 2010 01:52:22 GMT

by Marc Greenberg, Director of Technical Marketing, Denali Software
Momentum for LPDDR2 is building. It's mostly in the mobile space, and it's been in the general area of Handsets, MIDs, and other mobile devices. Both high-end and low-end handset customers are seeking LPDDR2 support, which is interesting since LPDDR2 was initially thought to be a high-end technology. Long-term, LPDDR2 devices are expected in a lot of embedded applications where DDR3 is unsuitable for various reasons.

When it comes to building chips today, the LPDDR2 market is still maturing and device availability is just now coming on-line, so chip guys need to hedge their bets by supporting at least one other memory technology, sometimes more.

The first hedge for pure handset folks is an LPDDR2/LPDDR1 combo. This allows them to get into a low-power memory with LPDDR1 or LPDDR2 technology, but the performance for this combo is limited by LPDDR1 which has a maximum clock rate of 200MHz (DDR400) and in reality, 166MHz is the popular frequency for LPDDR1. So, this doesn't work for high-end solutions since they are sacrificing performance or would need to deploy a wider interface.

The second hedge is DDR2. DDR2 makes a nice combo with LPDDR1/LPDDR2 because the IO voltage of DDR2 is 1.8v, same as LPDDR1, so you don't need a different oxide in the IO if you were already supporting 1.8v for LPDDR1. DDR2 is the low-cost memory leader and available up to 533MHz (DDR1066) today. So the LPDDR1/LPDDR2/DDR2 combo has been popular for most of 2009.

Lately, more companies are looking forward at DDR3. DDR3 offers the advantage of a 1.5v I/O and for the most part DDR3 is built on smaller process geometries so uses less power in general. The chart below shows a comparison of different memory technologies at the same throughput. The take-away from this chart is that a 16-bit DDR3 running at 333MHz (DDR667) is about the same power as a 32-bit LPDDR1 running 166MHz(DDR333) so there is equal throughput and similar power usage between DDR3 and LPDDR1.

Click to enlarge

This is not a completely fair comparison -- there are lots of things not considered:

SSTL IOs of DDR3 use a lot more power than the LVCMOS pads of LPDDR1;
DDR3 needs termination which uses power;
Those 16 extra DQ pins (plus 2 DQ and 2DMs) required for LPDDR1 also use power;
LPDDR1 can go into a low power mode more often and more easily;
LPDDR1 uses less power in standby;
etc...

So, let's look at the decision-making process: if I am a high end mobile customer, I need LPDDR2, that much is certain. I probably want to hedge my bets with another memory technology to ensure that I have supply of some memory in case LPDDR2 is expensive or unavailable. If I choose LPDDR1, I need to put down 2X the IO pins for data to get into a part that uses 10% less power than DDR3, remembering that LPDDR1 was first introduced over 6 years ago. Or, I keep the same number of IO pins, use the most mainstream memory for 2010 and beyond (DDR3), and live with 10% more power usage in my memory.

Finally, with mask costs and chip development costs being what they are, everyone has an eye on being able to use their chip in more than one application space. Even if the chipset is primarily mobile, with the projected cost of DDR3 being less cost per bit than DDR2 starting in 2010, DDR3 becomes a "must-have" for new chip designs.