Peter Heller Blog

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

PeteHeller — Fri, 14 Sep 2012 17:31:00 GMT

Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;} Earlier this year, Cadence announced the expansion of its VIP Catalog to include Accelerated VIP (AVIP). AVIP is used together with Cadence's Verification Computing Platform to enable RTL verification. AVIP running on the Palladium XP platform consistently executes hundreds of times faster than with simulation. Obviously this is great news for validation teams since designs routinely exceed 50Mgates these days and much greater performance is needed.

AVIP is also proving to be uniquely suited for another purpose: driver/firmware integration and validation. Cadence is seeing strong demand from our customers for this need.

One example I've been closely monitoring is Samsung Memory. I thought I'd draw your attention to it since many of our customers could similarly benefit from this approach.

Samsung has been using Cadence AVIP to verify their new PCI Express based solid-state drive (SSD) design. Samsung SSDs are typically being employed in laptops and servers to reduce power and space and increase reliability relative to traditional hard disk drives.

A bit of history...

This year Samsung Memory added a PCI Express interface to their SSD controller design. The PCI Express design addition significantly increases transaction rates and reduce latencies relative to earlier SSSD generations. To verify the block level protocol compliance of the new interface they began by using Cadence's simulation VIP. This proved to be highly effective. However, when the time came to do firmware/driver validation at the SoC level, they found the simulation environment wasn't sufficiently fast. In fact, Samsung determined they'd need a validation environment capable of delivering hundreds of times greater performance.

When they turned to Cadence for suggestions we recommended using our PCI Express Accelerated VIP (AVIP) with a C++ user interface designed for Palladium XP simulation-acceleration. Since Samsung had already used our PCI Express simulation VIP, the transition to AVIP was even more straightforward than usual. Within three weeks the accelerated environment was up and running. This in itself was highly advantageous since it meant Samsung's driver developer/integrators would become productive much sooner than if they'd had to wait for an FPGA prototype. It also enabled Samsung to realize validation productivity gains of 100%. See the Samsung Memory success story for additional details.

Summary

Samsung's experience, taken together with other customers has made clear that driver/firmware validation is becoming crucial step in SoC level validation. In fact we are seeing rapidly increasing demand for this use model.

Cadence AVIP optimizes Acceleration/Emulation to enable software driven use models. Seeing this trend we are already working on ways to make firmware/driver validation even easier and faster. If you've got a project nearing the SoC validation phase I'd urge you to connect with Cadence. We're confident that AVIP in conjunction with our Palladium XP Verification Computing Platform and RTL simulation can help you to improve productivity and quality in your projects.

Pete Heller

The Facts: Why Accelerated VIP Is Needed for SoC Verification

PeteHeller — Tue, 15 May 2012 13:30:00 GMT

On Tuesday May 15^th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question. This blog will answer that and explain the rationale behind Cadence's AVIP and more about our products and plans going forward.

A key driving factor impacting verification approach is the size of the design. Today designs commonly are in the 10's and even 100's of millions of gates. And software size is growing at an even faster pace. There's no respite in sight for these torrid growth rates. So even if you don't face such verification challenges immediately, read on, because they're coming.

Verification teams have taken notice of these facts and are adapting their approaches. It's become a necessity to expand the set of functional verification tools employed beyond just simulation. That's because simulation times have become excessive for SoCs, and even for many subystems. Consequently, leading companies have adopted accelerated platforms and accelerated verification IP (AVIP) for their hardware verification.

In addition, to tackle the expanding firmware/software development challenge, acceleration is frequently being used in tandem with a virtual prototype such as Cadence's Virtual System Platform. This enables the CPU cycles to be run separately from the rest of the logic to maximize software execution speed. These verification techniques are enabling leading verification teams to meet their design goals such as shortening overall product development cycle, increasing design functionality, reducing power consumption, and/or improving quality.

Such leading companies have adopted a tiered approach to system integration and verification. Their best practices include setting verification goals for each integration tier and selecting the verification methods and metrics to maximize those specific goals. These include:

Hardware IP Development and Verification
Hardware Subsystem/SoC verification
Hardware/Software Integration and Validation

For a more detailed discussion regarding the verification approaches being employed, please see Cadence's just published Comprehensive Acceleration White Paper.

That begs the question: is simulation and simulation VIP a dead end? Absolutely not. Simulation has an important place in the verification continuum, but as Clint Eastwood so famously said in his Dirty Harry role "a man's got to know his limitations."

Simulation's role is increasingly limited to IP/block verification. That's a critical role and a key reason that Cadence continues to invest heavily in simulation VIP in addition to accelerated VIP. But when it comes to SoC verification, the need for speed is crucial. We've seen from customers that SoC verification requires performance gains of at least 20X over simulation. And very commonly performance gains must be in the 100X-1000X over simulation when the full SoC is being validated and/or software is being developed. Meeting these needs is exactly why Cadence has brought acceleration and AVIP to market.

But be wary! Other VIP suppliers have posited that a 4X gain in simulation VIP speed will enable its use in SoC verification. First of all, Even if you take such speedup claim at face value, a 4X gain in VIP performance only translates to a 13% gain in overall performance. That's why Cadence takes a very different perspective. For more information my colleague Tom Hackett just wrote an excellent article about how testbenches and testbench languages must be properly applied and used on the right verification platform for SoC level verification. And, unlike other unsubstantiated claims, Tom's article includes hard data and simple math to back up our positions.

Like other accelerated VIP, Cadence AVIP uses a SCE-MI interface to connect to a host workstation. However, that's pretty much where the similarities end. Cadence AVIP is uniquely architected to deliver a range of performance and verification tradeoffs, all under user control.

OK, so you're sold on the need for accelerated VIP, why should you select accelerated VIP from Cadence? Cadence AVIP has several advantages. A partial list includes:

Cadence AVIP delivers high performance. All customer engagements have demonstrated the AVIP meets or exceeds its performance targets. To achieve the high performance, the AVIP employs another unique architectural advantage: the Acceleration Optimized Core.
Cadence AVIP provides multiple user interfaces to enable you to use just one single AVIP for all your verification tasks. These interfaces and their uses are briefly described below:
Cadence AVIP supports a UVM interface for easy UVM testbench reuse in acceleration, with the same consistent user interface as the Cadence simulation VIP. This also enables the AVIP to support testbenches written in verification languages such as SystemVerilog and e.
For testbenches written in C or C++, the C/C++ interface is used to deliver a higher level of performance than with the UVM interface, typically hundreds of times greater than with simulation
It is also possible to eliminate the testbench completely using the embedded interface. With the entire design running on the Palladium platform users get the maximum validation performance. (This can also be referred to as emulation.)
The TLM 2 interface is used for software development and/or hardware/software co-development.

Figure 1. Cadence AVIP provides multiple user interfaces so you can use a single AVIP for all your verification needs

Cadence AVIP provides "knobs" enabling you to make tradeoffs between performance and verification functionality. For example, streamlined stimulus generation, checking, and coverage for UVM environments are all under user control.

Thanks for reading this far! I suspect you're now wondering what protocols does Cadence provide AVIP for? Great question. Today Cadence provides AVIP for AMBA AXI 3/4, AMBA 4 ACE (including ACE Lite), PCI Express 2/3, USB 3.0, HDMI 1.4, SATA, and Ethernet 10G. We have plans for more protocols including MIPI and DisplayPort. I encourage you to get in touch with your Cadence AE or salesperson to discuss your needs with us.

For more information on AVIP, click here.

Pete Heller

ARM/Cadence Video: How ACE Coherency Adds Value and Verification Complexity

PeteHeller — Mon, 19 Sep 2011 18:00:00 GMT

The number of licensees for ARM's Cortex-A15 CPU core is growing rapidly, particularly for mobile computing applications. Customers tell us that's because it provides multiprocessor support and hardware based coherency while consuming only a small amount of power. In our experience the majority of A15 designs are also adopting the new ACE protocol due to their need for a fast and reliable coherency scheme.

To help potential A15 designers learn more about ACE, ARM and Cadence partnered to develop a video about ACE and ACE verification. It's only about 10 minutes long -- I encourage you to view it. In addition you can see my previous blog discussing the need for hardware based coherency.

While ACE compliance is challenging to verify, the even bigger verification challenge is ensuring the design is actually coherent. This is where Cadence's complete ACE verification solution provides superior value. We are seeing that nearly all ACE designs also incorporate fabrics such as ARM's CCI-400 and/or NIC-400. For this type of design it's necessary to have three verification tools all working in conjunction:

ACE Verification IP
Interconnect Monitor
Intelligent ACE Scoreboard

Only by having the ACE VIP, Interconnect Monitor and Scoreboard working together can you be assured of achieving end-to-end design coherency. Cadence's solution addresses all the common ACE/coherency verification challenges. For example it will:

Create the necessary scenarios needed to mimic processor and memory behavior including snooping operations
Ensure data coherency (i.e. ensuring that only one copy of any data is valid)
Ensure that all simultaneous write/snoop combinations are managed correctly
Ensure no scenarios create deadlocks

You can open the video below or click here to view:

For more information about ACE verification we encourage you to contact your Cadence field representative. You can also view our AMBA VIP information page. You'll find a datasheet there as well.

Pete Heller

Verifying AMBA® 4 ACE Designs – Cadence is Ready to Help, Now

PeteHeller — Tue, 16 Aug 2011 01:00:00 GMT

ACE is here. Are you ready?

Designers of multimedia smartphones, tablets, and other mobile computing devices face greater challenges than ever. They have to deliver ever more capable and responsive systems, yet must also consume the least amount of power possible -- certainly no more than their competitors.To achieve these goals, designers have been employing multi-processor architectures for many years. However, the need to squeeze the last drop of performance and power out of these compute clusters is now paramount. A big area of opportunity for performance gains/power reductions is through moving software-based cache-coherency management into hardware. ARM introduced the AMBA Coherency Extensions (ACE) protocol in June 2011 to address these very needs.

But alas, as we all know, there's no free lunch. Placing such an extensive additional function into hardware significantly expands the functional verification challenge and risk. Cadence recognized this well over a year before the ACE specification became public. In close collaboration with ARM we launched an aggessive development program to deliver a complete ACE verification solution in time for ARM's lead Cortex-A15 customers to use. That goal was accomplished and enabled Cadence to have mature verification IP (VIP) in time for ARM's public announcement of ACE.

More Info Available

The need for ACE and ACE verification as well as Cadence's VIP solution are discussed in the recently published EE Times article "Get control of ARM system cache coherency with ACE verification". I encourage you to take a look.

Get In Touch

And, as you plan your ACE or AMBA® 4 based system, I recommend that you connect with Cadence, the leading experts in this field. We have the most capable and mature solutions to help. Talk to you soon!

Pete Heller