https://community.cadence.com/searchen-USTelligent Community 12https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/62587/place-module-mdd-file-without-using-hierarchical-blocksSat, 21 Sep 2024 12:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62587Hussain Aalim/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/62587/place-module-mdd-file-without-using-hierarchical-blocks0Hi, I am trying to automate “ Place Module ” functionality of allegro by creating a module .mdd file and placing the module but I don’t want to use hierarchical blocks. Please help me with the automation of placing the modules without hierarchical blocks. For this, I have created a module (.mdd) and linked it with the schematic using “ Annotate ” functionality of OrCAD under “ PCB Editor Reuse ” tab. To use that module in the allegro, I had to place hierarchical blocks in the actual schematic that is going to be used for the design, and then linked the hierarchical blocks with the .dsn file of the “Reuse module” schematic. After that we annotated the schematic to use the Reuse Module in a new design. Later on, reuse module gets called by importing logic files and starts appearing under Placement section of “ Module Instances ” in allegro. There’s only one challenge that I want to overcome: this method of creating reuse modules requires a dependency on hierarchical blocks. The main limitation here is that I cannot use hierarchical blocks in my designs. Please provide an alternative solution that allows me to call modules intelligently without the dependency on hierarchical blocks. I would also like to have skill code available for this solution. Thanks in advance.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/62569/plotting-template-kept-plotting-placeholder-history-instead-of-current-history/1401187Sat, 21 Sep 2024 12:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401187HongJian/cadence_technology_forums/f/custom-ic-design/62569/plotting-template-kept-plotting-placeholder-history-instead-of-current-history/1401187Hi, thanks a lot. Will do thathttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62584/rotate-options-menu-missing-quickly-disappears/1401186Sat, 21 Sep 2024 12:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401186PK20240920135/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62584/rotate-options-menu-missing-quickly-disappears/1401186THank you for your reply. I entered this mode by mistake and dont need this feature. Is there a way to exit to normal symbol origin based rotate by using the command prompt ?https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/62583/files-for-nmdrc-in-calibre-for-gpdk180nm/1401185Sat, 21 Sep 2024 10:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401185Andrew Beckett/cadence_technology_forums/f/custom-ic-design/62583/files-for-nmdrc-in-calibre-for-gpdk180nm/1401185Given that Calibre is a tool from Siemens EDA (not Cadence), the various generic PDK releases do not include Calibre rules (we do not have access to the tool to write or validate the rule files). Support is there (depending on the PDK) for Assura and/or PVS, two of the Cadence physical verification tools. Andrewhttps://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/62576/failed-to-create-a-form-in-a-window/1401184Sat, 21 Sep 2024 07:16:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401184Martinsh/cadence_technology_forums/f/custom-ic-skill/62576/failed-to-create-a-form-in-a-window/1401184Hi, Andrew, If the form is created in a window, the function hiGetCurrentForm() can't get the form correctly. In following code, I'd like to pass the form handle as an argument of function funcLoad(), but failed. How to fix this problem? btnLoad = hiCreateButton(?name 'btnLoad ?callback " funcLoad(hiGetCurrentForm()) " ?buttonText "Load" )https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/62579/ams-simulation-use-systemverilog-module-instantiating-other-submodules-in-systemverilog/1401183Sat, 21 Sep 2024 06:41:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401183Mathieu Chene/cadence_technology_forums/f/mixed-signal-design/62579/ams-simulation-use-systemverilog-module-instantiating-other-submodules-in-systemverilog/1401183Hi, Thank you for your answer. I did it, I have just created a dedicated library SYSTEMVERILOG_lib to store these cell views . It works for one module (address_decoder) but muxReadX is not linked...https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/62586/regarding-code-to-generate-analog-matching-set-patternSat, 21 Sep 2024 06:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62586NG202409204827/cadence_technology_forums/f/custom-ic-design/62586/regarding-code-to-generate-analog-matching-set-pattern0Hi Team, Apart from modgen is there any tool to generate various Matching set with variation percentage for the selected number of devices. Thankyou, Nagarajhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59357/copy-duplicate-pages-within-a-dsn-in-orcad-using-tcl/1401181Sat, 21 Sep 2024 02:42:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401181tennywhy/cadence_technology_forums/pcb-design/f/allegro-x-scripting-tcl/59357/copy-duplicate-pages-within-a-dsn-in-orcad-using-tcl/1401181CadAP could you give me some more advice ? thanks.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62584/rotate-options-menu-missing-quickly-disappears/1401180Fri, 20 Sep 2024 22:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401180John T/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62584/rotate-options-menu-missing-quickly-disappears/1401180Hi PK, yes I see this error actually when I rotate a symbol about an unusual pin number such as bga; if I then try to rotate another component about a pin that does not exist on the second component I get an error message. Thanks for pointing out this issue! This is easily remedied using pre-command instead of post-command. Simply type spin into the command prompt. Now the options tab "Sym Pin #" can be modified to a relevant pin number. This can therefore be set before selecting any component for rotation.https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/62579/ams-simulation-use-systemverilog-module-instantiating-other-submodules-in-systemverilog/1401179Fri, 20 Sep 2024 21:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401179tpylant/cadence_technology_forums/f/mixed-signal-design/62579/ams-simulation-use-systemverilog-module-instantiating-other-submodules-in-systemverilog/1401179How about creating a systemverilog cellview for 'B' that has the module B code in it? Timhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/62585/gerber-and-other-manufacturing-export-via-skillFri, 20 Sep 2024 20:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62585drdanmc/cadence_technology_forums/pcb-design/f/allegro-x-scripting-skill/62585/gerber-and-other-manufacturing-export-via-skill0Are there some SKILL functions for generating manufacturing files such as RS247X, NC Drill, and also things like STEP export, PDF export, etc? Or do these things need to be done via individual command line programs like `artwork`? My goal is to automate as much as possible to make it possible for anyone on the team to be able to generate these files without needing to navigate several different menus and be presented with many different options that will get in the way of consistency across a team. I don't have much Allegro experience but have extensive experience with Virtuoso, SKILL in Virtuoso, and the IC flow in general. I've always used automation for chip tapeout so anyone on our team can confidently generate all output with a simple command. Thanks -Danhttps://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62584/rotate-options-menu-missing-quickly-disappearsFri, 20 Sep 2024 18:52:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62584PK20240920135/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62584/rotate-options-menu-missing-quickly-disappears2I selected in the options menu during component rotate, the last option of the drop down "Symbol Pin Number". And some default value there set to 'E'. Now every time i try to rotate another component the command window spits out " There are unmatched pin numbers". And the options menu closes quickly without allowing me to enter another option. So basically its stuck in this bugged mode and i cannot find a way to change that option back to "User Pick", "Body Center" etc... This is definitely a bug. Is there a way to bring that options menu to defaults or change it without entering a rotation mode ? What i am having to do now as a workaround is right click and enter move then change the rotate settings and rotate the component. But still does not change the global.https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/62583/files-for-nmdrc-in-calibre-for-gpdk180nmFri, 20 Sep 2024 18:33:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62583Sameerpy/cadence_technology_forums/f/custom-ic-design/62583/files-for-nmdrc-in-calibre-for-gpdk180nm1Hi , I tried to run nmDRC in calibre but don't know which file to be included in DRC rules files section as a valid DRC file. I already take a look in directory gpdk180nm but not able to know which DRC file to be included in this section. Thank in advance.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62562/adding-parallel-lines/1401178Fri, 20 Sep 2024 18:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401178John T/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62562/adding-parallel-lines/1401178I have now created the Cadence Change Request (CCR) number 3047246 for this enhancement.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62562/adding-parallel-lines/1401177Fri, 20 Sep 2024 17:51:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401177John T/cadence_technology_forums/pcb-design/f/allegro-x-pcb-editor/62562/adding-parallel-lines/1401177Hi Masamasa, yes I can see this issue repeated on my machine. I have checked it just now. This appears to be an oversight on our part. Let me raise an enhancement request internally to ask for the values entered to be retained. However, if you enter a value while in command, you can copy offset several lines in succession and the offset value is retained for the duration of these multiple operations. Have you found this also?https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/62581/want-to-fetch-the-part-reference-and-designator-in-orcad-capture-cis/1401176Fri, 20 Sep 2024 15:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1401176CadAP/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/62581/want-to-fetch-the-part-reference-and-designator-in-orcad-capture-cis/1401176Hi Hussain Aalim , There are two method to get it: 1. use property iterator to itrate over properties of an object. NewEffectivePropsIter(status) : returns DboEffectivePropsIter Class : DboPortInst(DboBaseObject,DboInstOccMapper): Parameters: status: DboState & 2. After selecting object you can use below command to get the property value: GetProperty "Part Reference" GetProperty "Designator"https://community.cadence.com/cadence_technology_forums/f/custom-ic-skill/62582/using-dbcreaterect-for-rx-layerFri, 20 Sep 2024 15:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62582MSP032/cadence_technology_forums/f/custom-ic-skill/62582/using-dbcreaterect-for-rx-layer0Hi, I'm unable to create a rectangle of RX layer using the dbCreateRect function. Please let me know if I'm missing anything. Thanks, Mallikarjun.https://community.cadence.com/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/62581/want-to-fetch-the-part-reference-and-designator-in-orcad-capture-cisFri, 20 Sep 2024 13:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62581Hussain Aalim/cadence_technology_forums/pcb-design/f/allegro-x-capture-cis/62581/want-to-fetch-the-part-reference-and-designator-in-orcad-capture-cis1Needed help in fetching the Part Reference and Designator. I have used GetReference and GetReferenceDesignator both returns the "Reference". Please help with the command to fetch " Part Reference" and "Designator" Thanks in advancehttps://community.cadence.com/cadence_technology_forums/f/awr-design-environment/62580/transfer-layout-from-awr-to-allegro-orcadFri, 20 Sep 2024 13:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62580MTalha/cadence_technology_forums/f/awr-design-environment/62580/transfer-layout-from-awr-to-allegro-orcad0I heard about unified library between AWR and Allegro PCB editor. Is this a good method to transfer layout to a PCB editor? Another question, I am confused of the difference between Allegro and Orcad and each one has many programs inside. Is there a difference between Orcad and Allegro PCB editor? and what are all of these ?https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/62579/ams-simulation-use-systemverilog-module-instantiating-other-submodules-in-systemverilogFri, 20 Sep 2024 12:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:62579Mathieu Chene/cadence_technology_forums/f/mixed-signal-design/62579/ams-simulation-use-systemverilog-module-instantiating-other-submodules-in-systemverilog2Hello, First, thanks for reading this post ! I am working on a mixed signal simulation using ADE explorer and AMS simulator. In the top design I have a module A I want to instantiate as a systemVerilog object. in the sv file this module include a submodule B also defined in sv. Both modules are defined in the same file /* Start file*/ module A(); B(ports...) endmodule module B(); description .... endmodule /*end file*/ When I generate the netlist it fails telling that B (here muxReadX) is not defined in config view .... Then I tryed to use a separate sv file for B in to use the `include "pathToB" method (adding the path to B in the ams simulator option) but I have the same error. /* Start file*/ `include "path_to_B" module A(); B(ports...) endmodule /*end file*/ Then I created a library named SYSTEMVERILOG_lib in which I store the sv description. I added it in the library list of my config view but it still does not find it (address_decoder is found and I do not know why it is different here) Do you have any idea on how to solve this ? I have also to precise that I do not have this issue with sv module that does not call submodule. I am using IC23.1 I have already seen this post but it was not helpful: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000006DdhMUAS&pageName=ArticleContent How to include Verilog functional files in Virtuoso Hierarchy Editor for SDF Simulation In AMS simulation, for verilog, how to use a module in a top module? I would be glad to give more precision if needed. Thank you in advance for your help Mathieu