Pete Hardee Blog

Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?

Pete Hardee — Tue, 12 Feb 2013 16:00:00 GMT

I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here. In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired by Horst Diewald, chief architect of MSP430^TM microcontrollers at Texas Instruments, the group's line-up is an impressive "who's who" of the microcontroller space, including Analog Devices, ARM, Atmel, Cypress, Energy Micro, Freescale, Fujitsu, Microchip, Renesas, Silicon Labs, STMicro, and TI.

As the press release explains, unlike usual processor benchmark suites which focus on performance, the ULP benchmark will focus on measuring the energy consumed by microcontrollers running various computational workloads over an extended time period. The benchmarking methodology will allow the microcontrollers to enter into their idle or sleep modes during the majority of time when they are not executing code, thereby simulating a real-world environment where products must support battery life measured in months, years, and even decades.

Processor performance benchmarks seem to be as widely criticized as EPA fuel consumption figures for cars - and the criticism is somewhat related. There is a suspicion that manufacturers can tune the performance for better test results, rather than better real-world performance. On the face of it, the task to produce meaningful ultra low power benchmarks seems even more fraught with difficulties. For a start, there is a vast range of possible energy profiles - different ways that computing is spread over time - and a plethora of low power design techniques available to optimize the system for the set of profiles that particular embedded system is likely to experience. Furthermore, you could argue that, compared with performance in a computer system, energy consumption in an ultra low power embedded system has less to do with the controller itself and more to do with other parts of the system like the memories and mixed-signal real-world interfaces.

EEMBC cites that common methods to gauge energy efficiency are lacking in growth applications such as portable medical devices, security systems, building automation, smart metering, and also applications using energy harvesting devices. At Cadence, we are seeing huge growth in these areas which, along with intelligence being introduced into all kinds of previously "dumb" appliances, is becoming known as the "Internet of Things." Despite the difficulties, with which the parties involved are all deeply familiar, I applaud this initiative. While it may be difficult to get to apples-to-apples comparisons for energy consumption in these applications, most of the time today we don't even know where the grocery store is. If the EEMBC effort at least gets us to the produce department, we're going to be better off.

Pete Hardee

Low-Power Technology Summit Proceedings Now Available

Pete Hardee — Thu, 06 Dec 2012 00:09:00 GMT

On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit Proceedings archive, which just went live.

We've put both video and PDF versions of the presentations there. Obviously the PDFs give you the quickest access to the material, but you'd be missing a lot to just grab those. Seeing and hearing the presenter in action is important, especially when one of the keynotes, entitled "The power wall - are we scaling it or is it just getting higher?", is delivered by a noted expert like Professor Jan Rabaey of the University of California at Berkeley. The videos also have the Q&A sessions at the end of each presentation -- there were lots of good questions, and good interaction. You do need a "Cadence Community" login to access those, so there will be a quick one-time registration for the login if you don't already have it.

Prof. Jan Rabaey presents at the Low Power Technology Summit

As well as the keynote from Professor Rabaey (which Richard Goering also covered in a blog here), there were also presentations from Sathya Subramanian of ARM on Low-Power Design with ARM® Physical IP and POP^TM IP, and technical updates from the Cadence team.

My personal highlight from the day was the presentation by Anis Jarrar of Freescale. Anis talked about all the measures they took to meet the aggressive power specifications on the Kinetis family of chips. Kinetis has been highly successful for Freescale, and they really are using all the tricks in the book (and then a few that aren't) to minimize power on these designs. You can also find more about Kinetis here. As well as the usual techniques (clock-gating, multi-Vt, Multi-Supply Voltage, Power Shut-off) they were also an early user of multi-bit register mapping in RTL Compiler. Further, they found a novel way to apply body bias that avoided the need for that inefficient, tricky way to generate a negative bias supply -- the charge pump. The audience was very happy to learn more about Anis's experiences, and the Q&A session for this one was lively and informative.

Finally, the presenters were joined by representatives of Broadcom and Berkeley Wireless Research Center for a panel session moderated by Richard Goering. Panelists provided a great low-power design-related discussion. You can also read Richard's blog on that, for a summary.

Enjoy!

Pete Hardee

Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS

Pete Hardee — Thu, 29 Nov 2012 16:30:00 GMT

The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises.

First, some of the expected stuff. We'd noticed in the last major surveys done almost two years ago (see the Perspective on Power blog from December 2010) that advanced low-power design techniques were starting to be applied outside of mobile (battery-operated) devices, and this trend has increased. 49% of the attendees surveyed worked on non-mobile end-applications. As in 2010, very nearly 100% were already using basic low-power techniques like clock gating and multi-Vt optimization. But the people using advanced techniques "currently" increased from 60% to 70% (see figure below).

As before, we define advanced low power techniques as the ones that apply to power domains - splitting the design into separately-powered areas where the voltage can be shut off to reduce leakage (Power Shut-Off - PSO, aka State Retention Power Gating - SRPG) or supplied with different voltage levels (permanently in the case of Multi-Supply Voltage - MSV, or dynamically in the case of Dynamic Voltage and Frequency Scaling - DVFS).

As in 2010, PSO was the most popular of the advanced techniques, followed by MSV, then DVFS. What was less expected was that, in contrast to 2010 where the "future" use of advanced techniques increased all of them proportionately, in the 2012 results, the designers surveyed were expecting to use a lot more DVFS in their next designs, pushing it into second place in front of MSV.

So why might DVFS become more popular than MSV? Both use different supply voltages for domains that have different performance needs. The difference is that DVFS allows the voltage level, or more usually a combination of voltage and clock speed, to be selected on the fly based on current performance demand. It is therefore a more complex technique to implement and verify, meaning that the designer has to achieve sign-off for power domain to which it applies at multiple modes and corners.

Also, opportunities to apply MSV may have already been fully exploited and designers are looking for more. Recently, design tools such as the Cadence Encounter RTL-to-GDSII flow support design closure for multi-mode multi-corner (MMMC) simulations, which is an important enabler for an increase in the use of DVFS on the next generation of designs.

Pete Hardee

Packed House Expected for Cadence Low-Power Technology Summit

Pete Hardee — Tue, 16 Oct 2012 17:28:00 GMT

It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full agenda covering multiple aspects of low-power design.

No longer the sole preserve of designers needing to extend battery life, low-power design has become ubiquitous in many different applications from mobile devices to datacenters. We have recently seen a bifurcation in the needs of our customers --- on the one hand, for power optimization in high-performance digital design, and on the other hand, ultra-low-power design techniques in a myriad of smaller, lower performance but none-the-less challenging mixed-signal devices. There will be technology updates from Cadence focusing in each of these areas. We also expect the audience to be given plenty to think about from our keynote speaker, Professor Jan Rabaey, of U.C. Berkeley. I just wanted to highlight a few of my favorites that I'm really looking forward to from the agenda.

Keynote speech by Professor Jan Rabaey - see Richard Goering's blog from a couple of weeks ago for more information on Professor Rabaey
Sathya Subramanian of ARM will talk about low-power support in ARM's physical libraries, memories, and also optimization of processor implementation with POP^TM IP and ARM-Cadence collaboration on design flows
Anis Jarrar of Freescale will talk about low-power design experiences on the latest Kinetis series of ARM Cortex®M-powered mixed-signal chips
Panel discussion moderated by Richard Goering with interesting diverse and experienced panelists:
- Sathya Subramanian of ARM
- Qi Wang of Cadence
- Anis Jarrar of Freescale
- Sushma Honnavara-Prasad of Broadcom
- Gary Kelson of the Berkeley Wireless Research Center

For more details on the agenda, times and logistics, please see the Cadence event page.

See you on Thursday!

Pete Hardee

Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year

Pete Hardee — Mon, 17 Sep 2012 13:00:00 GMT

CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far from San Jose, USA; Munich, Germany; and Hsinchu, Taiwan. If you click on those proceedings links, you get to a multitude of different tracks and, for those interested in everything low-power, it can be quite challenging to find all the relevant presentations. So I've saved you the trouble of hunting through by gathering them all here - 12 so far from Cadence customers plus 3 useful presentations from Cadence's own technologists.

Note: you will need to log in with your cadence.com user account to access the papers. If you don't have one, create a Cadence.com User Account now.

A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP
Norman Chan, Rambus
Conformal Low Power - Complex Low Power Design Verification
Sorin Dobre, Qualcomm
CPF in AMS Simulation and Macro IP
Qingyu Lin, Cadence
Low Power Implementation on Freescale Kinetis Family
Anis Jarrar, Freescale Semiconductor
Techtorial: Low Power Failures--What not to Plan
John Decker, Cadence
Low-power Verification using UVM SystemVerilog
John Decker, Cadence
Automation of Switch Insertion and Power Network Generation in 28nm PSO Designs
Shane Stelmach et al, Texas Instruments
Multi Voltage Domain, Multi VT Low power physical implementation with Cadence tool suite
Harald Hopperdietzel & Uwe Ratzmann, Texas Instruments
Power Calculation From Early Estimation to Silicon Correlation
Johannes Bruecker, Renesas Electronics
Implementation of a Flexible, Low Power and High Performance 4G Baseband Processor
Peter Debacker et al, imec
Hierarchical CPF Usage in ST-HED Low Power Flow
Sylvie Pierunek, STMicroelectronics
Early, Functional Unit-Based, Power Estimation for Wireless Baseband Processors
Peter Debacker et al, imec
Challenging Verification for Complex Low-Power Design without Always-Power-On Domain
Zhaohui Hu, ST-Ericsson
Effective GPU platform verification and power estimation solutions with Palladium
Kaowen Liu, MediaTek
Design Closure in 28nm Low-Power Design with EDI
Jurcy Huang, Socle
Huge thanks to all who contributed these presentations!

Pete Hardee

Mixed Signals from European Low-Power Designers

Pete Hardee — Wed, 25 Jul 2012 21:47:00 GMT

Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it a good time to visit - while it was nice in Germany the Northern European summer has been a disappointment so far, although the two days I spent in Scotland were, I'm told, the first two rain-free days since April.

It was a good time because our customers were keen to get a mid-year update, especially since so few make the trip over to DAC nowadays. And we had plenty of interesting stuff to share. But the value for me is not really the communication of our latest stuff to our customers; it's more listening to what their changing needs are. More than I'd ever experienced before, the needs stem from the confluence of low-power and mixed-signal design challenges.

While much of the semiconductor industry globally seems preoccupied with digital design in advanced nodes like 28nm, and starting to think about 20nm and beyond, you can practically count the companies in Europe involved with such designs on the fingers of one hand. However, if I try to count the companies involved with mixed-signal designs, combined with the need to meet stringent power specifications, I fast run out of digits.

The European chip design scene is all about mixed-signal and low-power in a wide range of mobile, automotive, industrial and medical applications. While designs tend to be implemented in less advanced process nodes - in companies I visited many new designs are moving to the 65nm node and designs at 90nm, 130nm and even 180nm are still commonplace - the designs are every bit as challenging. The challenges are just different. In the pure digital world, unless you've been living under a rock for the past couple of decades, you probably know that CMOS process technology has been able to follow Moore's Law - the approximate doubling of transistor count every two years. Try doing that with RF devices, passives, power management components, MEMS, or in short, all of those components you need to interface with the (analog) real world. Fabs specializing in mixed-signal technologies have recently coined the phrase "More than Moore" to describe this challenge.

Power-wise, these mixed-signal designs are no less challenging. Medical devices and smart card applications in particular have pushed back the state-of-the-art in ultra-low-power design. Power specifications in the automotive world have become tighter and tighter as the rapidly-growing electronics content adds up to significant power demand, and power densities are strictly controlled to avoid temperature-related reliability issues in an already pretty hostile environment.

Depending on the application, and given the process nodes in use, most emphasis so far has been on reduction of dynamic power. Aggressive techniques including multi-supply voltages, and dynamic voltage and frequency scaling are commonplace. But with the move to 65nm and beyond, and especially if the application involves extended idle periods, controlling leakage is becoming more important and power gating is starting to be more widely deployed. While the complexity of power architectures may not seem to be as great as the latest mobile multimedia platform, nonetheless it's introducing multiple power domains and multiple power modes on top of the existing complexities of mixed signal design.

This is critical, especially since verification complexity increases exponentially with complexity of the power architecture, and mixed-signal verification is already considerably more challenging than digital verification. Why? Continuous waveforms simulate slower than discrete, and techniques from the digital world like formal verification and hardware acceleration are almost impossible to apply, if the conventional mixed-signal verification methodology continues.

So, many customers were interested in recent developments at Cadence that bring our mixed-signal and low-power solutions closer together. This inlcudes capabilities like power-aware mixed signal simulation with real number modeling (i.e. wreal). Here, signals crossing the analog and digital domains are not just modeled abstractly for speed, but electrical-to-logical and logical-to-electrical conversion is power-aware, meaning all the logic states and their equivalent voltages are derived automatically from the Common Power Format (CPF) file. Also important is the ability to generate CPF from the analog circuitry in the Virtuoso schematic view, which makes a block that would be functionally a "black box" in digital formal verification tools like Conformal Low Power, look like a "white box" from the power intent point of view, enabling rigorous chip-level functional and structural checks of the integrated design's power intent. Mixed-signal and low-power design challenges seem daunting enough individually, but we're really starting to see what happens when they coincide. And hopefully, we're doing something useful about it.

Pete Hardee

What’s Cool for Low-Power at DAC?

Pete Hardee — Thu, 31 May 2012 01:29:00 GMT

Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's booth #1930. Here is a quick guide to presentations, demos and other events Cadence is involved with for low-power, as well as the latest updates on tools and flows support.

1. Luncheon on Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs. Time: Tuesday June 5^th. 12:00PM - 1:00PM (doors open and food is served at 11:30 AM). Location: 270-276 (Moscone Convention Center). Register here.

2. Three exciting customer presentations on low-power design in the Cadence EDA360 Theater at Booth 1930:

o   Marvell on accelerating low-power implementation using CPF, Monday June 4^th at 12:30PM
o   Maxim on designing their ADCs with the Cadence low-power/mixed signal flow, Monday June 4^th at 3:00PM
o   Broadcom on a designer's perspective on power formats, Tuesday June 5^th at 4:30PM

3. A demo of applying the latest mixed-signal verification methodology on a mixed-signal design using Cortex-M0 in ultra low power application. Time: Monday June 4^th - Wednesday June 6^th. Location: ARM Booth #1414, #802.

4. Cadence booth demo pods - Monday June 4^th - Wednesday June 6^th 9:00AM-6:00PM, at Booth #1930:

o Low-Power Verification in Mixed-Signal Design
o Incisive Low-Power Verification with UVM SystemVerilog and e

5. Optimizing Power, Reducing Energy, and Meeting Schedule using an Advanced Low-Power Solution. Time: Monday Jun 4^th 5:00PM-6:00PM, Tuesday June 5^th 10:00AM-11:00AM, Wednesday June 6^th 3:00PM-4:00PM. Location Cadence Demo Suite #2 at Booth 1930.

6. Meeting Power Targets using a Digital Front-End Design and Verification Solution. Time: Monday June 4^th 9:00AM-10:00AM, Tuesday June 5^th 1:00PM-2:00PM. Location Cadence Demo Suite #3 at Booth 1930.

7. Implementing Low-Power and High-Performance ARM® Cortex^TM Processor-Based SoCs. Time: Monday Jun 4^th 11:00AM-1:00PM, Tuesday June 5^th 2:00PM-4:00PM, Wednesday June 6^th 11:00AM-1:00PM. Location Cadence Demo Suite #3 at Booth 1930.

8. Achieving Faster Timing and Power Closure using an Advanced Digital Signoff Analysis Solution. Time: Monday June 4^th 3:00PM-4:00PM, Tuesday June 5^th 10:00AM-11:00AM, Wednesday June 6^th 11:00AM-1:00PM. Location Cadence Demo Suite #3 at Booth 1930.

9. Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs. Time: Monday June 4^th 3:00PM-4:00PM, Wednesday June 6^th 4:00PM-5:00PM. Location Cadence Demo Suite #2 & #3 at Booth 1930.

Not forgetting of course the Denali Party by Cadence. See you at DAC!

Pete Hardee

Low-Power Design? Brian Bailey Gets It

Pete Hardee — Wed, 02 May 2012 20:23:00 GMT

Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he put it: "I doubt if the EDA Designline, or in fact any Designline in the history of EE Times has ever had anything close to the concentration of design articles, opinions, book excerpts that I will be putting up this month - and all of them will be on the subject of power." And I agree.

Contributions have come predominantly from EDA, and from pretty much all the players with any kind of power analysis, verification or optimization offering. There's good stuff from a lot of different companies, but since this is a Cadence blog, I make no apologies for highlighting the Cadence content here.

In his opinion piece What Comes After Power Formats, Qi Wang elaborates on future developments we may see after the current focus on design automation for today's advanced low-power techniques. He touches on system level and software, novel clock tree methods, mixed-signal designs especially digitally-assisted analog, future process technologies, and 3D-IC.
Next up, Buda Leung and I wrote a detailed case study of power analysis in Building predictability into your low-power design flow. We looked at the power savings achieved with multi-supply voltage domains, power shut-off, and multi-voltage threshold techniques, showing that RTL power estimation gets you early feedback on the benefit of these techniques, and could get pretty good correlation to sign-off analysis provided you use realistic activity vectors. We deservedly credited Paul Weil, John Decker and Mickey Rodriguez for the design work they did that made the article possible.
Another major design article came from Luke Lang, who contributed Hierarchical methods for power intent specification. This article takes a comprehensive look at power intent specification for hierarchical designs, giving an in-depth "how to" on both top-down and bottom-up techniques, and pointing out that real-world design of any complexity is invariably a combination of both. Somewhere in the EDA Designline series, you can find an article on hierarchy management in UPF. Compare the two, and see which one makes more sense to you for real design. Maybe you will see why we're putting a lot of effort into driving methodology convergence with IEEE 1801 with broad industry backing, which is more fully explained in another EE Times article, co-written by ARM, Cadence, Qualcomm and TI, called Power Intent Formats: Light at the End of the Tunnel?
In Brian's editorial Power 107: Power Delivery Networks, Brad Griffin is quoted extolling the benefits of full chip-package-board PDN modeling solutions.
Finally, in Brian's latest editorial Power 108: Powering forward, I make some future predictions for 3 years and 10 years out. It's always difficult to know how far out on a limb to go on that kind of question, but all I ask is that, before you ridicule my predictions, let's see yours! However, I did note with a chuckle that, out of a list of 7 items predicted by a competitor for 10 years out, I believe Cadence customers already benefit today from 6 of them, with the remaining one on the roadmap slated for a release considerably sooner than a decade! Brian quite rightly pointed out that, 10 years out, you have to think a little outside the box.

Pete Hardee

Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!

Pete Hardee — Thu, 08 Mar 2012 05:22:00 GMT

CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. This year's theme is Connect, Share and Inspire.

There's a particularly strong showing this year for low power designs and techniques, with many user papers in Track 2, a shared track featuring Low Power and Mixed Signal. Track 2 low power papers are:

9:00 Tuesday: A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP; Rambus Inc.
9:00 Wednesday: Conformal Low Power - Complex Low Power Design Verification; Qualcomm Inc.
10:00 Wednesday: Low Power Implementation on Freescale Kinetis Family; Freescale
11:00 Wednesday: Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification; Cadence

Those interested in mixed signal designs will benefit by staying with Track 2 for the duration, while for those interested in low power design and power optimization for purely digital designs could check out my personal picks from these other tracks:

Track 8 - High Performance

1:30 Tuesday: Being Green - what Good Design and ccopt (formerly Azuro) can do to Reduce Power; Netronome Systems Inc.
2:30 Tuesday: Mali-T604 Embedded General Purpose Computing for GPU implementation in CMOS32LP using Cadence Reference Methodology; ARM
3:45 Tuesday: Implementation strategies for a high performance and low-power ARM® Cortex^TM-A15 processor: Methodology and tools usage best practices; Texas Instruments
4:45 Tuesday: Improving Performance, Power and Area of a High Speed Dual-core ARM Cortex-A9 Processor with Clock Concurrent Optimization Technology; Broadcom

Track 4 - Verification

3:45 Wednesday: Techtorial: Low Power Failures - What not to Plan; Cadence
4:45 Wednesday: Low-power Verification using UVM SystemVerilog; Cadence

Of course, don't miss the keynote speeches from executives from ARM, TSMC and Cadence on Tuesday morning, and the Partner Expo on Tuesday evening. Go to CDNLive SV 2012 for more information.

See you there next week!

Pete Hardee

Does Substrate Biasing Have a Future?

Pete Hardee — Mon, 06 Feb 2012 23:06:00 GMT

At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more widely as many designs, and by no means only mobile designs, become increasingly power-sensitive. But while many advanced techniques (which we take to be the ones applied to power domains, such as power shut-off, as opposed to well-established optimizations like clock gating) are clearly growing rapidly in adoption, some less well-known techniques only seem to find favor with a few, and it's less clear whether adoption is increasing.

In particular, it's widely believed that substrate biasing (AKA body biasing) gives a lesser return in more advanced process nodes (45/40, 32/28 and beyond). What's the latest we're hearing about this?

First the stats...

When we delivered live full-day low-power "Tech on Tour" symposiums around the world in late 2010 and early 2011, we met with over 500 designers interested in low power design. That gave us a great opportunity to survey them. Here's what we found for the adoption of low power technqiues: Biasing is currently used by 5% of our sample of designers, and expected near-future use is 17%. In comparison, for power shut-off, we found the technique in use by 51% currently and 68% in the near future. That would certainly imply the technique's adoption is growing.

Now the anecdotal evidence...

Here's what has been heard by a few of our low power experts worldwide when discussing biasing with customers:

The top two reasons against using substrate biasing are bias supply routing congestion (which increases at more advanced nodes); and difficulty of generating all the bias supplies.
Mobile device SoC's at advanced nodes need all the low-power techniques at the designer's disposal, including biasing, according to one major mobile SoC platform provider. Another provider sees their ability to widely-apply substrate biasing in their libraries and process as a significant differentiator.
Some customers who do not apply biasing to the whole chip below 45/40nm instead apply the technique in conjunction with low voltage standby modes, especially in memories.
At least one customer who used biasing successfully in a 90nm chip is applying biasing successfully to their next generation at 45nm, while another company using forward and reverse biasing in volume at 90nm struggled to meet timing in the next generation at 65nm.

Future of substrate biasing:

Substrate biasing is useful primarily to control leakage at near-threshold voltage in planar CMOS. When FinFET becomes the norm (already used in some 22/20nm processes and will become commonplace for the 14nm node), leakage is better controlled by the gate's 3-D topology and many experts believe use of substrate biasing is unlikely to offer further benefit.

Current support for substrate biasing in the Cadence Low-Power Solution:

Regardless of whether you believe substrate biasing is worth the effort, be assured that the technique is fully supported in Encounter Digital Implementation System and Conformal Low Power. However, please ensure it is also supported by your library provider and foundry.

If you have any experiences to share about substrate biasing or any thoughts on its future, we'd be happy to hear them!

Pete Hardee