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Mixed Signal Technology Summit Proceedings Now Available

nizic — Thu, 13 Dec 2012 15:39:00 GMT

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees used the opportunity to ask questions, share experiences and network.

Dr. Chi-Ping Hsu, Cadence Senior Vice president of R&D, welcomed the participants and opened the event. He pointed to Cadence's strong investment and leadership in mixed-signal solutions.

Prof. Ali Niknejad of the University of California at Berkeley delivered an inspiring academic keynote "Pushing the Frontiers of Silicon: Digital RF, mm-Wave, and THz Communication and Imaging." He shared with the audience his research on RF circuit design and silicon implementation for energy efficient, wider bandwidth communication in the 60 GHz frequency range. In second part of his keynote, he discussed design challenges and techniques for silicon-based, reflection-sensing radar imaging, which could potentially replace today's expensive X-ray Computed Tomography (CT) scanners with much less costly solutions for medical imaging and diagnosis.

Chris Collins, Director of Analog EDA and Design Services at Texas Instruments delivered the industry keynote "Tribulations of Combining Analog and Digital Design." In a very entertaining way, Chris shared some of his experiences in deploying an advanced, productive and scalable flow for mixed-signal design. He stressed the importance of a close relationship and collaboration with Cadence for the success of his projects.

Dr. Monte Mar of Boeing Corp. talked about statistical behavioral modeling for sensitivity analysis of analog circuits in order to make feasibility tradeoffs, and choose more suitable circuit topologies and specifications for practical implementation in a top-down design methodology.

Frank Nothaft and Nishant Shah from Broadcom presented a methodology for validating and maintaining a portfolio of AMS IP behavioral models used in SoC verification. They particularly focused on a high level of automation for checking the equivalency of models with their corresponding circuits through efficient regressions.

Prashanth Aprameyan from Micron Technology focused on a comprehensive mixed-signal verification solution for NAND memory using SPICE/fast-SPICE simulation for verifying performance and IR drop impact, and complementing it with "wreal" type Real Number Modeling for full chip functional verification.

Tim Guglielmo and Subodh Reddy from Maxim Integrated shared their findings on the Schematic Model Generation (SMG) tool they evaluated in early partnership program with Cadence. The tool makes it easier for analog designers to create and verify behavioral models using a schematic environment, rather than writing them in a text editor.

Dinraj Shetty and Joaquin Bartra from Spansion talked about their physical implementation flow. Interoperable on OpenAccess, the flow enables analog and digital layout designers to share and refine floorplans with pre-routes done by a custom router which are honored by digital physical synthesis. Designers can easily take the design back to a custom platform for chip assembly.

Mahesh Tirupattur from Analog Bits, and Kumar Keshavan from Sigrity which is now part of Cadence, jointly presented on IBIS algorithmic modeling (IBIS-AMI) for effective channel simulation, applied to 10 Gbps SerDes.

Jim McCanny and Ben Farhat from Cadence discussed the increased importance of static timing analysis for mixed-signal designs, and presented a methodology for characterizing timing of custom circuits and full chip timing analysis using a glass-box (instead of black box) approach.

I had the pleasure of teaming up with Dominic Pajak from ARM to present on Cortex^TM-M processor benefits for mixed-signal applications, and simulation flow for hardware/software verification.

Presentations and videos from the summit are now available for viewing. Please visit http://www.cadence.com/cadence/events/Pages/Mixed_Signal_Technology_Summit_Proceedings.aspx, or click on the link for particular session of interest, below. A Cadence Community log-in is required - quick and free registration if you don't have one.

Mladen Nizic

Topic	Speaker	Proceedings
Academic Keynote - Pushing the Frontiers of Silicon: Digital RF, mm-Wave and Terahertz Communication and Imaging	Prof. Ali Niknejad, University of California at Berkeley	View presentation View video
Cadence Mixed-Signal Solution Update	Mladen Nizic, Cadence	View presentation View video
Using Statistical Behavioral Models in Top - Down Analog Circuit Design	Monte F. Mar, Ph.D. Boeing	View presentation
MS Verification & RNM Modeling – NAND Memory Perspective	Prashanth Aprameyan, Micron	View presentation View video
ARM Cortex - M0 System Simulation Using RNM	Dominic Pajak, ARM and Mladen Nizic, Cadence	View presentation View video
Schematic-Based Behavioral Model Generation	Tim Guglielmo and Subodh Reddy, Maxim	View presentation
Static Timing Modeling and Analysis in Mixed-Signal Design	Jim McCanny and Ben Farhat, Cadence	View presentation View video
OA-Based Concurrent Mixed-Signal Implementation Flow	Dinraj Shetty and Joaquin Bartra Spansion	View presentation View video
IBIS - AMI Modeling for High-Speed I/O	Mahesh Tirupattur, Analog Bits and Kumar Keshavan, Cadence	View presentation View video

How to Design Analog/Mixed Signal (AMS) at 28nm

nizic — Tue, 21 Jun 2011 20:00:00 GMT

Wireless, networking, storage, computing and FPGA applications have been moving aggressively to advanced process nodes to take advantage of lower power consumption, improved performance and area reduction. Today, most of these applications integrate a significant amount of analog/mixed signal (AMS) or RF together with digital circuits. Since AMS often occupies over 50% of the chip area, applying traditional, conservative approaches when migrating to an advanced node diminishes and possibly eliminates these benefits.

Due to significant changes in physical effects and device performance, a simple migration to next node is not practical. AMS circuits need to be optimized and often completely redesigned to meet performance specs. This requires design companies to have an AMS IP flow fully ready at the same time as, or even earlier than, the digital flow in order to realize silicon at advanced process nodes.

A survey of 561 predominantly analog and mixed-signal designers and CAD engineers from over 150 companies, collected during Cadence worldwide Mixed-Signal Seminars in March 2011, confirmed that 65nm has became mainstream for mixed-signal. The survey also showed strong AMS design activity at 40 and 28nm.

Figure 1 - Analog/mixed-signal designers look to lower process nodes

Challenges of Advanced Process Nodes

Designing AMS chips at advanced nodes increases some of existing challenges and brings new challenges. The main challenges include parametric variation, device reliability, layout dependent effects (LDE) and overall design productivity.

Traditionally, designers analyze the impact of parametric variations and use more robust circuit topologies and statistical circuit optimization techniques to center designs to meet specifications with acceptable yield. Advanced node analog circuits increasingly require self-calibration to cope with increased parametric variation and process drift. Self-calibration typically involves digital logic implemented tightly with analog circuits, requiring a mixed-signal flow instead of pure analog design flow.

At advanced nodes, devices are more susceptible to effects like Time Dependent Dielectric Breakdown (TDDB), Hot Carrier Aging (HCA) and Negative Bias Temperature Instability (NBTI). Any of these can cause device failure, particularly if over-voltage conditions persist over longer periods. Therefore it is very important to identify devices with over-voltage conditions across all modes of operation and perform reliability analysis early in the design phase.

Due to LDE, device current and threshold voltage vary depending on the surrounding layout. This is mainly caused by well proximity and stress effects, and variation could be 10% or even more. To avoid late layout re-work and schedule delays, it is important to understand impact of LDE on circuit performance, identify the most sensitive devices, and implement them in silicon with special care keeping variation within acceptable tolerances.

Increased challenges require a higher level of design automation to keep up design productivity at advanced process nodes. Accurately predicting circuit performance in pre-layout stages, analyzing sensitivity and identifying the most critical devices, capturing design intent, communicating intent as a constraint to layout designers, and giving designers the means to construct layouts correctly are all becoming mandatory.

TSMC AMS Reference Flow

Through the AMS reference flow initiative, Cadence and TSMC are closely collaborating in addressing challenges of AMS design for the 28nm process. As result of this collaboration, AMS v1.0 was released last year, followed by AMS v2.0 released earlier this month. AMS v2.0 adds key features including LDE-aware layout, advanced Monte Carlo Analysis, device reliability analysis, Analog Base Sub-circuits (ABS) optimization and Multi Technology Simulation (MTS) for 3D-IC/package integration.

Figure 2 - Cadence track in TSMC AMS v2.0 Reference Flow

In AMS v2.0, the LDE calculation engine is tightly integrated in the Virtuoso environment to provide almost instantaneous feedback to layout designers on the quality of device placement through comparison of Vth and Id_sat variations of the particular device against specified constraints. The high yield estimation in Virtuoso-ADE using the Worst-Case Distance (WCD) method is validated to estimate yield within 1% accuracy, with 200 parameter samples as compared to a traditional 10,000 random sample analysis.

Assertions in Spectre/APS set in the Virtuoso-ADE environment are used to detect over-voltage conditions that can lead to device reliability problems. Circuit optimization capabilities in Virtuoso-ADE-XGL are validated for retargeting a generic ABS cell to a specific 28nm technology that meets given specifications. Additionally, a flow with Allegro SiP Architect and Virtuoso AMS-Designer was qualified for analysis of 3D-IC integration, leveraging ther Multi Technology Simulation (MTS) supported by Spectre.

Building on TSMC AMS v1.0 foundation in AMS v2.0, Cadence has delivered another strong set of capabilities for much more productive and predictable AMS design at 28nm. For further information on the TSMC AMS reference flow please contact me, your TSMC or Cadence representative.

Mladen Nizic

Advanced Mixed-Signal Designs Demand a Unified Methodology

nizic — Mon, 07 Feb 2011 05:00:00 GMT

Mobile, automotive, consumer and medical applications require the productive realization of large and complex mixed-signal systems in silicon, and they must be on time and within budget constraints. Process capabilities make it possible to implement analog and RF circuits in CMOS technology at advanced nodes, and to integrate analog and digital functionality at the system-on-chip (SoC) level. However, mixed-signal SoC design is not without challenges, including the functional and performance verification of complex designs, concurrent analog and digital block/IP physical implementation, analog-digital physical integration, and signoff.

To address these challenges, next-generation mixed-signal solutions must enable unified design intent, abstraction and convergence throughout the design flow. These three capabilities are requirements of Silicon Realization, which is part of the EDA360 vision.

Capturing, Communicating and Verifying Intent

Today's mixed-signal designs are realized through collaborations of multiple teams spread across the world, performing different design tasks. Disjoint design environments and informal communications among designers often result in loss of productivity due to data conversions, increased design iterations, and error-caused ECOs. For example, if a designer implementing a block misses an e-mail message from a top-level integrator telling him that a particular clock net needs to be shielded, just before tapeout (or even worse after) the team might find out that the design does not function at the specified frequency due to crosstalk, costing them valuable time and resources to fix.

To avoid this kind of problem, the flow needs to capture the design intent (such as a shielding requirement), share it across different design tasks and teams, and verify that it is met before taping out. In the Cadence mixed signal solution this is achieved by using the common OpenAccess database not only for the smooth exchange of design data, but also for conveying intent in the form of design constraints across analog and digital domains.

Mixed-signal chips are increasingly power sensitive, and low-power design methodologies have to be applied throughout the mixed-signal design flow. Low power techniques like multi-threshold voltage, multi-power domains and power shut-off are increasingly used for minimizing the power consumption of mixed-signal blocks. SoCs often contain many mixed-signal blocks, and verifying power intent for the full chip using simulation is practically impossible due to the size of circuits and number of modes that need to be verified.

In its mixed-signal solution offering, Cadence leverages the CPF (Common Power Format) to capture power intent for a mixed-signal block, and then abstracts it to a level suitable for much more efficient formal (static) full chip verification, using the industry de-facto power structural sign-off tool Conformal Low Power. This methodology is much more productive in capturing functional and electrical bugs without requiring test-benches, increases coverage in much shorter verification cycle, and helps avoid costly silicon re-spins.

Abstracting for Efficiency

Continuous advancements in simulation speed and capacity are absolutely necessary, but are not enough to address verification challenges for complex mixed-signal SoCs. We have seen from many publicly known examples (including some very recent ones) that bugs missed in verification can cost company tens and even hundreds millions of dollars.

Model-based, metric driven verification methodologies need to be extended to analog and mixed-signal verification to improve the verification quality and productivity. In addition, Cadence has enhanced support for real number models in Verilog-AMS to enable more efficient abstraction of analog and mixed-signal functionality for inclusion into full chip, digital-centric, metric driven verification without sacrificing performance.

Driving Convergence

A traditional black-box methodology with sequential design tasks is inadequate for advanced mixed-signal designs, and leads to numerous iterations with slow or no design closure. Design convergence starts with the right chip architecture and optimal floorplan in terms of performance, area, power, noise and package cost. This can only be achieved through close collaboration among analog, digital and package designers.

The Cadence mixed-signal solution offers advanced chip floorplanning capabilities to facilitate cross-domain collaboration, enabling designers to explore different alternatives and choose the one with the best path to design closure. For example, designers can tune the initial floorplan using automated timing and congestion driven criteria while keeping sensitive analog objects at pre-set locations, quickly estimate and adjust the area for a block, and optimize pin locations of a block by considering both block and top-level routing requirements.

Integrated signoff analysis is another critical element for design convergence. Cadence offers advanced timing signoff analysis for the mixed-signal SoCs, breaking the limitation of the traditional black-box (.lib) model. The new methodology traverses the hierarchy of mixed-signal blocks and performs timing and SI analysis on critical paths spanning through top level and multiple mixed-signal blocks. Fully automated and joined with user-friendly debug capabilities, this enables designers to converge on the design spec and achieve fast, silicon correlated signoff.

By unifying mixed-signal methodology around design intent, abstraction and convergence, the Cadence solution increases design productivity and predictability and addresses mixed-signal SoC design challenges, enabling customers to improve profitability and competitiveness in the marketplace.

Cadence outlined EDA360 industry vision with Silicon, SoC and System Realization as its three pillars. Mixed-signal is integral part of EDA360 and is at the core of Silicon Realization. The unified mixed-signal methodology is a practical example of transforming the vision into reality. Cadence is presenting details of the unified mixed-signal methodology and showing how it is implemented in our mixed-signal solution in full day seminars to be held at 15 locations around the world. A detailed agenda and event registration is available at https://www.cadence.com/cadence/events/Pages/event.aspx?eventid=502

Mladen Nizic

ARM And Cadence Get To The “Core” Of Mixed-Signal Design

nizic — Wed, 09 Jun 2010 01:00:00 GMT

An increasing number of analog and mixed-signal designs in automotive, power management, wireless, medical, and industrial applications require digital control. But designing a state machine, and integrating the increasing amount of logic gates that implements it, has been challenging for analog designers. They often start implementing some digital functionality using a custom methodology, but soon the growing gate count becomes overwhelming and requires digital skills.

Analog designers then find they need a more complete digital flow for the digital block design. This flow must work smoothly in conjunction with an analog-centric flow for top-level design and full-chip integration. The increasing size of digital logic requires formal verification, test insertion, and automation for low power techniques. The amount of digital logic might increase to the point that a digital-centric methodology is more suitable for full-chip integration, with analog functionality designed separately and integrated as black boxes.

Integrating a core processor within analog and mixed-signal designs is an attractive alternative for digital control. The processor architecture offers a high level of flexibility through programmability and scalability, thus realizing more advanced designs and meeting more complex specs. The benefits outweigh an initial investment in architectural development and a design methodology shift.

Cortex-M0 Targets Mixed-Signal Applications

ARM recently released the Cortex-M0 processor core targeting mixed-signal applications. It has a 32-bit architecture, compact instruction set, very small silicon footprint (base configuration is just about 12K gates) and is power efficient. In a typical application it is accompanied by a memory block, memory bus interface, peripheral interfaces (GPIO, I²C, UART, SPI, USB) and standard analog/mixed-signal IP (PLL, ADC, DAC). As such it is suitable for integration within analog sensors, RF transceivers, power regulators, LED drivers, barcode scanners, motor controllers, or similar applications.

At the end of last month, ARM organized a Cortex-M0 workshop in Paris, France, and invited Cadence to present design solutions. Judging by number of attendees and their strong interest, the future of analog and mixed-signal design lies in its integration with processor cores. Almost thirty companies from the region came to learn how to design mixed-signal applications with the Cortex-M0 processor core.

The Cadence mixed-signal solution spans different design styles and supports diverse applications while leveraging common technologies. For example, verification of the mixed-signal designs with embedded Cortex-M0 core can be done from either the schematic driven Virtuoso-ADE environment or the command-driven Incisive environment. Both use the same high performance, tightly integrated simulation engines including those for SPICE, RF, behavioral, RTL and gate-level simulation. This ensures consistency of results while analog and digital designers work in their preferred use models.

Similarly, physical implementation and signoff for analog-centric designs is done in Virtuoso for the high level of control required in crafting analog circuits, with a seamless integration to the Encounter Digital Implementation System for digital block implementation. If a design requires a digital-centric environment, Encounter offers the full strength of digital design automation and low power design techniques, with the ability to integrate analog blocks previously done in Virtuoso as hard macros. Both analog and digital centric design environments leverage Virtuoso-Encounter interoperability based on industry standard OpenAccess (OA) for sharing design data and constraints. The implementation solution extends to IC/package co-design through Virtuoso and an interoperable flow with the Allegro package and board design environment.

Bringing Digital Capabilities to Analog Designers

Many analog/mixed-signal design teams are facing the need for digital design capabilities for the first time. They might be intimidated by complexity and price of digital design tools they need to apply for a relatively small logic gate count, as compared to mainstream digital. Cadence has conveniently packaged digital capabilities for Virtuoso users who need a digital solution for limited-size digital block implementation.

The Virtuoso Digital Implementation package contains logic synthesis, placement, clock tree synthesis, timing optimization, routing, extraction and static timing analysis. This is the same Encounter technology but is limited to 50K instances, sufficient for most mixed-signal designs with Cortex-M0. Moreover, two Virtuoso Digital Implementation licenses can be combined to double the capacity, and there's a smooth path to the full Encounter configuration if digital design needs increase.

In addition to flows, Cadence offers highly experienced mixed-signal methodology and design services, and a complete ecosystem from IP providers to foundries.

With Cortex-M0, ARM has offered a simple but powerful processor core for mixed-signal applications. The Cadence mixed-signal solution enables designers to smoothly realize designs in silicon, with high design productivity, schedule predictability and project profitability. Offerings from both companies lower the barrier for adoption of processor cores in analog and mixed-signal applications, and I believe many designers will take advantage of them.

Note: The ARM workshop in Paris was first in serious of similar workshops. The next one is planned for middle of July in Zurich. Please contact your local ARM or Cadence representative for this or possible future workshop in your region.

Mladen Nizic