https://community.cadence.com/search?q=*%3A*&category=blog&users=147116&sort=date%20desc&Redirected=trueen-USTelligent Community 12https://community.cadence.com/cadence_blogs_8/b/cic/posts/start-your-engines-optimizing-mixed-signal-simulation-efficiencyWed, 05 Jun 2024 20:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1363055Qingyu Lin/cadence_blogs_8/b/cic/posts/start-your-engines-optimizing-mixed-signal-simulation-efficiency0Cadence Spectre AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines blog series will provide you with tips and insights to help you tune your simulation performance and accelerate down the road to productivity. In a traditional mixed-signal circuit design and simulation, the mixed-signal design comprises analog and digital design blocks. When running a simulation, analog and digital engines run simultaneously from the beginning to the end, with signals synchronized on the boundary. During the simulation, the analog engine usually dominates the simulation time and resources. If you need to run multiple tests of the same circuit with different stimuli or test patterns, then you need to run the simulation multiple times. Spectre AMS Designer provides two advanced technologies to help you improve the efficiency of your mixed-signal designs and increase the simulation speed. The first method is turning off the analog engine. This feature allows designers to turn the analog engine on or off in a mixed-signal simulation for a time window when the analog circuit function is not necessary during simulation. Turning off the analog engine can significantly speed up the simulation time when only the digital engine is running. In Spectre AMS Designer, there are both TCL commands and system tasks for designers to control when to turn the analog engine on or off. System tasks can be placed in a testbench and conditionally controlled by design signals. This is an easy-use model and gives the most flexibility. The second method uses the Process-Based Save Restart (PBSR) flow, which lets you save a snapshot of your design at a certain time point and then allows multiple users to load the same snapshot. This snapshot can be run with different stimuli or test vectors. Reusing the same initial stage of the design can reduce a lot of redundant costs of time and resources for simulations. Spectre AMS Designer also provides multiple TCL commands to let the design force or release both analog and digital node values and to change simulation parameters. Using these commands and the testbench behavior, a designer can run multi-test simulations without repeating the initialization for every run. To learn more about these methods, please refer to the latest version of the Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide or contact your Cadence Customer Support team. Related Resources Product Manual Spectre AMS Designer and Xcelium Mixed-Signal User Guide Troubleshooting Information Spectre AMS Designer For more information on Cadence circuit design products and services, visit www.cadence.com . About Start Your Engines The Start Your Engines series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box. - Qingyu Linhttps://community.cadence.com/cadence_blogs_8/b/cic/posts/start-your-engines-use-tcl-commands-to-save-signals-more-efficiently-in-mixed-signal-simulationsTue, 12 Sep 2023 21:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1360575Qingyu Lin/cadence_blogs_8/b/cic/posts/start-your-engines-use-tcl-commands-to-save-signals-more-efficiently-in-mixed-signal-simulations0Cadence Spectre AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune your simulation performance and accelerate down the road to productivity. Saving signal waveforms during a simulation is one of the basic ways to check the simulation results. However, with large SoC designs, it’s not always practical to save all signals during simulation, and the simulation performance might also be impacted by the number of signals being saved. Therefore, a crucial part of the simulation setup is to specify the expected and essential signals to save. Here are some examples of using TCL commands to save signals more efficiently: Saving a single signal Save the voltage of net3 in the hierarchy i1.i2 . probe -create top.i1.i2.net3 Save the current through port portA in the hierarchy i1.i2 . probe -create -flow top.i1.i2.portA Saving multiple signals in an instance Save the voltages of all ports and nets in instance i2 in hierarchy i1 . probe -create -noaicms top.i1.i2 Save the currents of all ports of instance i2 in the hierarchy i1 . probe -create -noaicms -flow -ports top.i1.i2 Saving selected signals in an instance Using the -depth option, save the voltages of all ports and nets in instance i1 , one level down the hierarchy. probe -create -noaicms -depth 2 top.i1 Using the -ports option, save all currents through the ports of instance i1 , one level down the hierarchy. probe -create -noaicms -depth 2 -flow -ports top.i1 Saving selected signals in a module with multiple instances (applicable for analog scope in Verilog-AMS format) Using with find command, save the voltages of all ports with the suffix out in the scope i1 , one level down the hierarchy. probe -create -noaicms [find -rec 1 -scope top.i1 -ports *out] For more advanced usage, save the voltages of all ports with the suffix out that exist in instances whose names begin with i, in the current scope, one level down the hierarchy. set inst_scope [find -instances -rec 1 -absolute -newline i*] foreach {inst} $inst_scope { catch {probe -create -noaicms [find -scope $inst -ports *out]} } As shown in the later examples, by combining probe and find commands, you will be able to precisely select the signals you need to save so that there is no redundant data in your waveform database and minimal impact on simulation performance. Related Resources Product Manuals Xcelium Simulator Tcl Command Reference Spectre AMS Designer and Xcelium Mixed-Signal User Guide Troubleshooting Information Spectre AMS Designer For more information on Cadence circuit design products and services, visit www.cadence.com . About Start Your Engines The Start Your Engines series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.https://community.cadence.com/cadence_blogs_8/b/cic/posts/running-post-layout-mixed-signal-simulation-with-a-more-complex-configurationThu, 19 Jan 2023 09:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1360163Qingyu Lin/cadence_blogs_8/b/cic/posts/running-post-layout-mixed-signal-simulation-with-a-more-complex-configuration0Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity. In the current times, post-layout simulation has become more and more important in design verification, not only in pure transient simulation but also in EM/IR analysis and electrothermal analysis. Usually, designers run a post-layout mixed-signal simulation with a design block (DUT) using a schematic and the rest of the design or testbench using pre-layout schematic or digital functional blocks. However, with a more complex design structure and advanced design flow, people now try to run a post-layout mixed-signal simulation with a more complex configuration. One such example is a sandwich structure, where the DUT block is a DSPF file with a blackbox inside that needs to be replaced by a digital functional block. There are two advantages of running this type of configuration. Firstly, it will further speed up the mixed signal post-layout simulation. The traditional blackbox DSPF allows designers to use pre-layout schematic to replace the blackbox in DSPF, but it is still limited by the capability and performance of the analog solver. When using Verilog/Verilog-AMS/SystemVerilog blocks to replace the blackbox in DSPF, it will give more performance gain and allow a much larger scale of the design to simulate. Secondly, it will allow designers to run verification as early as possible. Usually, post-layout simulations are run at a very late stage of the design flow. However, with more and more IP reuse, designers want to put the physical constraint at an early stage of the design flow and check the brief placement and routing. In this case, the sub-block level may still be at the functional or even behavior level, but designers prefer to run the full design post-layout on the top level to get an early estimation. With the DSPF-in-the-middle feature available in Virtuoso ADE flow, designers can easily set up this type of configuration in the Hierarchy Editor (HED) and run a post-layout mixed-signal simulation with just a few clicks. Related Resources Product Manuals Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide Rapid Adoption Kits (RAKs) Using DSPF Blackboxes in AMS Simulations for Post-layout Verification Troubleshooting Information Spectre AMS Designer Product Page For more information on Cadence circuit design products and services, visit www.cadence.com . About Start Your Engines The Start Your Engines series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the subscription box. - Qingyu Linhttps://community.cadence.com/cadence_blogs_8/b/cic/posts/start-your-engines-modeling-current-based-port-connections-between-electrical-and-real-number-modeling-modulesThu, 03 Jun 2021 18:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1351518Qingyu Lin/cadence_blogs_8/b/cic/posts/start-your-engines-modeling-current-based-port-connections-between-electrical-and-real-number-modeling-modules0Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity. In a mixed-signal simulation, the electrical signal modules and real number modeling (RNM) modules mostly have voltage-based ports. However, there may be still a few ports that need to model the current flow. Given that the fundamental properties for an electrical signal are very different from that of a real signal, modeling current needs special attention. Let’s look at a simple example to get a better understanding. Consider that there are two blocks, one of them being a driver and the other a receiver, and a current-based port connected to them. Irrespective of whether you use a RNM or electrical module on either the driver or the receiver side, the goal of the mixed-signal boundary modeling is to make sure that it always represents the same circuit. There can be four combination scenarios as shown below: Figure 1: Using Real Number Modeling and Electrical Modules with a Current-based Port If all of these four scenarios are to model the same electrical circuit, the electrical and RNM can be switched without any issues. Now we need to assess whether to use a positive real number to represent the forward current flow or a negative real number to represent the forward current. The reason that we can’t use the electrical way to define the sign of the signal, like flow-in is positive and flow-out is negative, is that RNM doesn’t follow Kirchhoff’s Current Law (KCL). So, a positive number from a driver will be received as a positive number at the receiver. Therefore, the flow-in/flow-out definition doesn’t work with RNM—only the forward/backward works. Let’s review what happens if we use a positive real number signal to represent the forward current flow. The following image shows the sign of each signal in the example discussed above: Figure 2: Using a positive real number to represent the forward current flow Let me explain the series of events that take place in this flow: In the beginning, both the blocks use electrical modules . As the current flows forward, we can see a negative sign electrical current on the output port of the driver and a positive sign on the input port of the receiver. Then, we switch the driver to use the RNM module . An R2E connect module is inserted, which converts the positive real signal into a negative electrical signal. So, the negative electrical signal represents the forward current flowing to the receiver. Next, we switch both blocks to RNM . The positive real signal is assigned to a positive real signal at the receiver. At last, we use the electrical block for the driver and RNM for the receiver . An E2R connect module is inserted, which converts a positive electrical signal (because current flows into the connect module) to a positive real signal and then assigns it to the RNM receiver. Now, all four scenarios are compatible and represent the same Silicon circuit. We can also use a positive real number signal to represent the backward current flow. The analysis is similar: Figure 3 Using positive real number to represent backward current flow In either of the cases shown above, we can see one of the E2R/R2E will need to reverse the sign of the converted signal so that the entire modeling process is self-consistent. These two examples show how to model two current-based ports connection. You may think what happens if there are three or more ports? After a simple analysis, the conclusion is we can’t model all scenarios self-consistently because of the lack of KCL in RNM. For a current-based connection with multiple ports, we have to follow KCL: Two ports’ connection can be considered as a special case as we can use reversal of signs to mimic KCL: However, with three or more ports, the reverse methodology would not work: Another problem with multiple ports is that there may be multiple receivers. The current flow needs to distribute between them in the current-based modeling instead of all receivers getting the same value in the voltage-based modeling. To conclude, here are some guidelines to model the current with a real signal (wreal/SV-real): Modeling a current-based design block in wreal/SV-real depends on the relationship between the current flow direction and port direction definition. If defining a positive real signal value as representing the forward current flow direction, keep the following in mind while performing RNM modeling for the current-based port: For the input port, the flow-in is positive and flow-out is negative For the output port, flow-in is negative and flow-out is positive If defining a positive real signal value as representing the backward current flow direction, then a reversed conclusion is also self-consistent: For the input port, the flow-in is negative and flow-out is positive For the output port, the flow-in is positive and flow-out is negative ~Qingyu Lin Related Resources One-Stop Knowledge Resource for Mixed-Signal Verification Spectre AMS Designer Product Page Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide For more information on Cadence circuit design products and services, visit www.cadence.com . About Start Your Engines The Start Your Engines! series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in Spectre AMS Designer, tips for enhanced understanding of existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.https://community.cadence.com/cadence_blogs_8/b/cic/posts/start-your-engines-two-critical-components-of-low-power-mixed-signal-simulation-in-ams-designerThu, 22 Oct 2020 14:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1345912Qingyu Lin/cadence_blogs_8/b/cic/posts/start-your-engines-two-critical-components-of-low-power-mixed-signal-simulation-in-ams-designer0Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity. The low-power format, CPF/UPF/IEEE1801, has been very popular in the digital simulation world for over ten years. Nowadays, it is also commonly used in the mixed-signal simulations. Besides the key technologies, such as power shut off, dynamic domain voltage, isolation, level-shifter, etc., there are other two critical components for the low power mixed-signal simulations, power-aware connect modules and mixed-signal power network . What are these? Let me explain these with the help of figures. Power-Aware Connect Module This figure shows how a power-aware connect module ( L2E_LPS ) converts a power-aware digital signal into an analog signal. In a low-power mixed-signal simulation, the digital blocks (for example, here digital_A ) are usually defined in a power domain ( PD1 ) whose power supply voltage and status are described in a low-power format, such as IEEE1801 . In the IEEE1801 file shown in this example, two supply sources are described for this block, VDD1 and VDD2 . An implicit switch cell is also described in the file to switch between the two sources dynamically. The L2E_LPS connect module is aware of the dynamic switching so that the correct reference voltage is used to convert a logic signal to analog. For example, when logic 1’b1 is converted to analog, at the same time there will be a supply of 1.8V from VDD1 to digital_A . So, the logic 1’b1 will be converted to 1.8V. The next time when 1’b1 is converted again, but with a supply of 1.2V from VDD1 to digital_A , 1’b1 will be converted to 1.2V. Low-Power Mixed Signal Power Network This figure shows how a low-power mixed-signal power network works for a mixed-signal simulation. For a large System on a Chip (SoC) design, power intent and power network are usually defined and designed independent of the design configuration, and mostly in the low-power format like IEEE1801 . When the SoC is configurated in a mixed-signal scenario, the power network needs to connect natively with both, analog and digital supply sources, and should also be able to distribute the power to both analog and digital function blocks. For example, in the figure above, the Power_Supply module is an electrical modeling block, so the port is providing an electrical signal. This module needs to connect to the power network in the yellow box and then the power supply with the switch cell needs to distribute the power to both the analog_A and digital_B blocks. Not only a static value but the transient change of supply voltage should also be reflected in the supply port of analog_A and digital_B . In this case, a mixed-signal simulation can always run correctly no matter which blocks are configured in analog or digital. Combined with other low power features, power-aware connect modules and low power mixed-signal power network will help designers to efficiently establish the mixed-signal configuration with their low power specification. For detailed use model and examples, refer to the low power mixed-signal simulation RAK, Verification of the Power Intent of a Mixed Signal SoC . ~ Qingyu Lin Related Resources One-Stop Knowledge Resource for Mixed-Signal Verification Spectre AMS Designer Product Page For more information on Cadence circuit design products and services, visit www.cadence.com . About Start Your Engines The Start Your Engines! series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in Spectre AMS Designer, tips for enhanced understanding of existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.https://community.cadence.com/cadence_blogs_8/b/cic/posts/start-your-engines-the-why-and-how-of-generating-spectre-netlists-for-analog-blocks-using-unlThu, 21 May 2020 21:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1342518Qingyu Lin/cadence_blogs_8/b/cic/posts/start-your-engines-the-why-and-how-of-generating-spectre-netlists-for-analog-blocks-using-unl0Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity. Did you know that AMS Unified Netlister (UNL) provides a comprehensive netlisting and binding framework for the AMS Designer-Virtuoso use model? When you run a mixed-signal design simulation from Virtuoso, UNL generates a netlist text file from the Virtuoso database and sends it to the selected simulator to run the simulation. By default, UNL generates this netlist in the Verilog-AMS format, which provides the best compatibility for parameters and port connections. However, in certain scenarios, such as pure schematics leaf branch or post-layout, netlisting the analog blocks in the Spectre format results in a more efficient elaboration process. Let us go over a couple of typical scenarios where a mixed-signal simulation would give better results with netlist generated in the Spectre format. Scenario 1: Mixed-Signal Post-Layout Simulation Consider a mixed-signal design that has an extracted view as a part of an analog block. When such a design is netlisted using AMS UNL, it will generate a very large Verilog-AMS format netlist that contains all the parasitic capacitors and resistors. These capacitors and resistors go through Xcelium elaboration and are passed back to Spectre to solve. This results in significant elaboration time. Scenario 2: Big-A-Small-D Design Simulation Consider a design that predominantly contains analog components. Or for that matter a design, which has components mostly at the transistor level, only containing a negligible digital portion (possibly, a small stimuli block). In such cases, a netlist generated in the Spectre format will be beneficial as the Spectre format netlist will not need to go through the Xcelium elaboration process. Using UNL to Generate a Netlist in the Spectre Format UNL has a feature, Netlist using Spectre , using which you can specify whether you want to netlist the pure analog blocks in the Spectre format. When this feature is enabled, UNL generates Spectre format files that the Xcelium elaborator directly passes on to the analog solver. Figure 1: New UNL Netlist with the Spectre Flow The Netlist using Spectre feature can be enabled in the AMS Options form. Figure 2: Enabling Netlist using Spectre in AMS Options The Netlist using Spectre field has the following two options: Pure Analog Cellviews Extracted Views Note that neither of the options is enabled by default. When you select the Pure Analog Cellviews option, the branch having only schematic views in the design hierarchy will be netlisted in the Spectre format. On the other hand, if you enable Extracted Views , only the extracted view will be netlisted in the Spectre format. The following image illustrates how the Netlist using Spectre options work. Figure 3: Differences in the "Netlist using Spectre" Options On enabling either of the options and running UNL netlisting, the analog blocks will be netlisted in the pureAnalog.scs file instead of netlist.vams in the netlist directory. Then, pureAnalog.scs will be included in pureAnalogSrcfile.scs , and later included in spiceModels.scs . Following is an example : Figure 4: UNL Netlist Using Spectre As would be evident by now, using the Netlist using Spectre option saves your time and computer resources when you are working with a predominantly analog design. So, if you haven’t yet tried out this feature, try it and experience the benefits for yourself. Qingyu Lin Related Resources One-Stop Knowledge Resource for Mixed Signal Verification AMS Designer Product Page Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide For more information on Cadence circuit design products and services, visit www.cadence.com . About Start Your Engines The Start Your Engines! series would bring to you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.https://community.cadence.com/cadence_blogs_8/b/cic/posts/start-your-engines-spectre-for-ams-designer-in-xcelium-take-your-pickThu, 16 Apr 2020 22:16:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1342431Qingyu Lin/cadence_blogs_8/b/cic/posts/start-your-engines-spectre-for-ams-designer-in-xcelium-take-your-pick0Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity. In the first post of the Start Your Engines blog series, I wish to introduce you to a more efficient version of AMS Designer! Background... The classic mode of AMS Designer comes with a specific Spectre engine integrated with the Xcelium digital engine so that both the engines can run together to solve a mixed-signal circuit design. While the classic integration provided synchronized communication between the two engines resulting in high efficiency and performance, there was still some scope of improvement in this architecture, in terms of cutting down the delay in accessing enhancements in the Spectre engine for a certain version of Xcelium. When new features and enhancements were delivered into Spectre, the designers would need to upgrade both Spectre and Xcelium in order to access them. Upgrading the digital engine version solely to match the analog engine upgrade was a challenge to the design house tool management. Introducing AMSD Flex Mode For the benefit of our AMSD users, in Xcelium 20.03, the AMSD flex mode has been introduced. With this mode, you get the flexibility to choose the version of Spectre for a particular Xcelium release. You no longer have to wait for the hard-coded integration done at the software level. The flex mode provides you quick access to new features and enhancements (or even fixes) of Spectre. Figure 1: Concept of AMS Flex Mode The idea of the new architecture is to create a standardized interface for the connection between the analog and digital engines. The interface is independent of the version of Xcelium or Spectre. Therefore, any version of Xcelium (with flex support) will be able to connect to any version of Spectre (with flex support), to solve a mixed-signal circuit design. Figure 2: Combinations of Spectre and Xcelium The new AMSD flex architecture not only provides flexibility and efficiency but also provides better performance during simulation. Testing shows that the run time improved 20 percent on an average, using the exact same Spectre and Xcelium versions. The major enhancements in the AMSD flex mode include: New architecture of the mixed-signal synchronization mechanism Optimization of the interface elements Better multi-threaded support Many more new features from both analog and digital engines will be supported in the flex mode. The flex mode is the direction for AMS Designer's future developments! Related Resources One-Stop Knowledge Resource for Mixed Signal Verification AMS Designer Product Page For more information on Cadence circuit design products and services, visit www.cadence.com . About Start Your Engines The Start Your Engines series would bring to you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMSD, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box. Qingyu Linhttps://community.cadence.com/cadence_blogs_8/b/cic/posts/cpf-low-power-simulation-with-analog-and-mixed-signal-design-cpf-amsMon, 23 May 2011 11:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1277237Qingyu Lin/cadence_blogs_8/b/cic/posts/cpf-low-power-simulation-with-analog-and-mixed-signal-design-cpf-ams0We have been talking about low power simulation and the Common Power Format (CPF) for five or six years now. It’s become popular in most digital designs thanks to a mature methodology and design flow. However, more and more SoC designs are coming up with mixed-signal content. How will low power technologies and formats be used in mixed-signal design? For SoC design verification, we always involve an analog solver in our simulation, no matter whether you are using Verilog-AMS to model your design block, or changing a block configuration from the Verilog/VHDL level to its SPICE/Spectre counterpart. When an analog solver is used, it can leverage the low power intent expressed by CPF. Although CPF was defined for higher-level designs, it works with analog solvers just as with digital content. Fig. 1 CPF-AMS In Fig.1 I drafted a simple diagram to show a scenario in which you switch a module from the Verilog version to Verilog-AMS or SPICE (here it’s ana_B). When you do this, there are three concerns: 1. Whether the power intent described in CPF file is also available for the Verilog-AMS or SPICE module . “Power domain” is a similar concept in both digital or analog content. Whatever Verilog module or SPICE subcircuit that is used to describe a circuit block should be handled in the same way for all low power related properties with respect to CPF information. 2. Whether the analog module can behave correctly according to the power state that is changing from CPF. In digital logic, when we turn off a power domain, the signal in the power domain will be forced to an ‘X’ state. This means the function described in CPF is able to affect the internal signal that belongs to the power domain. In analog circuitry, we should do the same thing to the analog signal in a power domain, turning it off or changing its value according to the power state in the CPF file. 3. Whether the low power digital and analog modules are able to talk each other . Usually, in mixed-signal simulation, a Connect Module is placed on the analog to digital and digital to analog boundary. When CPF is specified in the design, the Connect Module should have the capability to not only convert signal values from the logic side to analog side, but also convert the correct CPF information from one signal to the other. In addition, where real number modeling (wreal) is used to represent voltage or current instead of electrical signals, similar issues also will need to be considered in wreal modules. Qingyu Lin