https://community.cadence.com/search?q=type%3Ablog%20-%22Chinese%20blog%22%20-%22Japanese%20blog%22%20-%22Taiwanese%20blog%22en-USTelligent Community 12en-usnoSearch results for 'type:blog -"Chinese blog" -"Japanese blog" -"Taiwanese blog"'https://community.cadence.com/cadence_blogs_8/b/di/posts/accelerate-design-signoff-with-the-updated-cadence-voltus-training-kitTue, 21 Jul 2026 03:44:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364254Vinod Khera/cadence_blogs_8/b/di/posts/accelerate-design-signoff-with-the-updated-cadence-voltus-training-kit0By Ronen Stilkol, Senior AE Architect As advanced-node and 3D-IC designs push higher performance into tighter power, thermal, and packaging constraints, engineers must understand how the die, package, board, activity profile, and implementation flow interact. In this environment, signoff success depends not only on powerful tools but also on a guided methodology that shows what to run, why it matters, how to debug issues, and how to apply proven flows to real designs. That is where the updated Cadence Voltus Training Kit comes in. The latest June 2026 release expands the kit from a training resource into a comprehensive methodology environment for power integrity and signal integrity(SI/PI) and signoff. With more than 170 ready-to-run Rapid Adoption Kits, updated documentation, make-based automation, design-review templates, and an early interactive assistant, the kit helps engineers ramp faster, run flows more consistently, and move from learning to signoff with greater confidence. The goal is straightforward: turn complex signoff methodology into a practical, guided path that engineers can learn, trust, and apply. Voltus Training Kit: A Methodology, Not Just a Collection of Examples The Voltus Training Kit is a Voltus PI/SI signoff methodology integrated into a CAD environment. It uses recommended Cadence PV scripts and settings, TSMC PVT tables, and Self-Heat guides, and it is tested with the latest Cadence tools release and the previous year’s release. The kit is designed for training, customer design, ramp-up and evaluation, QA, test-case creation, and proof-of-concept work for new technologies. A key design goal is accessibility. Users do not need prior knowledge to start. They download the kit from the Cadence ASK portal, untar it, set the environment, and use make commands to run simulations, read results, view scripts, open documentation, and check errors. This make-based structure helps users focus on the methodology rather than rebuilding scripts from scratch. The kit supports DP/XP and Common_UI/Legacy modes, with DP mode planned to become obsolete in a future release. It also includes integrated simulation guides, debug documents, design-review templates, and direct document links, so engineers can work in a complete, guided environment rather than searching through disconnected material. What Is New in the June 2026 Release The latest release focuses on two major engineering needs that repeatedly come up in customer and field discussions: die/package co-verification and faster access to methodology knowledge. Stronger Die/Package Co-verification One of the biggest updates is the expanded package and die-model flow. In practice, die and package teams often need to collaborate, but each side may not fully understand the other's data, extraction steps, or simulation expectations. The updated Voltus Training Kit helps bridge that gap by explaining both directions of co-verification: Package-to-die: generate a package model and use it in die simulation so the silicon-side analysis can account for the package effect. Die-to-package: create a die model from Voltus simulation data and provide it to the package design team so the package team can understand current consumption and plan the package more effectively. This is especially important because package-aware analysis is no longer an isolated activity. Power integrity depends on how the die, package, board, voltage regulator, and design activity interact. The updated kit gives engineers a guided way to understand those interactions and run the flow step by step. A More Complete Package SPA and Die-Model Workflow The package SPA section now covers package design using Allegro APD, package extraction using XtractIM, MCP (Mode Connection Protocol) use in Voltus package simulation, and PowerDC package IR simulation in Voltus. The updated package flow shows how to design, extract, and simulate a package using Cadence tools in both batch and GUI-oriented workflows. Die Model has also been enhanced with die-model transient simulation, die-model frequency simulation, RC and frequency text reporting, and SystemPI die-model simulation with the package model. This helps the silicon and package teams exchange the right information and analyze behavior across frequency-dependent model data. Interactive Assistant Bot The June 2026 release also introduces a first-draft Voltus Training Kit interactive assistant bot, launched with make BOT. The bot is designed to help users ask practical questions about the kit, for example, how to run a static simulation, how to access methodology information, how to review environment settings, or how to find guidance on thermal simulation. This is an early version and will be improved over time based on usage and feedback. The bot reflects a larger direction for the kit: using AI carefully and controllably to improve engineering productivity. In the latest development work, AI was used to help test and improve scripts, support documentation updates, generate question-and-answer coverage from the kit documentation, and assist with automation. The goal is not to replace engineering judgment; it is to help engineers find the right information faster, run flows more consistently, and spend more time solving design problems. A Systematic Signoff Methodology The Voltus Training Kit is built around a stage-by-stage signoff methodology for early detection of design power-grid weaknesses, higher failure coverage, and faster root-cause analysis. The recommended flow includes: Design and library input checks: identify missing vias, shorts, unconnected devices and wires, and library-input issues before they become expensive signoff problems. Design power-grid weakness checks: evaluate PDN hookup quality of instances. Static simulation: verify that the power-grid metal density can supply the design’s average current requirements. Dynamic vectorless simulation: detect design weaknesses with high coverage using smart toggling-instance selection. Dynamic SCAN simulation: evaluate maximum peak demand current. Dynamic RTL VCD simulation: use real activity values with state propagation. Dynamic gate-level true-timing simulation: Use gate-level VCD with true timing for accurate activity and toggle-time simulation, supporting silicon correlation. Passing the vectorless stage may be sufficient for signoff, while VCD availability improves the correctness of the activity. Dynamic simulation also adds important context by capturing the effect of package and decaps, checking simultaneous switching, and analyzing noise injected by the die, board, and package. Getting Started with the June 2026 Kit The setup remains intentionally simple. After downloading the release from the Cadence ASK portal, users can install and launch the environment with the following flow: cd gtar -zxvf VTK_Jun_15_2026.tar.gz cd VTK_Jun_15_2026/Voltus_Training_Kit # Edit environment_settings to set the PDF reader, for example: setenv PDF_READER evince # Source the environment and run make commands source environment_settings You may find various common make commands in the Voltus Training Kit . Bring Your Design into the Flow The Voltus Training Kit is not limited to canned examples. It can also run user-design simulations using integrated scripts. The June 2026 introduction describes separate paths for Voltus and Insight flows. Voltus Flow Download and install the kit from Cadence ASK. Run make REQUIRED_VOLTUS_DESIGN_INPUTS to identify required design inputs. Run make ADD_VOLTUS_DESIGN to add the design to the training-kit structure. Update the block setup file manually if needed. Source environment_settings and run make commands, such as make RLRP. The user may further refer to the included design-review presentation in the Voltus training kit for more details. Insight Flow Download and install the kit from Cadence ASK. Run make REQUIRED_INSIGHT_DESIGN_INPUTS to identify required design inputs. Run make ADD_INSIGHT_DESIGN to add the design to the training-kit structure. Update the block setup file manually if needed. Run make commands, such as make INSIGHT_POST_CTS_RPG. Use the included design-review presentation. Direct Access to the Full Learning Path The kit also provides direct links to its documentation so users can go directly to the topic they need. The documentation includes infrastructure guides, design-review templates, and simulation guides for IR basics , Data input preparation , Design input, and Libraries checks , RLRP simulation, Static Simulation , Dynamic Simulation , Power-up Simulation , Die model , Thermal simulations , Signal EM , ESD , Hierarchy Simulation, IR Aware Timing , 3DIC , Package SPA , SoC with Analog Design , Insight and Table2IR to expedite the design as user need not to open the tar gzipped file". This structure matters because not every engineer needs to learn the complete kit at once. A package engineer may start with Package SPA. A thermal engineer may start with thermal simulation. A digital implementation engineer may start with Insight or IR-aware timing. The full kit remains comprehensive, while individual chapters make it easier for users to learn and apply the methodology that maps to their immediate design challenge. Why AI Matters in the Voltus Training Kit Evolution The June 2026 release also shows how AI can improve engineering productivity when used with control and review. In the recent development cycle, AI assisted with script improvements, documentation consistency, bot question coverage, and automation tasks such as generating and updating presentation content from simulation runs. The important principle is that engineers remain in control: AI helps accelerate repetitive or knowledge-search tasks, while engineers validate the methodology and results. This is where the Voltus Training Kit can become valuable beyond external customer enablement. It can also help internal application engineers, product engineers, and support teams reuse proven flows, learn faster from existing methodology, and respond more consistently to customer questions. From Tool Knowledge to Signoff Confidence Power integrity and signal integrity and signoff issues require a structured methodology, correct data preparation, trusted scripts, simulation coverage, debug guidance, and the ability to connect die, package, board, thermal, timing, and analog/digital considerations. The Cadence Voltus Training Kit brings these elements together into a single guided environment. For engineers working on advanced designs, the value is practical: faster ramp-up, more consistent methodology, easier debug, broader simulation coverage, and a clearer path from learning to production signoff. Download the Cadence Voltus Training Kit from the Cadence ASK portal and explore how the latest release can help accelerate your next design signoff journey. For more information, visit the Cadence ASK portal or contact the support team for guidance on using the Voltus Training Kit. Power grid weaknesses can appear as IR drop violations, excessive supply noise, timing degradation, or silicon correlation gaps late in the design cycle. In the next blog, we will cover a structured Power Grid Verification Flow Methodology that helps detect weaknesses early, improves analysis coverage, and reduces root-cause debug effort by moving from structural input checks through static simulation and advanced dynamic analysis.https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/cadence-welcomes-xinqiao-electronics-to-the-certified-training-partner-programMon, 20 Jul 2026 04:26:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364258ACat299612/cadence_blogs_8/b/cadence-support/posts/cadence-welcomes-xinqiao-electronics-to-the-certified-training-partner-program0The semiconductor industry requires a highly skilled workforce and demands that recent engineering graduates swiftly bridge the gap between academia and practical application. This is where the Cadence Training Partner Certification Program comes in. This program provides a learning environment that helps students successfully transition from academia to industry. To qualify for Cadence's certification, partners must have a proven track record of educating and placing students, as well as a portfolio of high-quality courses. Xinqiao Electronics, based in Shanghai, China, is renowned for its top-tier training solutions. We recently welcomed them as a Cadence Certified Training Partner, specializing in PCB Design . This program certifies both the training partner and the students upon completion of the required requirements. Group photo of Xinqiao Electronics team members: Technical Manager and Gold Medal Training Instructor, Zhuang Ma (f irst from left), Founder, and CEO, Jie Bai (t hird from left in the first row). Scott Hargraves, group director of Education Services at Cadence, shared his enthusiasm, saying, "We are thrilled to have Xinqiao Electronics as a Cadence-certified training partner, offering education in PCB Design while integrating Cadence's cutting-edge software and methodologies into the curriculum." Alan Bai, CEO of Xinqiao Electronics, said, "We are proud to become a member of the Cadence for the Certified Training Partner Program, marking an important milestone in our commitment to technical excellence and professional education. This certification recognizes our capabilities in delivering high-quality technical training. As a Cadence Certified Training Partner, we will continuously enhance our instructor team and integrate the latest Cadence technologies into our training programs. Our goal is to provide customers with professional, standardized, and industry-leading certification training services." The Cadence Training Partner program introduces badges in key technology areas to motivate students and recognize their achievements. These badges can be shared on social media, validating students' knowledge and skills, and enhancing their appeal to potential employers. This initiative is poised to impact the industry significantly by nurturing a skilled talent pool proficient in the latest tools and methodologies, ultimately expediting product development, reducing time to market, and elevating design quality. The collaboration between Cadence and Xinqiao Electronics demonstrates how cooperation and knowledge-sharing can foster excellence. The program aims to cultivate a vibrant community of engineers who continually push the boundaries of innovation by equipping professionals with the requisite skills and acknowledgment of their achievements. Learn more about Cadence Training Courses.https://community.cadence.com/cadence_blogs_8/b/fv/posts/pss-3-1-channels-the-gamechanger-for-target-time-communicationThu, 16 Jul 2026 18:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364251Siddh Virani/cadence_blogs_8/b/fv/posts/pss-3-1-channels-the-gamechanger-for-target-time-communication0Portable Stimulus models already feature powerful language constructs to describe scenario intent. Activities, constraints, resources, buffers, streams, and states let the Perspec solver build a legal action schedule before the test runs. That is the right layer for planned action relationships: which action produces data, which action consumes it, which operations may run in parallel, and which resources must be shared or locked. Build a legal action schedule before the test runs. That is the right layer for planned action relationships: which action produces data, which action consumes it, which operations may run in parallel, and which resources must be shared or locked. The tests generated also need to coordinate while they are running. A target-side interrupt may arrive after a device finishes work. A service loop may need to wait for requests from another running exec block. One execution context may need to send several values to another before either action completes. These situations are not just solver scheduling relationships; they are target-time communication between realization code that is already executing. The upcoming PSS 3.1 channel addresses this gap. A channel is a component type defined inside the core library sync_pkg package; it is designed to carry typed values at the target time. It provides blocking get() and put() methods, nonblocking try_get() and try_put() methods, FIFO ordering up to the declared depth, and thread-safe behavior for concurrently running realization code. PSS 3.1 channels are a standardized feature that replaces a Perspec proprietary implementation known as ps_event. Why Channels Are Different from Flow Objects Buffers and streams are scenario-layer flow objects. They make dependencies visible to the solver. A buffer says the producer must finish before consumers start. A stream says producer and consumer actions are scheduled concurrently. These are powerful constructs, but they describe relationships in the solved action graph. Channels operate inside target execution. An action can remain active, loop, compute a value from target-time state, put that value into a channel, wait for a completion value, and continue. Communication does not need to be exposed as a separate solver-visible flow object for every runtime exchange. Use flow objects when the relationship should shape the generated scenario. Use channels when the running target code needs FIFO communication or blocking synchronization after execution has started. Basic Example: Runtime Request and Completion The following example models a simple client and service that exchange multiple requests and completions while both exec bodies are running. The client sends a request, waits for the matching completion, then sends the next request. The service waits for each request and returns to completion. import std_pkg::*; import sync_pkg::*; const int NUM_REQUESTS = 4; struct request_s : packed_s<> { bit[16] addr; bit[8] data; } struct completion_s : packed_s<> { bit[8] status; bit[8] observed_data; } component pss_top { channel_c requests; channel_c completions; action client { exec body { repeat (i:NUM_REQUESTS) { request_s req; completion_s done; req.addr = (bit[16])(0x1000 + i); req.data = (bit[8])(0x40 + i); message(LOW, "client sends request addr=0x%x data=0x%x", req.addr, req.data); comp.requests.put(req); done = comp.completions.get(); if (done.status != 0) { error("request failed with status %d", done.status); } if (done.observed_data != req.data) { error("completion data mismatch expected=0x%x actual=0x%x", req.data, done.observed_data); } } } } action service { exec body { repeat (i:NUM_REQUESTS) { request_s req; completion_s done; req = comp.requests.get(); message(LOW, "service handles request addr=0x%x data=0x%x", req.addr, req.data); done.status = 0; done.observed_data = req.data; comp.completions.put(done); } } } action runtime_request_completion { activity { parallel { do client; do service; } } } } This is not just a producer-consumer stream. A stream would make the producer and consumer relationship part of the solved scenario. Here, the interesting behavior is the target-time request/completion loop inside the running exec bodies. The two actions stay active, exchange several values, and block only when the channel operation requires it. That is the kind of runtime coordination channels were designed to express. This example was generated successfully with Cadence’s Perspec version 26.06.001 using the below command: perspec generate -pss runtime_request_completion.pss -top_action pss_top::runtime_request_completion Interrupt Modeling Is an Important Use Case Interrupt-driven flows are a common place where channels are useful. A test may start a device operation, continue running target code, and then wait until an interrupt handler confirms that the hardware has completed the operation. A typical structure is: import sync_pkg::*; extend component uart_c { channel_c tx_irq; channel_c rx_irq; target function void Isr() { uart_ctrl_ua_cisr_reg_s status; status = regs.ua_cisr.read(); if (status.tempty == 1) { bool put_status = tx_irq.try_put(1); if (put_status == false) { message(LOW, "TX interrupt indication could not be queued"); } } if (status.rtrig == 1) { bool put_status = rx_irq.try_put(1); if (put_status == false) { message(LOW, "RX interrupt indication could not be queued"); } } } extend action rx_uart_data { exec body { bit[32] fifo_data; comp.rx_irq.get(); fifo_data = comp.regs.ua_rfifo.read().data; // Check or process the received data here. } } } The ISR uses try_put() because interrupt handlers should avoid blocking when possible. If the channel is full, the return value makes overflow handling explicit. The waiting action uses get() because it should stop at that point until the interrupt indication is available. This mirrors real interrupt-driven software more naturally than a purely solved dependency. The action is not merely ordered after another action. It is waiting for a runtime condition observed by the target code. Executors and Target Execution Units PSS already uses the term executor for a target thread or processing context that can run exec code. A generated test may also have a larger packaging boundary: a target program or image that contains one or more executors. In the current Perspec flows this packaging boundary is called an executable. In the upcoming PSS 3.1 terminology, this concept is expected to be called a target execution unit. This distinction matters for channels because target-time communication may happen between exec blocks that are placed in different ways: On the same executor, On different executors in the same target execution unit, Or on executors that belong to different target execution units. The PSS source code should not need to change for each placement. The model says put(), get(), try_put(), or try_get() on a channel. The tool then chooses the appropriate generated implementation for the target platform. When both sides of the channel are local to the same generated C image, the implementation can use local generated storage and a local mailbox-style synchronization mechanism. When the channel crosses target execution units, the implementation must use a communication mechanism both sides can access. In the HSI example, Perspec generated two C files: One C file runs on the simulation side and drives the SystemVerilog environment through DPI, while another embedded C file executes on the OpenRISC RTL. For channel communication that crosses that boundary, Perspec generated a shared memory mailbox plus a doorbell-style notification mechanism. This is one of the main benefits of channels. The model captures the target-time communication intent once, while the tool handles whether the generated implementation is local, shared-memory based, or mapped to another platform-specific synchronization mechanism. When to Use Channels Use channels when: Communication happens while exec code is running. The producer and consumer are long-running target-side behaviors rather than single solved action endpoints. Runtime code needs FIFO ordering with a declared depth. Blocking or nonblocking synchronization is needed between concurrently running realization code. An interrupt handler or callback needs to notify model code that is waiting at the target time. Do not use channels just to replace flow objects. If the dependency should be visible to the solver, use buffers, streams, states, resources, and constraints. Channels are for target-time communication in the realization layer. Conclusion PSS 3.1 channels add a standard way to describe target-time communication between running realization code. They complement, rather than replace, solver scheduling and flow objects. Flow objects shape the scenario before execution; channels coordinate execution after the generated test is already running. Interrupt modeling is one of the most common uses, but it is not the only one. Request/completion loops, service-style target code, callbacks, and communication across execution contexts all benefit from the same abstraction. Channels let the model express the intent portably while leaving the implementation details to the PSS tool and target platform. While PSS LRM 3.1 is expected to be officially published in October–November 2026, users can start leveraging channel functionality today with Perspec version 26.06.001 .https://community.cadence.com/cadence_blogs_8/b/cic/posts/corner-fomo-ai-enabled-smart-corners-know-where-the-real-problems-hideThu, 16 Jul 2026 08:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364063Niyati Singh/cadence_blogs_8/b/cic/posts/corner-fomo-ai-enabled-smart-corners-know-where-the-real-problems-hide0Imagine you are designing a precision analog block targeted for a high‑volume product. Your schematic looks clean, specifications pass across nominal conditions, and traditional PVT corners seem well covered. Yet, late in the design cycle, unexpected yield loss appears—not at obvious corners, but at rare combinations of process and mismatch variation that were never explicitly simulated. This is the reality of modern silicon variability. As process nodes shrink and performance margins tighten, rare statistical outliers—not nominal corners—often determine yield. This is where Spectre Fast Monte Carlo (FMC) Analysis’ Smart Corners fundamentally changes how designers think about variation analysis. Delivered through Virtuoso ADE Artist, Smart Corners leverages AI‑assisted techniques to find statistically derived worst‑case corners, enabling designers to detect rare failures, estimate yield accurately, and improve robustness—without the prohibitive cost of brute‑force Monte Carlo simulations. The Problem with “Corner Anxiety” Every analog designer knows the feeling. You run simulations at nominal corners, everything looks beautiful. You run SS and FF corners, still okay. Then someone asks: “But what about the real worst case ?” Cue the corner anxiety. Modern silicon variability doesn’t always show up where we expect it. That’s why Cadence introduced Spectre FMC Analysis to make statistical variation analysis faster and more practical. And sitting right on top of that capability is a powerful idea called Smart Corners . Smart Corners help designers stop guessing and start listening to the data , all inside Virtuoso ADE Artist , where simulation results turn into real insight rather than simulation fatigue. What Makes Smart Corners “Smart”? Smart Corners help to make statistical variation analysis more efficient and insightful. Smart Corners begins with the process, voltage, temperature (PVT), and design parameter combinations already defined by the designer. Spectre FMC then performs statistical analysis across these conditions and identifies groups of corners that exhibit similar behaviour. By classifying and prioritizing existing simulation conditions according to their statistical impact, Smart Corners leverages computational effort on the classifications, quickly identifying those that fail to meet performance requirements and risk yield. In traditional corner analysis: Designers define numerous PVT combinations to improve coverage Many corners provide overlapping information Simulation cost grows rapidly as coverage expands Identifying the truly influential conditions can be difficult With Smart Corners: Spectre FMC evaluates statistical behaviour across the defined corners Similar corner behaviours are identified and grouped Verification effort is intelligently distributed across groups Yield-relevant scenarios can be analyzed with improved efficiency The result is a more targeted verification methodology that helps designers gain statistical insight while reducing unnecessary simulation effort. Smart Corners Explained (With a Real-Life Analogy) Think of Smart Corners like planning a road trip. Old-school method: You examine every available route individually, even when many of them experience nearly identical traffic patterns. Smart Corners method: A navigation system says: "These routes behave similarly. Focus on these few representative routes because they capture the important traffic patterns." That’s Smart Corners for your circuit. Rather than treating every predefined corner as equally important, Spectre FMC identifies behavioural similarities and helps direct analysis that provide the greatest insight into performance variation and yield risk. Why Virtuoso ADE Artist Is the Perfect Playground Virtuoso ADE Artist is designed for advanced‑node and high‑sigma designs , building on ADE Assembler and the Virtuoso Variation Option to provide a unified cockpit for advanced statistical analysis. Virtuoso ADE Artist serves as the interactive cockpit for: Managing simulations Visualizing Monte Carlo results Evaluating performance metrics When paired with Spectre FMC: Statistical trends become visible Outliers stop hiding Smart Corners become actionable verification points How Smart Corners Improve Yield Confidence Smart Corners enable designers to move from coverage‑based verification to risk‑based verification. Instead of asking: “Did I simulate all the standard corners?” Designers can now ask: “Have I found the statistically worst conditions that threaten yield?” Smart Corners help teams focus verification effort where it delivers the greatest value. Conclusion: Work Smart, Not Hard (or Not All Corners) As variability becomes the dominant design challenge, statistically intelligent methodologies are no longer optional . Spectre FMC Smart Corners empower designers to uncover hidden risks, validate designs with confidence, and achieve high yield—without the simulation burden of brute‑force approaches. Spectre FMC Smart Corners represent a practical evolution in analog verification: From exhaustive corner exploration → statistically guided analysis From redundant simulations → focused verification insight When used inside Virtuoso ADE Artist, Smart Corners help designers spend less time running simulations and more time understanding what actually matters! So the next time someone says: “Did you run all corners?” You can smile and reply: “I focused on the ones that mattered most.” Watch and Learn: Demo Video on Smart Corners! To understand more about Smart Corners, you can watch a small training bye video which shows this in action. Demo Spectre FMC Smart Corners in Virtuoso ADE Artist Training Spotlight: Spectre FMC in Virtuoso ADE Artist These concepts are covered in depth in the Spectre FMC in Virtuoso ADE Artist Customer Education course. Key Topics Covered Monte Carlo simulations in Virtuoso ADE Assembler Spectre Fast Monte Carlo methodology AI‑enhanced FMC analysis Smart Corners setup and execution Mismatch contribution analysis Yield estimation and improvement techniques For lecture, lab instructions and a downloadable design, enroll in the online training courses of your interest on Spectre FMC in Virtuoso ADE Artist . Training is also available as "Blended" or "live" class. Digital Badge Available You can become Cadence Certified once you complete the course (s) and share your knowledge and certifications on social media channels. Go straight to the course exam at the Cadence ASK and Learning portal. Note : Some of the above links are accessible only to Cadence customers who have a valid login ID for the Cadence ASK and Learning portal . The faster you finish your online training, the sooner you can claim your Digital Badge . Want to know how accelerated learning works? Our video walks you through the pre-quiz, navigation, and essential features. This is just the beginning. We're regularly adding new Accelerated Learning titles . Accelerated Learning courses are marked with this symbol in our Learning Maps . Do You Have Access to the Cadence ASK Portal? To find information on how to get an account on the Cadence ASK – Learning portal, check the Cadence ASK – Application Support and Knowledge page. To stay up to date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails. Cadence Customer Education Learning Maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. Click on Learning Map to see all our courses in each technology area and the recommended order in which to take them. Wondering how to take an online class at your own pace? Come join us and learn from the Cadence Training offerings. If you have questions about courses, schedules, online, public, or live on-site training, reach out to us at Cadence Training . Happy reading! Niyati Singhhttps://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/the-three-phases-of-ai-adoptionThu, 16 Jul 2026 00:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364221Corporate/cadence_blogs_8/b/corporate-news/posts/the-three-phases-of-ai-adoption0Artificial intelligence is often discussed as if the industry is moving through a single technology cycle. But AI adoption is not unfolding as a single event; it is unfolding in waves. The first phase of AI adoption, infrastructure AI, is already reshaping the global technology economy. Driven by hyperscale computing, generative AI, agentic systems, and increasingly long-running reasoning models, this phase alone represents a multi-trillion-dollar market that continues to expand at extraordinary speed. Still, it represents only the first stage of a much broader transformation that will eventually extend from data centers to autonomous systems and scientific discovery itself. This broader view of AI adoption also reflects Cadence's long-standing systems-oriented approach to intelligent engineering, where infrastructure, computational software, and AI increasingly evolve as interconnected layers of innovation. Each wave introduces new opportunities and increasingly complex engineering challenges. The first phase centers on building the infrastructure required to power intelligence. The next step extends intelligence into systems that can perceive and interact with the physical world. Beyond that lies perhaps the most ambitious opportunity yet: applying AI to accelerate scientific discovery itself. Industry discussions have pointed to AI demand increasing by as much as over the next five years. Even assuming major advances in hardware and software efficiency—including more efficient models, mixed-precision computing, and improved accelerator architectures—the resulting growth rates could still translate into sustained annual expansion of roughly 30–60%. But the current AI buildout represents only the opening chapter. Each phase builds on the previous one while expanding the boundaries of what intelligent systems can do. Phase One: Infrastructure AI The first phase of AI adoption is the one reshaping entire industries today. Infrastructure AI includes the technologies required to train, deploy, and scale modern AI systems—advanced semiconductors, AI accelerators, high-bandwidth memory, hyperscale data centers, communications infrastructure, and edge computing. Demand for these systems continues to accelerate rapidly. The rise of agentic AI systems and long-running reasoning models is further accelerating infrastructure demand, increasing the need for compute capacity, memory bandwidth, networking performance, and system-level optimization across the AI stack. What makes this moment particularly significant is that AI demand is growing faster than traditional engineering productivity can scale. Yet building larger infrastructure is no longer simply a matter of increasing compute capacity. As AI models become larger and more complex, performance increasingly depends on optimizing entire systems rather than individual components. Chips, chiplets, packaging technologies, networking architectures, cooling systems, power delivery, and data center environments must operate as tightly integrated platforms. The challenge is shifting from building more infrastructure to building smarter infrastructure. This shift is already changing how engineering teams think about system design. Performance, efficiency, and scalability can no longer be optimized independently; they increasingly need to be addressed simultaneously across the entire stack. But intelligence does not stop at data centers. The next wave begins when AI moves from processing information to interacting directly with the physical world. Phase Two: Physical AI Until now, much of AI has lived inside data centers and software environments. Physical AI represents the next major shift: moving intelligence into machines and systems that can perceive, reason, and act within the real world. Physical AI introduces autonomous vehicles, drones, robotics, industrial systems, and intelligent edge platforms that are expected to reshape industries already measured in trillions of dollars. The automotive industry alone represents a multi-trillion-dollar market, while industry projections increasingly point to robotics becoming one of the largest technology categories ever created, with long-term opportunities potentially reaching tens of trillions of dollars. The opportunity extends across transportation, industrial automation, healthcare, logistics, and intelligent machines designed to operate alongside people and within complex environments. But enabling intelligence to operate in the physical domain introduces entirely new engineering challenges. Training an AI model inside a data center is fundamentally different from enabling a robot to navigate a factory floor or allowing an autonomous system to safely operate in dynamic environments. AI is no longer simply processing information; it is increasingly interacting directly with the world around it. Systems require more than compute power and inference capability. They must understand motion, physical interactions, environmental conditions, safety constraints, and unpredictable behavior. These requirements are increasing the importance of computational software and high-fidelity simulation because intelligent systems first need to understand reality before they can safely operate within it. Increasingly, simulation is evolving into broader digital twin environments that continuously connect virtual and physical behavior. Beyond modeling structural behavior, thermal effects, motion, and system interactions before deployment, digital twins help engineers validate, optimize, and refine performance across the lifecycle of increasingly complex systems. Closing the gap between simulation and operational behavior is becoming one of the defining engineering challenges of the physical AI era. As intelligence expands into physical systems, engineering itself becomes increasingly multidisciplinary. Phase Three: Sciences AI Beyond infrastructure and physical systems lies the third phase of AI adoption: applying intelligence to science itself. If infrastructure AI teaches machines to process information and physical AI enables machines to understand the world, sciences AI may help uncover knowledge that humans have not yet discovered. Over the long term, this may ultimately become the largest opportunity of all. Scientific problems often involve enormous search spaces and highly complex interactions that can take years—or even decades—to explore through traditional methods. AI has the potential to accelerate discovery across material science, molecular modeling, biology, and drug development in ways that were previously difficult to imagine. Many industry leaders believe life sciences may ultimately become one of the largest opportunities for AI-driven discovery, particularly as AI systems become increasingly capable of modeling biological complexity and accelerating molecular research. Rather than simply automating existing processes, AI begins helping researchers uncover entirely new possibilities. The same capabilities that enable intelligent systems, massive computational scale, physically grounded models, and intelligent exploration—can increasingly help scientists navigate complexity and identify patterns that may otherwise remain hidden. In this phase, AI shifts from helping humans perform tasks more efficiently toward helping discover solutions that may never have been considered before. The Future Extends Beyond AI Models These phases are not isolated technology trends. They represent a progression in how intelligence expands. Infrastructure AI creates the systems that power intelligence. Physical AI moves intelligence into the real world. Sciences AI applies intelligence to discovery itself. As new phases start, the previous ones do not stop. The compute required to generate and distribute the models and compute for physical AI and sciences AI only increase the opportunity for the designers of the silicon and systems infrastructure. Across all three phases, one principle remains constant: progress depends on more than AI alone. Increasingly capable systems require advances in computing infrastructure, computational software, and intelligent engineering working together. As AI systems become more sophisticated, engineering itself becomes more intelligent, creating a continuous cycle in which technology not only drives innovation but increasingly helps create it. The future of AI will not be defined solely by larger models or faster hardware. It will be defined by how effectively intelligence and engineering evolve together—and by how successfully we move from building intelligent systems to building systems that help create the next generation of intelligence itself. Learn how Cadence's Design for AI and AI for Design vision is reshaping semiconductor innovation. Explore the rest of this series to learn how Cadence's Design for AI and AI for Design strategy, together with the Three-Layer Cake framework , helps connect infrastructure, intelligent systems, and the future of AI-driven engineering.https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/the-three-layer-cake-the-foundation-behind-intelligent-engineeringThu, 16 Jul 2026 00:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364206Corporate/cadence_blogs_8/b/corporate-news/posts/the-three-layer-cake-the-foundation-behind-intelligent-engineering0Artificial intelligence is rapidly becoming the engine behind the next era of technology innovation. From hyperscale data centers and autonomous systems to robotics and scientific discovery, AI is expanding into nearly every industry. Yet many discussions about AI focus only on what people can see—larger models, smarter assistants, and increasingly capable autonomous systems. The reality is that AI itself represents only the visible layer of a much larger technology ecosystem. Behind every AI breakthrough lies a much larger technology stack that includes advanced computing infrastructure, physically accurate computational software, and intelligent automation working together. As AI expands into hyperscale computing, autonomous systems, robotics, scientific discovery, and intelligent products, success increasingly depends on how effectively these technologies operate as an integrated ecosystem. Cadence has been evolving this systems-oriented view of intelligent engineering for years. Earlier strategies centered on concepts such as pervasive intelligence, system innovation, and design excellence, reflecting the industry's growing need to optimize hardware, computational software, and engineering workflows as interconnected systems rather than isolated domains. By 2023, as AI infrastructure, scientific computing, and intelligent automation increasingly converged, Dr. Anirudh Devgan , president and CEO of Cadence, began referring to this vision as the "Three-Layer Cake" to help visualize how innovation across these interconnected layers must work together to power the next era of intelligent system design. The Three-Layer Cake is a framework that illustrates how innovation depends on the convergence of accelerated computing, computational software, and intelligent automation. The framework describes AI as three interconnected layers: Accelerated Computing and Data Principled Simulation and Optimization AI Agents and Agentic Intelligence The lower layers create the infrastructure and scientific foundation required to build increasingly intelligent systems, while the upper layer applies AI to improve how those systems themselves are designed. Together, these layers form the bridge between building AI technologies and using AI to accelerate engineering innovation. Layer One: Accelerated Computing and Data The foundation of the cake is Accelerated Computing and data infrastructure, the systems responsible for delivering the performance and scale required for modern AI. This layer forms the core of Design for AI because it provides the hardware foundation required to power modern AI workloads, from advanced silicon and memory architectures to large-scale computing systems and AI infrastructure. Over the last several years, the compute foundation has transformed dramatically. Traditional X86-centric environments have evolved into platforms built around GPUs, Arm systems, AI accelerators, emerging XPU architectures, and custom silicon. Recognizing this transition early, Cadence began porting computational software several years ago to operate efficiently across hybrid environments. As AI workloads continue scaling, software optimization across increasingly diverse hardware architectures becomes just as important as raw compute capability. This infrastructure now powers everything from cloud computing environments and AI factories to large-scale training and inference workloads. As AI models become larger and more complex, demands on this layer continue to increase. Performance is no longer determined by silicon alone. It increasingly depends on optimization across the complete system stack, including advanced packaging, chiplets, networking, power delivery, cooling systems, and large-scale data center environments. Equally important is the growing convergence between hardware and computational software. Matching the right software to the right hardware architectures is unlocking orders-of-magnitude improvements in computational performance, scalability, power efficiency, and the ability to analyze increasingly complex datasets and engineering problems. As heterogeneous computing continues to evolve, advances in hardware and software optimization are becoming deeply interconnected drivers of AI innovation. This foundation provides the computational scale needed for the AI era. But raw compute capability alone does not create intelligent systems. Layer Two: Principled Simulation and Optimization Above the compute layer sits the scientific backbone of intelligent engineering: the computational foundation that connects Design for AI and AI for Design . It combines classical algorithms, numerical methods, and science-based models from physics, chemistry, and mathematics to accurately model real-world system behavior. While AI can generate possibilities, this layer determines whether those possibilities work in the world around us. For semiconductor and system design, these models ensure compliance with real-world constraints such as: Thermal behavior Signal integrity Analog characteristics Manufacturability Reliability Power consumption This layer becomes increasingly important as systems become more heterogeneous and interconnected. Continued innovation in the middle layer remains critical because AI cannot compensate for weak engineering foundations. Automation alone does not create better outcomes. A useful analogy is autonomous driving. Adding sophisticated automation to a poorly designed vehicle does not create a better system. The underlying vehicle itself must already operate reliably. Similarly, AI-driven automation requires highly accurate, physically grounded computational engines underneath it. Improvements in simulation, optimization, and core design technologies ultimately amplify the effectiveness of the AI layer above. Intelligence becomes significantly more valuable when built on top of physically accurate and scientifically grounded foundations. This is also where computational software becomes increasingly important, not simply as a collection of tools and solutions, but as the engines that transform raw compute capability into accurate engineering outcomes. Layer Three: AI Agents and Agentic Intelligence At the top of the framework sits AI itself—the layer that increasingly enables AI for Design by embedding intelligence directly into engineering workflows. This layer includes generative AI, reasoning systems, optimization AI, and agentic AI technologies capable of coordinating complex workflows. AI has evolved from optimization AI focused on narrow tasks to more sophisticated agents and now toward super-agent systems capable of orchestrating complete engineering workflows. Importantly, not every engineering challenge requires massive, general-purpose AI models with billions of parameters. Many design problems demand highly specialized optimization approaches tailored to specific tasks. Rather than relying exclusively on large general-purpose models, Cadence also leverages compact domain-specific neural networks, optimization engines, and reasoning systems that can operate in real time while maintaining speed, scalability, and physical accuracy. Cadence is advancing this transition through applying agentic AI to engineering with innovations such as ChipStack AI Super Agent , ViraStack AI Super Agent , InnoStack AI Super Agent , and AuraStack AI Super Agent , which use domain-specific knowledge graphs to capture design semantics, hierarchy, and connectivity beyond the context limits of traditional LLMs. These systems can autonomously generate verification plans, refine tests, optimize implementation strategies, and coordinate complex design tasks across engineering environments. Rather than replacing engineering expertise, these systems now function as specialized design partners embedded directly into the engineering process. As AI becomes more tightly integrated with computational software and underlying compute infrastructure, super agents have the potential to transform how engineering work is planned, executed, and optimized across increasingly complex design environments. In many ways, this reinforces the virtuous cycle at the center of Design for AI and AI for Design: increasingly capable AI systems require more advanced engineering, while AI itself increasingly helps engineers create the next generation of those systems. Understanding each layer independently is important. The larger insight, however, comes from understanding how they interact. Why Is It a Cake? The value of the Three-Layer Cake framework is in combining solutions that leverage simultaneous innovation across the full engineering stack. Advances in compute create larger opportunities for simulation and AI. Improvements in computational software strengthen physical accuracy and system understanding. AI then amplifies both through automation, reasoning, and productivity gains. The result is a self-reinforcing cycle where each layer strengthens the others. This interconnected nature is also why Dr. Devgan began referring to the framework as a "Three-Layer Cake." As he later explained, the layers of the cake are not consumed independently like a traditional technology stack; they work together simultaneously. Accelerated Computing and data, principled simulation and optimization, and AI—each layer amplifies the capabilities of the others, and meaningful breakthroughs increasingly happen when all three are optimized together. As the framework gained broader visibility, the "Three-Layer Cake" terminology itself increasingly became shorthand for describing the tight interplay among hardware, software, and AI in industry discussions. The growing adoption of the phrase reflects an important engineering reality: the industry is moving toward tightly integrated systems where compute, software, and intelligence are inseparable. This is also why the Three-Layer Cake serves as the bridge between Design for AI and AI for Design. The lower layers create more capable systems and infrastructure, while the upper layer applies intelligence back into engineering processes. Together, they create a continuous cycle where AI systems and AI-driven engineering reinforce one another. Building the Future Across Every Layer The future of AI will not be defined solely by larger models or faster hardware. Competitive advantage will increasingly depend on how effectively organizations innovate across the complete technology stack. The Cadence Three-Layer Cake illustrates that intelligent engineering requires more than AI alone—it requires advances in Accelerated Computing and data, principled simulation and optimization, and AI-driven intelligence working together. This same framework also serves as the foundation for Cadence's Design for AI and AI for Design strategy, creating a virtuous cycle where AI systems and intelligent engineering continuously strengthen one another. As the industry moves toward physical AI and sciences AI, innovation across all three layers will shape the next era of technology. Learn how Cadence's Design for AI and AI for Design vision is reshaping semiconductor innovation. Explore the rest of this series to learn how Cadence's Design for AI and AI for Design strategy and the Three Phases of AI Adoption help connect infrastructure, intelligent systems, and the future of AI-driven engineering.https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/design-for-ai-and-ai-for-designThu, 16 Jul 2026 00:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364193Corporate/cadence_blogs_8/b/corporate-news/posts/design-for-ai-and-ai-for-design0The semiconductor industry is experiencing a once-in-a-generation transformation. Recent projections suggest the semiconductor market could approach $2 trillion by 2030 , driven by the rapid rise of AI and the growing demand for intelligent computing systems. Generative AI, hyperscale computing, autonomous systems, and intelligent infrastructure are reshaping both the demand for semiconductors and the way complex systems are designed, built, and deployed. AI is now driving investment across the entire technology ecosystem: from advanced silicon and high-bandwidth memory to AI factories, cloud infrastructure, robotics, and intelligent edge systems. What defines this moment is not just the scale, but the complexity. Every new generation of AI systems demands significantly higher compute performance, deeper system integration, tighter software optimization, and exponentially greater engineering effort. This growing complexity is creating a major challenge for the industry. Each new AI chip or intelligent system requires larger engineering teams and longer design cycles. Simply adding more engineers, or taking longer to deliver, is not a sustainable path forward. This is where Cadence's Design for AI and AI for Design strategy becomes fundamental. These two ideas are not separate; they form a virtuous cycle. AI systems require increasingly advanced semiconductors, infrastructure, and intelligent systems, while AI itself is helping engineers design those next-generation technologies faster and more efficiently. The relationship between intelligent systems and intelligent engineering is becoming deeply coupled across silicon, systems, and computational software. This coupling creates a powerful engineering flywheel. As the industry builds more advanced AI infrastructure, it enables more capable AI models and intelligent systems. Those models, in turn, help engineers create better design tools, automate more complex workflows, and accelerate innovation across the engineering stack. The result is a self-reinforcing cycle in which Cadence's customers and partners build the AI infrastructure, which creates the next generation of AI. Cadence uses this AI in our design solutions, accelerating the creation of the next generation of intelligent infrastructure. To understand why both aspects matter, it is useful to view AI not as a single technology trend but as a layered ecosystem where infrastructure, scientific computing, and intelligent automation converge to address the grand challenges ahead. This can be visualized as a "three-layer cake" of AI innovation: the foundation is accelerated computing and data infrastructure; the middle layer is software simulation and optimization based on physics principles; and the top layer is AI itself. Innovation across all three layers is mutually reinforcing. AI alone cannot compensate for weak infrastructure or inaccurate engineering models; advances in each layer amplify the effectiveness of the others. Design for AI – Building the Infrastructure of Intelligence "Design for AI" focuses on building the hardware, systems, and infrastructure required to power modern AI workloads. Today's AI models demand massive computational scale, driving rapid innovation in advanced silicon, high-bandwidth memory, photonics-based interconnects, accelerated computing platforms, AI factories, and hyperscale data centers. Engineering Beyond the Chip AI infrastructure is no longer defined at the chip level alone. Performance now depends on system-level optimization across chiplets, advanced packaging, boards, cooling systems, power delivery, networking, and full data center architectures. This is accelerating innovation in 3D-IC design, photonics, multiphysics simulation, and system-level analysis. Solutions such as the Integrity 3D-IC Platform , Allegro X Design Platform , and Clarity 3D Solver address challenges associated with heterogeneous integration, signal integrity, thermal analysis, and multi-chiplet system design for AI infrastructure. Designing Sustainable AI Infrastructure As AI compute scales exponentially, energy efficiency has become one of the defining engineering constraints of the AI era. The rapid expansion of hyperscale AI infrastructure is increasing demands on power delivery, cooling systems, thermal management, and overall data center sustainability, making system-level optimization critical for the future of large-scale AI deployment. Digital twins, thermal analysis, multiphysics simulation, and intelligent system design are becoming increasingly important for improving data center efficiency and operational sustainability. Platforms such as the Cadence Reality Digital Twin Platform and Celsius Studio Platform help model airflow, cooling behavior, thermal dynamics, and power distribution before physical deployment, improving reliability, optimizing energy usage, and accelerating deployment cycles. This physics-based approach for data center design and operation is critical to meet the computation requirements for tomorrow's AI. While these technologies define the infrastructure layer of AI, AI is transforming the design process itself. AI for Design – Using AI to Reinvent Engineering AI is not only reshaping what engineers build; it is also transforming how they build. Traditional electronic design automation (EDA) workflows relied heavily on deterministic algorithms, manual iteration, and heuristic optimization. However, modern semiconductor and system designs have grown too complex for conventional approaches alone. AI systems now contain billions—or even trillions—of transistors, highly heterogeneous architectures, and deeply interconnected hardware and software workflows. At the same time, product cycles continue to shrink. To keep pace, AI is embedded directly into engineering workflows. This is the essence of AI for Design . AI-driven design solutions help engineers automate repetitive tasks, optimize power, performance, and area (PPA), accelerate verification, analyze enormous datasets, and explore design spaces far beyond human capability. Optimization AI Built for Engineering Not all engineering AI problems require large, general-purpose large language models with billions of parameters. Many require highly specialized optimization approaches tailored to specific design objectives. Cadence's optimization AI strategy centers on bespoke, purpose-built neural networks embedded deeply inside core design engines . These compact neural networks contain thousands—not billions—of parameters and are designed for real-time learning directly during active design runs. This enables tight integration with classical EDA algorithms while preserving speed, scalability, and physical accuracy. An example is Cadence Cerebrus AI Studio to autonomously explore backend implementation strategies across block and full SoC designs, enabling faster convergence, improved PPA, and greater compute efficiency through cross-project learning. As AI becomes more deeply integrated within engineering systems, the industry is shifting from task-level automation toward end-to-end workflow orchestration. From AI Assistants to Super Agents The industry is moving beyond simple AI assistants toward a new class of computational software: super agents capable of orchestrating complex, end-to-end engineering workflows . Rather than functioning as standalone LLMs, these systems combine natural-language interaction, structured workflows, deterministic guardrails, and domain-specific capabilities and skills, with deep EDA integration to deliver predictable and production-grade outcomes. This evolution reflects a broader progression in AI-driven engineering: from isolated task automation to coordinated, system-level intelligence. Advances in agentic AI, long-context reasoning, and skills-based orchestration are enabling AI systems to operate across tools, workflows, and design environments with increasing autonomy. Cadence is advancing this transition through an expanding portfolio of AI super agents, including ChipStack AI Super Agent , ViraStack AI Super Agent , InnoStack AI Super Agent , and AuraStack AI Super Agent , along with Cadence AgentStack as a head agent to coordinate multiple specialized agents. These systems combine the best of both worlds: the reasoning and generative capabilities of AI, grounded in the science and physics of trusted EDA and SDA solutions. They leverage domain-specific knowledge graphs and contextual design intelligence to capture semantics, hierarchy, connectivity, and workflow intent, extending far beyond the context limits of traditional LLMs. The emergence of skills-based agentic AI is significantly expanding engineering automation. These systems can autonomously generate verification plans, refine tests, optimize implementation strategies, coordinate regression workflows, and interact directly with engineering tools across the design process. By continuously ingesting specifications, design data, documentation, and workflow context, they build a persistent representation of engineering intent that enables deeper orchestration across semiconductor and system design environments. This shift is not only transforming engineering productivity—it is reshaping the trajectory of AI adoption itself. Beyond Infrastructure AI As AI evolves from infrastructure AI to physical AI and eventually to sciences AI, the connection between intelligent systems and intelligent engineering will only deepen. The future of the semiconductor industry will not be defined solely by faster chips or larger AI models. It will be defined by how effectively intelligence, computational software, and engineering infrastructure evolve together to create increasingly autonomous systems capable of designing, optimizing, and accelerating the next generation of technology itself. Learn how Cadence's Design for AI and AI for Design vision is reshaping semiconductor innovation. Explore the rest of this series to learn how Cadence's Three-Layer Cake framework and the Three Phases of AI Adoption help connect infrastructure, intelligent systems, and the future of AI-driven engineering.https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/ai-infrastructure-starts-beyond-the-chipWed, 15 Jul 2026 22:35:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364249Corporate/cadence_blogs_8/b/corporate-news/posts/ai-infrastructure-starts-beyond-the-chip0Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation For much of the AI revolution, competitive advantage has been measured by one metric: building faster chips. Every breakthrough in foundation models has driven demand for more powerful GPUs, higher memory bandwidth, and increasingly advanced semiconductor process technologies. The prevailing assumption has been that AI leadership would be determined primarily by silicon innovation. That assumption is no longer enough. As AI infrastructure scales from individual accelerators to rack-scale systems and planetary-scale AI factories, the industry's next frontier of innovation is shifting beyond the processor itself. Performance now depends just as much on the physical systems that connect, power, cool, and integrate compute at unprecedented scale. Advanced packaging, high-speed printed circuit boards (PCBs), power delivery, thermal management, and heterogeneous integration have become defining elements of modern AI architecture. This evolution also exposes a new engineering challenge. While semiconductor design has benefited from decades of highly automated EDA, PCB and advanced packaging development remain comparatively fragmented. Engineering teams often work across disconnected tools and sequential workflows despite solving increasingly complex electrical, thermal, mechanical, and manufacturing problems. Closing that gap requires extending AI beyond chip implementation into system realization. Building on Cadence's proven AI Super Agent architecture for silicon design, AuraStack AI Super Agent extends intelligent engineering into advanced packaging and PCB development. Purpose-built for system design, AuraStack AI Super Agent coordinates domain-specific AI agents across planning, implementation, and tightly integrated signoff multiphysics analysis, enabling engineering teams to move from disconnected workflows toward AI-native, physics-aware design orchestration. Why is this evolution necessary? Because the bottleneck in AI is no longer just the chip, it is the system surrounding it. Packaging Has Become Part of the Compute Architecture For decades, semiconductor packaging primarily protected the die, provided electrical connectivity, and enabled manufacturability. Today, it has become an active component of the compute architecture itself. Every modern AI accelerator depends on advanced packaging. Whether deployed for hyperscale AI training, enterprise inference, robotics, or edge intelligence, there is no practical path to delivering the bandwidth, memory capacity, and energy efficiency demanded by AI without technologies such as chiplets, HBM, silicon interposers, and advanced 2.5D and 3D integration. The industry's transition toward heterogeneous integration is fundamentally changing how processors are built. Rather than manufacturing ever-larger monolithic dies, designers increasingly partition functionality across specialized chiplets optimized for compute, memory, I/O, networking, and domain-specific acceleration. Advanced packages provide the communication fabric that integrates these chiplets into a single logical system. Packaging is no longer an extension of chip design; it is part of the compute architecture. Every architectural decision, from die placement and interconnect topology to power distribution, thermal paths, and manufacturing strategy, directly affects performance, yield, scalability, reliability, and cost. As chiplet adoption accelerates, packaging increasingly determines how efficiently AI systems scale. PCB Design Has Become a Multiphysics Challenge If advanced packaging governs communication within the processor, the PCB governs communication across the entire system. That responsibility has never been more demanding. Modern AI accelerator boards must deliver thousands of watts of power, route ultra-high-speed interfaces exceeding 224G, maintain exceptionally tight signal integrity margins, support increasingly sophisticated cooling technologies, and satisfy stringent manufacturability requirements. These are no longer independent engineering challenges. A routing decision influences electromagnetic behavior. Electromagnetic effects alter signal integrity. Signal quality impacts timing margins. Timing affects power consumption. Power density changes thermal behavior, which influences mechanical stress, reliability, and product lifetime. The physics are inseparable. As a result, AI infrastructure demands concurrent optimization across silicon, advanced packaging, PCB implementation, thermal management, power delivery, and manufacturing. Extending the intelligence and automation that transformed semiconductor design into these disciplines represents the next major opportunity for engineering innovation. Engineering Workflows Have Not Kept Pace Ironically, while AI infrastructure has become increasingly integrated, the engineering workflows used to build it remain fragmented. Semiconductor teams routinely benefit from unified design databases, AI-assisted optimization, continuous verification, and highly automated implementation flows. PCB and advanced packaging development have not experienced the same level of transformation. Package designers, PCB engineers, thermal analysts, mechanical specialists, manufacturing experts, and reliability teams frequently work in separate environments using disconnected data models. Design decisions are often evaluated sequentially, creating lengthy iteration cycles as changes ripple across electrical, thermal, mechanical, and manufacturing domains. That methodology was effective when interactions between disciplines were limited. It becomes increasingly unsustainable when every engineering decision affects system-level performance. The challenge is no longer solving individual problems. It is orchestrating them into a single, continuously connected engineering process. Physical AI Raises the Stakes The next wave of AI will make this challenge even more pronounced. Unlike today's cloud infrastructure, Physical AI spans an extraordinary range of deployment environments, from autonomous vehicles and industrial robots to aerospace systems, medical devices, and intelligent factories. Each application introduces unique requirements for package architectures, PCB form factors, power delivery, thermal management, mechanical durability, and environmental resilience. There is no universal hardware platform capable of satisfying every workload. Instead, engineering teams must evaluate countless combinations of chiplets, advanced packaging technologies, PCB architectures, cooling strategies, materials, and manufacturing processes to optimize each application. Every design decision introduces tradeoffs that ripple across electrical, thermal, mechanical, and manufacturing domains. As AI moves from hyperscale data centers into the physical world, the diversity and complexity of system design will continue to accelerate, making intelligent orchestration across these disciplines increasingly essential. From AI Assistance to AI Orchestration Meeting this challenge requires more than incremental improvements to existing workflows. It requires a fundamentally different engineering model, one that combines agentic AI, trusted EDA, and system design analysis (SDA), multiphysics simulation, and domain-specific engineering knowledge within a single environment. Rather than merely assisting engineers with isolated tasks, AuraStack AI Super Agent orchestrates the complete PCB and advanced packaging design flow. Domain-specific AI agents coordinate planning, implementation, constraints management, physical realization, and tightly integrated signoff multiphysics analysis while continuously grounding decisions in trusted engineering data and verified simulation models. Within this AI-native workflow, domain-specific simulation technologies remain at the center of engineering decision-making: Sigrity X Platform – In-design signal integrity (SI) and power integrity (PI) analysis. Celsius Thermal Solver – Early-stage system analysis of thermal behavior, warpage, and stress fields. Clarity 3D Solver – High-fidelity 3D electromagnetic analysis for signal integrity and electromagnetic performance. MSC Nastran Finite Element Solver – Mechanical analysis performing structural, thermal, dynamic, and nonlinear simulations. Marc Advanced Nonlinear FEA Simulation – Advanced finite element analysis simulating coupled multiphysics, including thermal-mechanical, electromechanical, and fluid-structure interactions. ANSA Pre-Processor – Advanced CAE pre-processing for efficient and reliable simulation model preparation. Rather than operating as standalone point tools, these technologies are orchestrated by the AuraStack AI Super Agent, enabling AI agents to invoke the appropriate solver at the right stage of the design process and continuously optimize electrical, thermal, electromagnetic, mechanical, and manufacturing tradeoffs across the complete system. This approach shifts engineering from sequential iteration to continuous co-optimization. Instead of validating designs only after implementation, multidisciplinary teams can evaluate electrical, thermal, mechanical, and manufacturing tradeoffs throughout development, reducing costly respins while accelerating design convergence. By integrating AI orchestration with high-fidelity simulation, engineering expertise becomes more accessible. Organizations no longer need large multidisciplinary teams to evaluate every design alternative manually. Startups developing AI accelerators, robotics platforms, and next-generation computing systems can leverage the same intelligent engineering capabilities traditionally available only to the industry's largest organizations, helping democratize innovation across the AI ecosystem. The Next Era of AI Will Be Defined by System Intelligence The semiconductor industry spent decades transforming chip design through automation, simulation, and electronic design automation. The next decade will be defined by extending those same principles beyond the chip. Advanced packaging, chiplets, high-speed PCBs, multiphysics analysis, and manufacturing-aware optimization are no longer supporting disciplines, they have become the new locus of innovation for AI infrastructure. As compute scales from individual processors to heterogeneous packages, rack-scale systems, and planetary-scale AI factories, competitive advantage will increasingly depend on orchestrating the entire physical computing platform rather than optimizing isolated components. This is precisely the challenge AuraStack AI Super Agent was built to solve. With the introduction of the AuraStack AI Super Agent, Cadence extends its AI Super Agent strategy beyond silicon, bringing AI-native orchestration to advanced packaging and PCB design. The platform coordinates domain-specific AI agents across planning, implementation, and integrated multiphysics analysis, enabling engineering teams to move from fragmented workflows to a unified, intelligent design environment. Grounded in trusted EDA and SDA technologies, high-fidelity simulation, and design intent, AuraStack AI Super Agent enables continuous optimization across electrical, thermal, mechanical, and manufacturing domains. The result is faster design convergence, earlier identification of system-level issues, fewer costly respins, and better product-level optimization across the complete system. With AuraStack AI Super Agent, Cadence now delivers agentic AI super agents across the complete electronic system design flow, from digital and analog silicon implementation to advanced packaging and PCB design. This extends the company's silicon-to-systems vision into an AI-native engineering platform capable of addressing the growing complexity of next-generation computing infrastructure. The next chapter of AI will not be defined solely by more powerful processors or larger models. It will be defined by the intelligence used to engineer the complete systems that connect, power, cool, and integrate them. That future starts beyond the chip. Explore the AuraStack AI Super Agent and its AI-native approach to PCB and advanced packaging design, read the press release , and discover how Cadence is extending agentic AI across the complete electronic system design flow.https://community.cadence.com/cadence_blogs_8/b/pss/posts/the-top-five-reasons-to-use-cradle-cfd-2026-1Wed, 15 Jul 2026 14:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364252Cadence MSC Software/cadence_blogs_8/b/pss/posts/the-top-five-reasons-to-use-cradle-cfd-2026-10If you’ve been weighing whether it’s time to upgrade your CFD software , Cradle CFD 2026.1 makes a very strong case for taking the time and effort to update. This release introduces new physics, new hardware pathways, and new workflow efficiencies that directly affect throughput, cost, and product quality. Here are the top five reasons this upgrade deserves a place on your product development roadmap. 1. Multi-GPU Simulation Without the Memory Ceiling A big update in this release is GPU-native computing in scFAST. Simulations can now scale across multiple GPUs in a single run, removing the memory limits of the previous release. Direct GPU-to-GPU communication adds a further performance boost, and the new architecture supports the latest Blackwell GPUs, with rotating domains handled through a fixed-mesh (MRF) approach. For teams under pressure to shorten design cycles, this translates directly into faster iteration and the ability to tackle larger, more complex models without re-architecting your compute infrastructure. 2. New Physics for Laser Welding Accuracy Manufacturing and process engineering teams working with laser welding now get a meaningful accuracy upgrade. scSTREAM's standard single-phase MARS method has never been able to represent a gas phase, meaning air bubbles trapped in molten metal were effectively invisible to the simulation. A new model based on the adiabatic expansion and contraction of air bubbles changes that, allowing engineers to predict air-pocket formation and tune laser intensity, path, and speed to avoid defects before they happen on the shop floor. 3. A Step Toward AI-Driven Surrogate Modeling The (currently in beta) AI-powered 3D-ROM capability in ODYSSEE lets users treat mesh point coordinates as parameters when generating reduced-order models, enabling surrogate models to account for geometry changes, not just operating conditions. A glider wing that deforms under load, for instance, can be represented in a surrogate model that predicts performance across that deformation. For product leaders exploring digital twins or real-time design exploration, this is an early but important building block toward AI-augmented engineering workflows. 4. Native Linux Post-Processing on the Cluster The new headless scPOST module runs directly on Linux-based HPC systems, eliminating the need to download massive results files just to generate a report. Post-processing can now be performed as a batch export directly from the simulation cluster or from remote storage. This is a meaningful efficiency win that translates to less data movement, less wasted engineer time, and faster turnaround from simulation to decision. 5. Broader Workflow and Accuracy Gains Across the Board Beyond the headline features, 2026.1 delivers a set of practical improvements: an scSTREAM FMI 2.0-compliant co-simulation with more flexible variable support, a non-equilibrium solidification and melting framework for more physically accurate multiphase results in scFLOW, meshing improvements in scFLOWpre for faster model setup from imported meshes, and dynamic electric current calculations in scSTREAM that cut computation time by 35% without sacrificing accuracy. A Forward-Looking Approach to CFD Cradle CFD’s development team is investing in both raw performance and forward-looking capability. For simulation managers focused on throughput and for product leaders focused on innovation velocity, Cradle CFD 2026.1 offers a compelling reason to upgrade now and plan to incorporate future updates as they release to keep on top of the latest improvements in speed, robustness, and efficiency. Learn more about all the updates to Cradle CFD over at SimCompanion .https://community.cadence.com/cadence_blogs_8/b/di/posts/cadence-rtl-design-studio-built-for-the-full-ppac-journeyTue, 14 Jul 2026 17:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364241raquelp/cadence_blogs_8/b/di/posts/cadence-rtl-design-studio-built-for-the-full-ppac-journey0If you've used Joules RTL Design Studio, you already know what it can do. Now it has a name that matches its full potential. We're renaming Joules RTL Design Studio to Cadence RTL Design Studio . The product isn't changing, just the name. Why Is the Name Changing? When Joules RTL Design Studio launched, it expanded upon the Joules RTL Power Solution by adding visibility into performance, area, and congestion alongside power. But the "Joules" name stuck—and with it, the perception that this was primarily a power tool. It isn't. It never was just power. Cadence RTL Design Studio is a full PPAC solution. It gives front-end designers early, accurate insight into power, performance, area, and congestion—all before handoff to implementation. The new name makes that clear from the get-go. What It Does Cadence RTL Design Studio delivers up to 5X faster RTL convergence and up to 25% improvement in quality of results (QoR) by bringing physical design feedback to the RTL stage—where changes are fastest and cheapest to make. Key capabilities include: Full PPAC visibility at RTL – Identify timing, congestion, power, and area issues early, before they become costly implementation problems. Intelligent RTL debugging assistant – An expert system that triages violations, explores what-if scenarios, and provides actionable guidance to resolve issues directly in the source code. Proven engine accuracy – PPAC estimates are driven by the same trusted engines as Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, so designers can trust that RTL-stage decisions will track with production implementation. Unified cockpit – A single GUI for RTL analysis, schematic cross-probing, layout feedback, and design exploration. AI-powered design exploration – Integration with Cadence Cerebrus ® Intelligent Chip Explorer enables generative AI-driven exploration of floorplan optimization, frequency vs. voltage tradeoffs, and more. Prototyping support – Designers can explore and prototype design decisions prior to committing to place and route, reducing costly late-stage iterations. The Bigger Picture For too long, RTL designers operated separately from implementation engineers. Problems that could have been identified and resolved quickly during the RTL phase were instead found later, causing costly revisions and delaying product release. Cadence RTL Design Studio closes that gap. It shifts left the visibility and intelligence implementation teams have always had, putting them directly in the hands of front-end designers at the moment they're most useful. The name change goes beyond appearance; it indicates that this tool supports the entire PPAC process—from initial RTL design to final production implementation. Learn more about Cadence RTL Design Studio . The product formerly known as Joules RTL Design Studio is now Cadence RTL Design Studio. No changes are being made to the product at this time.https://community.cadence.com/cadence_blogs_8/b/di/posts/the-truth-about-design-for-testability-flow-what-most-engineers-missTue, 14 Jul 2026 05:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364209KShubham/cadence_blogs_8/b/di/posts/the-truth-about-design-for-testability-flow-what-most-engineers-miss0Design for Testability is a critical step in achieving high-quality silicon. In this Training Bytes blog, we are going to explore implementing an efficient DFT flow using the Genus Synthesis Solution, covering key concepts such as synthesis with test, scan insertion, test readiness, and preparing your design for ATPG with Modus and for fault diagnostics. Synthesis with DFT In this section, we introduce the DFT implementation flow using the Genus Synthesis Solution. These videos focus on preparing your design for test by integrating DFT architectures early in the flow. Ever wonder how DFT fits seamlessly into your synthesis flow? Check out our short byte on YouTube titled: A Design with Test Circuit where you can explore your design with test structures. Adding test structures in your design requires some Basic DFT Rule Checks . The intent of these checks to ensure the elements put in the scan chains are shifting data properly. DFT isn’t just an added step, it is the backbone of test-ready design. To make the design test ready, you need to fix violations; for example, Fixing Asynchronous Set and Reset Pin Violations. You can also run the DFT rule checker and fix the DFT Violations on a Scan-Mapped Design at any stage in the synthesis with DFT Flow. To increase the coverage of your design, Insert Test Points Manuall y during synthesis. You can also Insert Shadow Logic Around the Untestable Logic to increase the design’s controllability and observability. To access the functional ports of your chip independent of system logic, Insert the Boundary Scan Architecture in your design. You can also learn to add other test structures, such as Memory Built-In-Self-Test (MBIST) and Logic Built-In-Self-Test (LBIST). See our YouTube videos: What is MBIST and What is Logic BIST. ATPG Flow with Modus DFT Software Once your design is synthesized and includes the test architecture, you can seamlessly handoff to the Cadence Modus DFT Software solution to run the Automatic Test Pattern Generation ATPG flow. See the following steps and embedded links to the respective topics: To understand Modus ATPG Flow Steps and its Graphical User Interface , watch the embedded video. The first step is creating a Modus model, defined by Build Model . It does this by reading the design netlist and reading the structural library files combining together to create a design image. This model will be used for all further steps in the ATPG flow. You can also build the test mode to set up the device for testing, as described in: What Is Test Mode. To update the global fault list faults detected in the design, watch the video: What Is the Commit Experiment ? If you are curious about writing the industry standard test vector, click on the embedded link and watch the video ATPG Vector Generation and Writing the Patterns. You can also debug the broken scan chains in your design by Debugging Broken Scan Chains using the Modus GUI or How to Debug Broken Scan Chains using Tcl Interface in Modus DFT? Diagnostics with Modus DFT Software Once your test patterns are generated, the real challenge begins—diagnosing manufacturing defects and identifying faults. Modus Diagnostics assists in identifying the root causes of defects in manufactured digital semiconductor devices. Identifying the root cause facilitates corrective actions to avoid future defects and improve product yields. The Modus Test Diagnostics Overview is a good resource to start with. Because there is no industry standard, failures from Automated Test Equipment (ATE) are reported in a variety of ASCII formats. You can convert your Tester Fail Data to Chip Pad Pattern CPP Format. Modus has established a simple input Failure Format Called Chip Pad Pattern (CPP) file. Once you Read the Tester Failure Data into binary format, you start diagnosing the failures in your design. With Modus diagnostics capabilities, you can Diagnose Single/Multiple Manufacturing Defects in the functional logic of the chip, select all the faults in the logic back cone of the flops, then perform fault simulation and compare the results. Modus DFT Software provides a wrapper that allows you to execute all steps, including determining if the failures are on Logic or Scan patterns, in one command. You can get more information by watching this Demo. For more such videos and training bytes, login to Cadence Learning and Support Portal. For technical shorts, subscribe to Cadence's official YouTube Channelhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/why-10base-t1s-automotive-ethernet-soc-verification-needs-more-than-simulationTue, 14 Jul 2026 04:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364230Vinod Khera/cadence_blogs_8/b/fv/posts/why-10base-t1s-automotive-ethernet-soc-verification-needs-more-than-simulation0Cadence Multi-Platform Verification improves functional coverage and verification time The recent advancements in the automotive industry, such as ADAS/AV, and infotainment all depend on reliable in-vehicle communication. To keep up with the high-speed, low-cost, and optimized EMC and weight constraints, the automotive industry is moving from legacy buses to automotive ethernet, with 10BASE-T1S , ethernet sub systems emerging as a key technology for shared, multidrop connectivity. These subsystems must support diverse multidrop configurations while interacting reliably with safety-critical domains such as ADAS and zonal controllers. However, such advancements have led to increasing challenges for design teams, as they face issues verifying these 10BaseT based networking subsystems thoroughly enough to guarantee no surprises in silicon. In addition, as protocols expand and multidrop topologies emerge, traditional single‑platform verification (simulation) methods struggle to deliver sufficient coverage and timely signoff and guarantee. The STMicroelectronics team was also facing the same issue. This blog post explores how the team verified a 10BASE-T1S automotive ethernet subsystem using a Cadence tools-based multi-platform verification, which unifies simulation, emulation, and formal verification techniques. At CadenceLIVE Silicon Valley 2026, the STMicroelectronics team showed how this approach improved functional coverage by 15% and reduced verification cycle time by 40% versus a simulation-centric flow. Why 10BASE-T1S Matters in Automotive Networks Traditional in-vehicle networks have relied on buses such as CAN, CAN FD, LIN, and FlexRay. Each served an important role, but together they added complexity. ECUs often had to support multiple bus types, software stacks became harder to manage, and additional wiring and connectors increased system weight and potential points of failure. 10BASE-T1S changes that equation. It enables automotive ethernet over a twisted-pair copper connection and supports multidrop network topologies. In the STMicroelectronics presentation, one of the central advantages was the ability to reduce the number of bus interfaces an ECU must support while also reducing wiring complexity. The optional power-over-data-line capability further strengthens the value proposition by allowing the same cable to carry both data and power where applicable. A key technical feature is physical layer collision avoidance (PLCA), and provides a collision free access on a shared bus. PLCA provides deterministic access to each node and ensures that it uses the entire 10 Mbps bandwidth. The working principle of PLCA is that transmit opportunities on a mixing segment are granted in sequence based on a node ID unique to the local collision domain (set by the management entity). Each node gets a fair opportunity to transmit, and each transmission is completed before the next node takes the bus. This creates the deterministic, collision-free behavior required for shared-bus automotive communication. The Verification Challenge: New Protocol, Complex SoC, No Room for Surprises For STMicroelectronics, the challenge was not simply verifying an ethernet block in isolation. The subsystem sat inside a broader SoC context with multiple CPU groups, multiple cores, AXI masters, memories, a network-on-chip, bus-width adaptation logic, and multiple Ethernet-related paths. Ethernet traffic moved through the NOC, into memory, and ultimately toward CPU processing. That system context made end-to-end behavior just as important as protocol correctness. The team faced three core challenges. The 10BASE-T1S, PLCA, and three-pin interface specifications are relatively new and still evolving. With several gray areas, the team had to rely on best practices and close collaboration to interpret the spec consistently. As multiple clocks, multiple CPU cores, several ethernet instances, and multidrop scenarios all had to work together, verifying collision-free communication across a shared bus added another layer of difficulty. Simulation alone is not enough. The sheer breadth of scenarios, from functional checks to performance under heavy traffic to precise timing, demanded more than a single verification engine could deliver efficiently. These challenges called for a structured, multi-platform verification strategy rather than a simulation-centric approach. A Multi-Platform Verification Methodology To address these challenges and uphold the "no surprises, later in silicon" objective, the STMicroelectronics team implemented a multi-platform flow leveraging Cadence tools. This platform used ethernet verification IP for simulation, Palladium for emulation, and formal verification. Cadence Ethernet VIP for comprehensive functional level verification Palladium-based emulation for SoC scenarios and performance scenarios Formal verification is employed to verify ED pulses and timing-related checks This combined methodology provides detailed protocol-level control and debugging, enables large-scale SoC and software scenario testing via emulation, and delivers precise timing assurance through formal methods. Collectively, these platforms offer a holistic view of the subsystem, surpassing the capabilities of any single engineering approach. Cadence Ethernet VIP also played a central role in accelerating the verification environment, reducing the time to almost a week compared to a month during the first project's bring-up. That improvement reflected both methodology reuse and close collaboration between STMicroelectronics and Cadence around protocol interpretation, VIP integration, and feature enablement for areas such as PLCA and multidrop operation. Coverage-Driven Verification Across Engines A critical strength of the flow was coverage continuity. Cadence Ethernet VIP provided built-in monitors, checkers, and coverage, including instance-based functional coverage that could be extended by the user. This was important because the design included multiple Ethernet nodes, and future designs could scale even more Ethernet instances. Instance-based coverage helped the team understand progress at the node level rather than only at the aggregate level. The team verified register access, frame transmission and reception, reset and configuration commands, half-duplex operation, PLCA mode, multidrop scenarios, low-power behavior, and sleep commands. In the simulation, more than 40 directed and random tests were used for IP verification. In emulation, the team exercised stressed multi-frame scenarios and performance-oriented cases. In formal, assertions were used to verify the ED pulse width and timing behavior. Key Metrics: Earlier Bug Discovery and Stronger Silicon Confidence The outcome was measurable, and the results tell a clear story. STMicroelectronics reported 97.2% toggle coverage, 94% code coverage, 90% branch coverage, and 95% coverage for PLCA and three-pin specific bins in functional coverage. The team also achieved nearly 100% toggle coverage at the SoC level in the formal context described in the presentation. Just as important, the flow helped find issues early in the SoC verification process. By applying the right engine to the right class of problem, VIP-based simulation for functional behavior, Palladium emulation for software-driven and performance stress, and formal verification for precise timing checks, the team improved confidence before tapeout and avoided silicon respins. The Takeaway STMicroelectronics’ CadenceLIVE Silicon Valley presentation showed a practical path for verifying a new class of automotive Ethernet subsystem. 10BASE-T1S offers significant system advantages for in-vehicle networking, but it also introduces verification requirements spanning protocol behavior, SoC integration, multidrop arbitration, software-driven traffic, and timing-sensitive interface checks. By using Cadence Ethernet VIP, Palladium emulation, and formal verification in a coordinated multi-platform flow, STMicroelectronics accelerated bring-up, improved coverage, exposed issues earlier, and moved toward silicon with greater confidence. For automotive design teams facing the next generation of Ethernet-based in-vehicle networking, that is the real value of multi-platform verification is fewer gaps, faster learning, and fewer surprises in silicon. Want to learn how STMicroelectronics achieved these results? Watch the full CadenceLIVE Silicon Valley 2026 presentation, “ From Protocol to Silicon: Multiplatform Verification of 10BASE-T1S in Automotive Ethernet SoCs ” by Bipul Haldar, Asjad Fahmi, Sahana Sanagowda from STMicroelectronics, and Krunal Patel from Cadence.https://community.cadence.com/cadence_blogs_8/b/cfd/posts/how-fidelity-cfd-improves-hydraulic-turbine-performance-predictionTue, 14 Jul 2026 03:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364237Veena Parthan/cadence_blogs_8/b/cfd/posts/how-fidelity-cfd-improves-hydraulic-turbine-performance-prediction0Francis-99 Hydraulic Turbine (Trivedi, 2026) Accurately predicting the performance of hydraulic turbines requires more than a steady-state efficiency estimate. Engineers also need insight into how the machine behaves away from its best efficiency point, where unsteady flow structures, rotor-stator interaction, and draft-tube instabilities can affect both performance and stability. This is where a high-fidelity computational fluid dynamics (CFD) workflow becomes especially valuable. This blog summarizes a detailed simulation study of the Francis-99 benchmark case using Fidelity CFD software, showcasing how GPU-accelerated steady and unsteady CFD can be used to predict the hill chart, evaluate part-load behavior, and identify a turbulence model that accurately predicts flow behavior for reliable hydraulic turbine analysis. Building a Simulation Workflow for Complex Hydraulic Turbine Flows The Francis-99 turbine is a well-known benchmark case with experimental data available from workshop studies for validation against the CFD simulation results. The simulation uses a mixed meshing strategy to balance topological control and geometric flexibility. Structured meshes generated with Fidelity Autogrid are applied to the guide vanes and runner, where periodicity, blade shape, and high mesh quality are critical. Unstructured meshes generated with Fidelity ANSA are used for the inlet spiral and draft tube, where geometry is more complex and a structured topology is less practical. This combination allows the solver to maintain accuracy in the blade passages while keeping the workflow manageable in the surrounding stationary components. The steady-state setup includes mass-flow inlet conditions, mixing planes at rotor-stator interfaces, periodic boundaries, and an outlet opening to accommodate backflow at selected operating points. From Hill Chart Prediction to Part-Load Physics For steady-state simulation, the workflow is used to compute the hill diagram across multiple guide vane angles and rotational speeds. The results capture both the location of the best efficiency point and the shape of the efficiency isocurves in strong agreement with the available experimental data. A slight overprediction of efficiency is observed, which can be attributed to disk-friction losses not included in the computational model. From an engineering standpoint, this is an important result: it shows that CFD can reliably reproduce global turbine performance trends while also clarifying which modeling assumptions influence the final comparison. Under part-load operating conditions, the flow becomes increasingly unsteady, and the limitations of a steady-state approach become more apparent. As a result, transient simulations are required to accurately capture the complex flow structures and associated performance characteristics in these regimes. Capturing Rotor-Stator Interaction and Draft-Tube Instabilities To analyze part-load behavior, the simulation is extended to a full-wheel model with all guide vanes included so that rotor-stator interaction can be resolved directly. A sliding grid is used between rotating and stationary domains, and the transient setup is evaluated with multiple time steps. This comparison shows that although a coarse time step may capture some dominant frequencies, it fails to resolve the full range of flow physics. In this case, the one-degree time step resolves more unsteady flow features and avoids the artificial frequency behavior seen with coarser settings. The study also compares three turbulence models—shear stress transport (SST), explicit algebraic Reynolds stress model (EARSM), and scale-adaptive simulation (SAS). While SST provides a strong baseline and the EARSM improves anisotropy representation, SAS is the only model that accurately captures large-scale unsteadiness, such as the vortex rope and its frequency in the draft tube. Probe-based frequency analysis, along with Q-criterion and swirling-velocity visualizations, shows that SAS better resolves the coherent unsteady structure expected under partial-load conditions. How This Workflow Supports Turbomachinery Design and Analysis This benchmark demonstrates a practical CFD workflow that engineers can use to accurately predict both turbine performance and the underlying flow structures, including challenging off-design operating conditions. The study highlights how key modeling decisions — such as mesh strategy, turbulence-model choice, etc. — directly influence the ability to capture not only global performance metrics but also the complex flow phenomena responsible for efficiency losses, instabilities, and part-load behavior. In this study, steady-state operating points were solved in minutes on the GPU, and even the unsteady Reynolds-Averaged Navier-Stokes (URANS) simulations—covering 40 full runner revolutions—were completed in about 10 hours, showing that both steady and unsteady hydraulic turbine analyses can fit within practical engineering timelines. Frequently Asked Questions ⇒ How do you decide whether to use Fidelity Flow or Fidelity Charles Solver for a turbomachinery simulation? Use Fidelity Flow when you need rapid, structured, GPU-enabled CFD for early design exploration, performance mapping, and efficient turnaround. Use Fidelity Charles when the problem involves complex off-design physics, strong unsteadiness, or separated flow that cannot be resolved with sufficient fidelity using RANS or URANS approaches. ⇒ Why use a mixed structured–unstructured workflow in turbomachinery CFD? A mixed workflow helps balance mesh quality, geometric flexibility, and simulation cost. Structured meshes are well-suited for blade passages where topological control and periodicity are important, while unstructured meshes are more practical for geometrically complex regions such as the inlet spiral and draft tube. ⇒ Why is full-wheel meshing necessary for off-design rotor-stator interaction analysis? Full-wheel meshing is needed when the goal is to resolve rotor-stator interaction, because reduced periodic sectors may suppress important circumferential interactions. In this case, the full runner and all guide vanes were meshed, increasing the total mesh size to about 37 million cells. ⇒ How do SST, EARSM, and SAS differ for turbomachinery off-design simulations? SST is the standard baseline turbulence model and is widely used for steady-state performance prediction. EARSM improves the representation of turbulence anisotropy, which can be important in complex turbomachinery flows. SAS extends SST by enabling the resolution of large-scale unsteady structures, making it more suitable for capturing phenomena such as vortex rope behavior. ⇒ How does time-step size affect rotor-stator interaction capture in unsteady URANS? Time-step size directly affects how well transient blade-row interactions are resolved. In this case, a five-degree time step was too coarse and introduced aliasing, whereas a one-degree time step resolved more of the unsteady content and was chosen to capture both rotor-stator interaction and low-frequency flow phenomena. Reference Trivedi, C. (2026). Francis-99 workshop 1: Steady state operation [Data set]. Francis-99 (V1). DataverseNO. https://doi.org/doi:10.18710/HKQ2RF Watch the on-demand webinar Advanced CFD for Francis Turbines: Hill Chart Prediction and Part-Load Analysis by Margarita Campos to see the complete Francis turbine CFD workflow in action—from hill chart validation and transient setup to probe-based frequency analysis and draft-tube visualization.https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/how-the-new-ask-ai-assistant-makes-support-more-seamlessTue, 14 Jul 2026 03:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364245Corporate/cadence_blogs_8/b/corporate-news/posts/how-the-new-ask-ai-assistant-makes-support-more-seamless0Finding the right answer often takes more than one question. Users may start with a broad query, add details, clarify the issue, or ask a related follow-up before reaching what they need. The new ASK AI Assistant is designed for this kind of natural, connected support experience. With session-based context retention, the assistant can understand follow-up questions based on the ongoing exchange until the page is refreshed. Users can build on an earlier answer, narrow the scope of their query, or shift to a related issue without starting over. Whether the question is about licensing, account access, product details, or support options, the experience stays connected and intuitive. With the assistant available across Cadence ASK web pages, users can get timely support while staying focused on the task or information they are exploring. Behind the assistant is a large, carefully curated knowledge base developed by Cadence engineers using award-winning knowledge management practices. Dedicated efforts have been put into making this knowledge base Gen AI-ready, so the assistant can draw on high-quality, structured information. Its relevance threshold is carefully calibrated to prioritize accuracy over generating “just any” answer, and responses are supported by citations so users can review the source context with confidence. The result is a support experience that simplifies finding information while maximizing the overall value of each interaction, ultimately leading to a more satisfying user experience. Ready to try the new ASK AI Assistant? Log in to the new ASK portal to experience the features of the new AI Assistant discussed in this blog. For more details on the latest features and updates in the new ASK portal, read The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experiencehttps://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/you-ll-still-do-the-work-you-just-won-t-do-the-boring-partMon, 13 Jul 2026 16:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364248Corporate/cadence_blogs_8/b/artificial-intelligence/posts/you-ll-still-do-the-work-you-just-won-t-do-the-boring-part0Agentic AI is about to change your flow. Here's what actually shifts—and why the engineers who move first will pull away from the ones who wait. It's 11 p.m. The overnight regression failed—again—and you're three hours into triaging waveforms to find the one signal that went sideways. Tomorrow you'll hand-edit the same constraint file for the 40th time, rerun the flow with one parameter changed, and copy the results into a tracker nobody reads. None of this is why you got into chip design. It's just the connective tissue between the decisions that actually need your judgment. Now imagine that connective tissue handled for you—the triage, the reruns, the testbench grind—while you stay focused on the parts that need an engineer's mind. That's the promise of agentic AI, and it's closer than the hype cycle makes it sound. Start with the distinction that matters. A copilot answers when you ask. An agent takes a goal, makes a plan, calls your tools, implements the steps, and returns a result for you to check. The difference between "explain this timing violation" and "go close these violations and show me what you changed" is the whole ballgame. Why Now: This Is Becoming an Implementation Advantage Here's the part worth sitting up for. Chip complexity is outpacing the number of engineers available to handle it—the industry is staring down a talent gap of over a million people by 2030 , and demand for senior design talent already outstrips supply. As Forbes put it, silicon complexity is outpacing engineering scale even at NVIDIA's headcount —autonomy is shifting from a nice-to-have to an existential one. This isn't theoretical anymore. At Computex 2026, Cadence and NVIDIA unveiled a Level-5 autonomous ChipStack AI Super Agent, accelerated by NVIDIA Nemotron . In NVIDIA's own design environment, it closed the entire verification loop in under a day: 40X Faster Verification NVIDIA's Level-5 ChipStack AI Super Agent completed the full verification loop in under a day—a 40X leap beyond the 10X reported just months earlier. Not a slide-ware demo: a working engineering collaboration on production-grade RTL. (Computex 2026; reported by Forbes.) Sit with what that means competitively. When one team closes verification in a day, and another still measures it in weeks, that's not a 10% edge—it's a different speed of business. The implementation gap between early adopters and the wait-and-see crowd is going to be enormous—and it's only going to compound. Adopting early isn't about chasing a trend. It's about not getting lapped. So what does that actually mean for your flow? Three things matter most. You Move from Operator to Orchestrator A huge fraction of your day goes to running the flow—kicking off regressions, hand-editing constraints, babysitting jobs, and copy and pasting results. None of it is why you became an engineer. It's the busywork between the decisions that require judgment. Agentic AI targets exactly that. Instead of implementing each step yourself, you define the intent —the goal, the constraints, the guardrails—and supervise agents that carry it out. You're not pushing every button; you're directing the work and reviewing what comes back. This is what people get wrong when they panic about AI "replacing engineers." You're not removed from the loop—you're moved up it, from the person typing commands to the person deciding which commands are worth running and whether the answer holds. That's not a smaller job. It's a more senior one, available to you regardless of title. Correctness, quality, the tradeoffs, the signoff—all still yours. The mechanical implementation underneath gets handled. You Stay in Control—Agentic Doesn't Mean Autonomous-and-Gone Every good engineer asks the right question first: "So it just… does things? Without me?" No. The useful version is built around human-in-the-loop by design. You decide what an agent does on its own and what needs your signoff. Routine, low-risk, easily-verified work—regression triage, first-pass setup, debug data gathering, documentation—can run with a light touch. The weighty calls—architecture, tradeoffs, anything touching tapeout—stay gated behind your review. In NVIDIA's Level-5 deployment, the agent runs the workflow with little human involvement, but engineers still inspect, guide, and collaborate as needed. That's the model: supervised autonomy, not a switch you flip and walk away from. And because semiconductors have no margin for error , the verification story matters as much as the automation. The credible approach keeps agents anchored to physics-based design and signoff-accurate engines—grounded in proven computational models rather than letting a language model freelance. An agent that can't show its work isn't ready for your flow. The good ones know it. The Skills that Make You Valuable Shift—in Your Favor If less of your day is spent on manual implementation, what fills the gap? More of the work that was always the interesting part. The emerging skills aren't exotic—they're things good engineers already do informally: decomposing a fuzzy problem into clear steps, expressing intent precisely, knowing when a result smells wrong, and deciding when to trust an output versus dig in. Add a working sense of how to supervise an agent—where it's strong, where it's weak, when to step in—and you've described the engineer who gets the most leverage from these tools. Notice what's not on that list: you don't need to become an AI researcher, and you don't abandon your domain expertise. The opposite. Your deep knowledge—of the design, the corner cases, the "we tried that in 2019 and here's why it broke"—becomes more valuable, because it's exactly the judgment an agent can't supply. The automation handles volume and tedium; you supply the experience that separates a good result from plausible-looking garbage. Agentic AI doesn't commoditize the engineer. It amplifies the one who understands the problem. Your Flow Today vs. with Agentic AI Same responsibilities. Different distribution of where your hours go. Your Flow Today With Agentic AI Manually kick off regressions and babysit jobs for hours Agents launch, monitor, and triage regressions—you review the findings Hand-edit the same constraint files and setups, run after run Agents generate first-pass constraints and setups from your intent Debug waveforms line by line at 11:00p.m. Agents surface root-cause hypotheses and debug hints—you make the call Write the 400th testbench by hand Agents draft RTL and testbenches from the spec—you verify Copy and paste results into trackers Agents compile results and metrics automatically Your hours go to implementation Your hours go to architecture, tradeoffs, and signoff The Takeaway You'll still own your designs. You'll still make the calls that matter. You'll still be the engineer. You'll just spend far less of your week on the tedious, high-volume, error-prone busywork that never deserved your attention—and far more on the problems actually worth an engineer's mind. That's not a threat to your job. It's the most interesting version of it. The only real question is whether you start learning to work this way now—while it's an advantage—or later, when it's just catching up. See what an agentic flow looks like in practice—from spec to verified design: Cadence AI for Design Sources: Cadence/NVIDIA Level-5 ChipStack AI Super Agent, Computex 2026 (40X verification), reported by Forbes, Jun 2026; Cadence AI infrastructure proven across 1,000+ tapeouts, Forbes, Feb 2026.https://community.cadence.com/cadence_blogs_8/b/fv/posts/understanding-pcie-6-0-power-state-l0p-vs-l0s-vs-l1Mon, 13 Jul 2026 06:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364247mrana/cadence_blogs_8/b/fv/posts/understanding-pcie-6-0-power-state-l0p-vs-l0s-vs-l10PCI Express has always focused on a single goal: maximizing performance while minimizing power. However, with PCIe 6.0, maintaining this balance has become far more challenging. With PAM4 signaling in PCIe 6.0, link power is no longer a secondary concern—it is now a first-order design constraint. The PHY consumes significantly more energy, and modern workloads generate traffic patterns characterized by bursts of multiple flits rather than continuous transfers. This is where PCIe 6.0 introduces a major shift in power-state strategy: the real battle is no longer between L0 and L1—it is between L0p, L0s, and L1. In this blog, we explore how these states differ, why PCIe 6.0 changes the rules, and which one matters most moving forward. Why Power States Matter More in PCIe 6.0 PCIe 6.0 doubles bandwidth compared to PCIe 5.0. While PCIe 5.0 relies on NRZ signaling, PCIe 6.0 adopts PAM4 , along with  Forward Error Correction (FEC)  and  FLIT mode  to achieve higher throughput. However, these advancements come at a cost: Increased PHY power consumption Higher equalization complexity Greater idle-to-active power overhead In this environment, remaining in L0 (fully active) during idle gaps becomes inefficient. Yet, modern workloads, especially in accelerators, AI, and storage systems consist in  frequent micro-idle periods . Therefore, PCIe 6.0 requires power states capable of responding  within microseconds , without compromising throughput or latency. PCIe Link Power-State Landscape PCIe defines multiple link states within the  LTSSM (Link Training and Status State Machine) . The most relevant states for active and idle operation are: State Meaning Depth Wake Latency L0 Fully active None 0 L0s Shallow standby Light sleep Low L1 Deep idle Heavy sleep Higher L0p Low-power active (6.0+) New hybrid Near-zero PCIe 6.0 introduces  L0p  because neither L0s nor L1 alone can effectively handle modern workload demands. L0s: The Legacy “Quick Idle” State L0s was introduced as a fast idle state for short inactivity periods. In L0s, the transmitter may stop sending symbols, the receiver stays partially ready, and the link is still logically active. But Why Did L0s Work in Older Generations? Because in previous generations the PHY power was manageable, the traffic/data patterns were simpler, and the wake latency requirements were relaxed. L0s provided moderate savings without much complexity. But L0s turn out to be limited to PCIe 6.0. At PAM4 as the equalization must remain stable, the continuous readiness becomes expensive. So L0s does not reduce enough PHY power to justify its use. So, the PCIe 6.0, L0s becomes less effective. How About L1? Let us understand L1 now. L1 is a deeper, low-power idle state. In L1, most of the link circuitry powers down, and the exit requires a more involved wake sequence. Though it’s beneficial in terms of significant power savings and is ideal for long idle durations, it has higher exit latency and can disrupt low-latency fabrics (e.g., CXL) The m odern PCIe traffic which consists of b urst transfer and m icro-idle gap , If the link enters L1 too aggressively, the w ake overhead will hurt performance and will cause the l atency-sensitive traffic to suffer . So PCIe 6.0 needs something between L0 and L1. Hence L0p Was Introduced L0p (Low Power L0) is a new PCIe 6.0 link state designed to reduce power while keeping the link operational and responsive. It is best described as: “Active mode, but PHY-optimized.” L0p sits between: L0 (full activity) L1 (deep sleep) In L0p, the link remains logically active, some portions of the PHY can be powered down, lane width may be reduced dynamically, and the exit latency is near-zero compared to L1. This makes L0p ideal for short idle gaps. L0p vs L0s vs L1: Key Comparison Feature L0s L1 L0p Introduced Earlier PCIe gens PCIe baseline PCIe 6.0 Target Idle Duration Very short Long Short-to-medium Power Savings Low- moderate High Moderate- high Exit Latency Low High Very low PHY Power Reduction Limited Strong Significant Best for 6.0 PAM4? Not really Sometimes Absolutely Supports Burst Workloads Partial Poor Excellent One unique PCIE 6.0 capability is that L0p may support dynamic link width changing. L0p supports: x16 → x8 → x4 downsizing during idle gaps. Maintaining at least one active lane Restoring full width instantly when traffic returns This is a major step toward the power aware of PCIe fabrics . So, in PCIe 6.0 systems, the emerging hierarchy is that L0 for full traffic, L0p for burst idle gaps, L1 for extended inactivity, and L0s becomes increasingly irrelevant. PCIe 6.0 changed the power management equation. L0 is too expensive to stay in during idle gaps; L1 saves power but adds latency, and L0s is no longer sufficient for PAM4 PHY power. Hence L0p fills the critical missing middle. L0p is not just another low-power state. As PCIe evolves toward Gen 6.0 and forward and on CXL fabrics, L0p will become foundational for more output for less power. To learn more about Cadence solutions for PCIe and CXL verification, explore these resources: VIP for PCI Express TripleCheck Test Suite For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website If you have more feedback or need more information, reach out to us at talk_to_vip_expert@cadence.comhttps://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/how-cadence-and-tsmc-are-accelerating-ai-silicon-design-at-advanced-nodesMon, 13 Jul 2026 00:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364244Corporate/cadence_blogs_8/b/corporate-news/posts/how-cadence-and-tsmc-are-accelerating-ai-silicon-design-at-advanced-nodes0Designing AI silicon for increasing AI/HPC workloads at advanced nodes has become one of the toughest challenges in the semiconductor industry. Escalating goal-driven PPA, reliability, and productivity-optimization demands are converging as development cycles continue to compress. At advanced nodes, even small inefficiencies can lead to costly design iterations, schedule slips, and delayed market entry. To address these challenges, Cadence and TSMC have expanded their collaboration, focusing on accelerating the AI-driven semiconductor innovation through advanced design flows for leading-edge AI silicon. This post opens a four-part series exploring how the expanded Cadence–TSMC collaboration helps accelerate AI silicon design innovation. It frames the collaboration at advanced-node design to reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs—accelerating time to silicon with greater confidence. In the posts ahead, we’ll look more closely at the role of certified flows and signoff-ready methodology, the importance of silicon-proven IP, the latest enablement across advanced nodes, including TSMC’s N3, N2, A16 TM , and A14, and the customer momentum already underway at 3nm and 2nm. Expanding a Longstanding Cadence–TSMC Collaboration As compute demands expand across IoT, smartphones, AI, HPC, and automotive applications, mutual customers need to design efficiently and confidently on TSMC’s cutting-edge technologies and advanced packaging platforms. The long-standing Cadence collaboration with the TSMC Open Innovation Platform® (OIP) ecosystem directly addresses this need by delivering certified digital, analog, and signoff solutions that meet required design criteria while helping improve power, performance, area, and productivity at TSMC advanced process technologies. Through partnership with TSMC, Cadence is advancing its “Design for AI and AI for Design” strategy to reduce time-to-silicon and time-to-revenue by combining certified EDA flows, silicon-proven IP, agentic AI technologies, and accelerated computing as a workforce multiplier. The collaboration spans the full design lifecycle, from front-end synthesis through implementation, multiphysics analysis, and signoff. It will help customers reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs, accelerating time-to-silicon with greater confidence. Working with TSMC, Cadence is making design flows, optimization engines, and signoff infrastructure “agent-ready,” so AI systems can combine domain reasoning with physics-based analysis to drive convergence for designs at TSMC advanced process technologies. Certified Design Flows to Reduce Iterations and Accelerate Time to Market At advanced nodes, design iterations are increasingly expensive, and gaps in correlation between implementation and signoff can quickly derail schedules. A central focus of the Cadence–TSMC collaboration is the delivery of TSMC‑certified, end‑to‑end EDA flows that improve consistency and predictability throughout the design process. These TSMC-certified flows help teams converge earlier on tapeout‑quality results by reducing late‑stage surprises and minimizing rework or design iterations. Cadence introduced early detailed routing technology to enable improved correlation between early exploration and final signoff, delivering more predictable closure of performance, power, and reliability targets for advanced AI and HPC designs. This approach is especially critical for DTCO‑focused environments, where tight coordination between design and process is essential. Cadence collaborated with TSMC to develop completely new implementation and signoff flows to support new advanced node innovations, such as backside power routing. End-to-End, Signoff-Ready Methodology for AI Silicon Modern AI silicon designs increasingly span digital logic, custom and analog circuitry, power and signal integrity, thermal and electromagnetic effects, and heterogeneous integration. To support this complexity across SoC design, Cadence and TSMC deliver a signoff‑ready, end‑to‑end design methodology aligned with the requirements of advanced AI and HPC applications. This methodology integrates: Digital implementation ( Innovus Implementation System ) Custom and analog design and simulation ( Virtuoso Studio and Spectre Simulation Platform ) Signoff technologies, including Tempus Timing and ECO Solutions, Quantus Extraction Solution , Liberate Characterization Portfolio , and Pegasus Verification System Thermal analysis, power integrity, and electromagnetic analysis with Celsius Thermal Solver , Voltus IC Power Integrity Solution , and EMX Planar 3D Solver Additionally, the Genus Synthesis Solution is enabled for TSMC process technologies and ongoing collaboration is under way on Clarity 3D Solver . By unifying these capabilities within certified methodologies, the collaboration supports predictable convergence from architecture through signoff, helping teams manage advanced‑node complexity with greater confidence. Complementing the flows is Cadence’s silicon‑proven IP portfolio for advanced nodes, including high‑bandwidth memory and high‑speed interface technologies tailored to AI system requirements. Focus on Advanced Nodes: TSMC’s N3, N2, A16 TM , and A14 The expanded collaboration spans multiple advanced process generations, enabling continuity as customers plan multi‑generation AI roadmaps. N3: Cadence delivers certified end-to-end flows, and Cadence’s Artisan foundation IP advanced‑node portfolio is in production designs using TSMC N3 process technologies N2: Cadence delivers certified end‑to‑end EDA flows and a rich silicon‑proven IP portfolio optimized for TSMC N2P A16 TM : Cadence’s digital, custom/analog, and signoff platforms are certified for TSMC A16, supporting advanced AI and HPC designs A14: Cadence and TSMC are engaged in ongoing collaboration on TSMC A14 PDK enablement to accelerate future convergence toward tapeout‑quality results Across these nodes, Cadence and TSMC are aligning certified methodologies and design infrastructure, helping customers adopt advanced processes with reduced risk. Customer Momentum at 3nm and 2nm Strong customer adoption underscores the impact of the expanded Cadence–TSMC collaboration. Across the AI and HPC ecosystem, companies are actively designing silicon on TSMC’s 3nm and 2nm technologies, leveraging certified flows and silicon‑proven IP. This momentum reinforces the importance of signoff‑ready, end‑to‑end infrastructure in enabling faster, more confident delivery of next‑generation AI silicon at advanced nodes. Accelerating AI Silicon Design with Greater Confidence As AI and HPC workloads continue to push the limits of semiconductor design, success at advanced nodes depends on reducing design iterations, improving correlation, and enabling predictable execution across the full design lifecycle. Through their expanded collaboration, Cadence and TSMC are delivering the certified, end‑to‑end foundation required to meet these demands, supporting advanced AI silicon across TSMC’s N3, N2, A16 TM , and A14. With strong customer momentum already underway at TSMC’s 3nm and 2nm technologies, the collaboration is helping semiconductor teams accelerate innovation and bring next‑generation AI silicon to market with greater confidence. Learn more about the expanded Cadence–TSMC collaboration in the next blog post on the importance of silicon-proven IP from Cadence that helps reduce integration uncertainty, improve correlation between implementation and signoff, and support smoother convergence toward tapeout.https://community.cadence.com/cadence_blogs_8/b/pss/posts/everything-to-look-forward-to-in-actran-2026-1Fri, 10 Jul 2026 23:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364246Cadence MSC Software/cadence_blogs_8/b/pss/posts/everything-to-look-forward-to-in-actran-2026-10Cadence has released Actran 2026.1 , and this version adds more capabilities to two key areas: high-frequency radiosity modeling and turbomachinery duct acoustics. It also makes it noticeably easier to bring real-world measurement data into your simulations. Here's a look at the highlights. Radiosity Gets Easier and More Powerful Setting up a radiosity model traditionally meant manually building element sets in ActranVI. In 2026.1, that step is now automated, with element set size and angle thresholds optimized for convergence, while still leaving room for manual control. The radiosity solver now also supports multiple meshes across different topologies in a single radiosity analysis, allowing independent meshes to be combined without grid or element-numbering conflicts. For teams doing large-domain, high-frequency acoustic work, this translates directly into faster model builds. Radiosity also gains two significant modeling capabilities. First, transmission effects : using transmission loss (TL) data assigned to a PANEL component, the solver can now account for acoustic energy that passes through surfaces, not just energy that reflects or is absorbed. That's a meaningful addition for automotive, aerospace, and shipbuilding applications, where sound transmission through panels and structures often drives the acoustic outcome. Second, radiosity sources can now be defined directly from structural vibration or acoustic intensity data , pulled from measurements or simulation, with user-supplied radiation-efficiency data feeding into accurate power injection. Together, these updates mean radiosity models can better reflect what's actually happening in physical systems. Duct Acoustics: Now with Shear and Swirl For aeroacoustics and turbomachinery teams, 2026.1 introduces modal extraction and injection with non-uniform mean flows, such as axial shear and swirl, across Actran TM, Actran DGM, and iTM modal matching. Both 2D axisymmetric and 3D annular/circular duct geometries are supported, with user-defined, CFD-fitted, or fully interpolated flow profiles. The payoff is more accurate mode refraction, smoother SPL predictions, and better robustness in the complex rotating-flow environments typical of aircraft engines, turbochargers, and industrial fans. Measurement Data Gets Streamlined A new experimental data conversion tool in ActranVI turns raw .csv measurement data, vibration or acoustic, into Actran-ready .nff and .plt files with no manual scripting required. This pairs well with the new accelerometer-based source type in the pass-by noise workflow manager, which maps accelerometer measurements onto automatically generated transfer functions across RPM-, speed-, and time-dependent formats. Small Changes Mean Real Time Savings A small change can translate into real time savings for acoustic simulation. The unified search bar on the ribbon now offers instant suggestions and bookmarkable favorites that reduce the learning curve for new users, and can help power users get more productivity out of Actran. The Actran 2026.1 release is all about closing the gap between acoustic simulation and the real world with easier setup, real-world physics, and tighter data integration, all while shaving time off routine or less-frequently performed tasks. To see all the updates in the Actran 2026.1 release, be sure to check out SimCompanion !https://community.cadence.com/cadence_blogs_8/b/pcb/posts/high-speed-heterogeneous-integration-with-multiphysics-analysis-for-sow-xWed, 08 Jul 2026 04:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364197MSATeam/cadence_blogs_8/b/pcb/posts/high-speed-heterogeneous-integration-with-multiphysics-analysis-for-sow-x02.5D advanced packaging is becoming increasingly critical as the demand for AI and high-performance computing (HPC) applications continues to rise and monolithic die size hits reticle limit. To sustain continuous growth in computing performance, advanced packaging technologies are constantly evolving. TSMC's System-on-Wafer (TSMC-SoW™) technology and its highly advanced design necessitate a reliable and efficient high-performance electromagnetic (EM) analysis tool. Design Optimization for SerDes Beyond 200G Interconnects and PDNs with Clarity 3D Solver CadenceLIVE 2026 included a presentation by Cadence customer Global Unichip Corp. (GUC) discussing how GUC uses Clarity 3D Solver and Sigrity X PowerSI analysis technologies to perform signal integrity/power integrity (SI/PI) simulations for high-speed key IP on SoW-X, including serializer/deserializer (SerDes) 212G, GUC's Universal Chiplet Interconnect Express (GUCIe) D2D 64G, and more. An example is provided showing how the Clarity solver is used to analyze the signal integrity of the SerDes 212G signals on SoW-X. Through the visualized EM field provided by the tool, the near-end crosstalk (NEXT) at the micro bump (μBump) and ball-grid array (BGA) interfaces is strengthened from approximately −46dB (failed spec. −65dB) to about −74dB (pass spec.), while the far-end crosstalk (FEXT) is improved from approximately −27dB (failed spec. −40dB) to about −60dB (pass spec.). S-Parameters Correlation Between Third-Party EDA vs. Clarity 3D Solver The figure below compares the S-parameters extracted by the Clarity 3D Solver with those from a third-party 3D full-wave solver, showing very similar trends between the two approaches. The discrepancy in the worst-case SDD21/SDD11 at 53GHz is within approximately 0.6dB, while the difference in NEXT/FEXT at 53GHz is within 0.2dB. Notably, compared to the third-party 3D full-wave solver, Clarity extraction not only provides results similar to those but also achieves about a 15% reduction in runtime when handling scenarios with dozens of SerDes physical layers (PHYs). SerDes212G PDN Loop Inductance Analysis and Optimization For the SerDes 212G power delivery network (PDN), GUC designers solved their PDN concerns using Sigrity X PowerSI technology to optimize the loop inductance of the worst-case domain from 337pH, which exceeds the specification limit of 300pH, down to 287pH, bringing it within specification. After optimizing the PDN from the front-side redistribution layer (RDL) to the backside, all five power domains met the constraint of the loop inductance of <300pH, as shown in the figure below. Conclusion TSMC's SoW-X is a novel advanced packaging and heterogeneous integration technology that satisfies the demands of HPC and AI applications through the benefits of elevated computing performance, power savings, and area optimization, and more, as well as the tight integration of μBump to BGA, local silicon interconnect (LSI), RDL, PDNs, and voltage regulator modules (VRMs). The optimization strategies (e.g., main route, BGA area, planes, and vias) discussed in this presentation provide insights and guidance for SoW-X design integration. GUC uses Cadence multiphysics solutions, i.e., 224G-SerDes, UCIe-64GT/s, HBM4, and SoC logic core power rails to successfully meet SI/PI constraints of SerDes above 200G designs. The signal/power integrity analysis in this presentation has been well verified by Cadence's Clarity3D Solver and Sigrity X PowerSI. To see the full presentation, visit the CadenceLIVE 2026 Silicon Valley on-demand webpage . To learn more about Cadence's tools featured in the GUC presentation, visit the Clarity 3D Solver product webpage and the Sigrity X product webpage .https://community.cadence.com/cadence_blogs_8/b/fv/posts/from-pacemakers-to-adas-verifying-systems-before-tapeoutTue, 07 Jul 2026 14:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364236Reela Samuel/cadence_blogs_8/b/fv/posts/from-pacemakers-to-adas-verifying-systems-before-tapeout0Imagine discovering a critical bug in a heart pacemaker, not after deployment, not during final qualification testing, but months before the chip itself exists. At first glance, that sounds impossible. After all, how can engineers validate a system that has not yet been manufactured? Yet this question sits at the center of modern semiconductor development, where the challenge is no longer simply building silicon. Increasingly, the real challenge is proving that the software, algorithms, interfaces, and system behavior will function correctly long before the first wafer reaches the fab. As systems become more software-defined, the traditional development model is being pushed to its limits. Medical devices, automotive safety systems, and intelligent robotics platforms all depend on increasingly sophisticated SoCs that integrate hardware, firmware, operating systems, communication stacks, sensors, and application software. Waiting for first silicon before beginning meaningful validation is no longer practical. Development cycles are too short, software stacks are too large, and the cost of finding problems late in the process is simply too high. This shift is driving a new approach to verification: one that enables software bring-up, system validation, and large-scale testing months before physical hardware is available. Platforms such as Cadence Palladium Emulation System and Protium Enterprise Prototyping System are helping engineering organizations make that transition by allowing teams to validate complex systems earlier, iterate faster, and reduce risk throughout development. Different Industries. The Same Verification Challenge. A pacemaker. An ADAS controller. A humanoid robot. At first glance, they seem to have little in common. One monitors heart rhythms. Another helps prevent vehicle accidents. The third navigates the physical world through sensors, perception, and motion control. Yet beneath the surface, they share the same engineering reality. All three depend on increasingly sophisticated SoCs that combine hardware, firmware, operating systems, communication interfaces, sensor processing, and application software. And all three must answer the same question: How do you validate system behavior before the hardware exists? Traditional simulation remains essential, but as designs grow larger and software stacks become more complex, simulation alone often becomes the bottleneck. Teams need environments that can execute real workloads, run longer test scenarios, and support software development months before first silicon arrives. That is where hardware-assisted verification changes the equation. When a Pacemaker Needs Years of Confidence Consider a modern implantable cardiac device. The algorithms inside these systems continuously analyze physiological signals and make decisions that directly impact patient safety. Testing them is not simply a matter of running a handful of unit tests. Engineers must evaluate thousands of signal variations, operating conditions, and edge cases to build confidence that the system will behave correctly over years of operation. For many organizations, the challenge is compounded by the fact that relatively small hardware teams must support large, globally distributed software organizations working on multiple product variants simultaneously. In these environments, the bottleneck is often not engineering expertise but access to realistic hardware platforms. Cloud-based prototyping environments help remove that constraint by allowing software teams to begin algorithm validation, firmware development, and long-duration testing long before silicon becomes available. Instead of compressing validation into the final stages of development, teams can start earlier, test longer, and uncover issues when they are far less expensive to fix. ADAS: Where "Almost Correct" Is Not Good Enough The automotive industry faces a different but equally demanding challenge. Advanced Driver Assistance Systems (ADAS) must interact reliably with sensors, communication networks, safety mechanisms, and vehicle control systems while operating under strict functional safety requirements. Here, verification is not simply about proving that software runs correctly. It is about proving that the entire system behaves correctly under realistic operating conditions. A software model may suggest everything is working as intended, but real-world behavior is often influenced by interface timing, protocol interactions, and system-level effects that only emerge when hardware and software execute together. This is why many automotive teams use emulation platforms to perform large-scale hardware verification and regression testing before transitioning to hardware-accurate prototyping environments for software validation. The goal is not merely faster execution. It is confidence that the complete system will behave as expected when exposed to real interfaces, real workloads, and real operating conditions. Accelerating the Learning Loop in Robotics Robotics introduces yet another layer of complexity. Every movement a robot makes depends on a constant stream of data flowing through sensors, vision systems, accelerometers, motion controllers, and software algorithms. What appears effortless from the outside is the result of thousands of iterative development cycles. A robot attempts a movement, fails, the software is adjusted, and the process repeats. Innovation depends on how quickly teams can complete that loop. Traditional simulation often becomes a bottleneck because realistic robotics workloads require long-running execution and continuous interaction between hardware and software. Hardware-assisted verification environments allow engineers to run larger workloads, validate software against realistic hardware behavior, and iterate faster without waiting for physical silicon. The result is not simply accelerated verification, it is accelerated learning, which often becomes the difference between a promising concept and a viable product. The Bigger Shift: Verification Is Becoming a Continuous Workflow Across all three industries, the most important transformation is not technological. It is organizational. Historically, software teams waited for hardware. Today, software development often begins months before silicon arrives. Historically, validation happened late in the project schedule. Today, it starts much earlier and continues throughout development. Historically, verification resources were tied to physical labs and limited infrastructure. Today, cloud-enabled environments allow globally distributed teams to access sophisticated verification platforms from virtually anywhere. This shift is changing how engineering organizations operate. Small hardware teams can support much larger software organizations. Verification scales more effectively with growing design complexity. Development no longer stalls while teams wait for physical hardware to arrive. Most importantly, organizations gain confidence earlier in the lifecycle, when design changes are easier to make and risks are easier to manage. Why This Matters More Than Ever As semiconductor systems continue to grow in complexity, this capability is becoming increasingly important. Medical devices are becoming smarter. Vehicles are becoming more autonomous. Robots are becoming more capable. Every advancement introduces more software, more interfaces, more sensors, and more opportunities for failure. The traditional approach of waiting for silicon before validating complete system behavior simply cannot keep pace. The organizations pulling ahead are not necessarily those building the most advanced chips. They are the ones finding ways to validate reality earlier. They are reducing iteration cycles, enabling hardware and software teams to work in parallel, and creating development environments that closely mirror real-world operation long before tapeout. That is why hardware-assisted verification platforms such as Palladium and Protium matter. They are not simply tools for running tests faster. They are helping redefine when validation happens, how teams collaborate, and how confidence is built throughout the development process. Final Takeaway The most compelling lesson from mission-critical semiconductor development is surprisingly simple: the earlier you can validate reality, the fewer surprises you encounter later. Whether the product is a pacemaker, an ADAS controller, or a humanoid robot, the objective remains the same: find issues earlier, validate longer, and move faster without sacrificing confidence. For engineering leaders navigating increasingly complex SoC development, that may be one of the most important competitive advantages emerging in modern verification. Want to hear the full discussion? Click here to listen to the complete discussion by Lance Tamura, product management director and see how leading teams are accelerating software and system validation before first silicon.