https://community.cadence.com/search?q=type%3Ablog%20-%22Chinese%20blog%22%20-%22Japanese%20blog%22%20-%22Taiwanese%20blog%22en-USTelligent Community 12en-usnoSearch results for 'type:blog -"Chinese blog" -"Japanese blog" -"Taiwanese blog"'https://community.cadence.com/cadence_blogs_8/b/di/posts/boost-design-productivity-by-cadence-digital-tools-webinar-recording-availableThu, 02 Jul 2026 03:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364233sakshin/cadence_blogs_8/b/di/posts/boost-design-productivity-by-cadence-digital-tools-webinar-recording-available0Did you miss the next‑gen Cadence digital implementation tools webinar series? No worries, the recording is now available! If you missed joining or registering for the Next‑Gen Cadence Digital Implementation Tools Webinar Series , the complete recording is now available as a Training Byte at the Cadence ASK portal. This webinar series helps designers explore Cadence’s latest digital design and signoff tools, discover powerful debugging workflows, smart scripting techniques, rapid editing capabilities, and advanced analysis features to help you work faster and elevate your design’s PPA. Why This Webinar Series Matters In today’s advanced nodes, late‑stage surprises in timing, QoR, or testability can result in costly redesigns and schedule slips. The key to avoiding these risks lies in shifting insight earlier in the design cycle and maintaining strong correlation as the design matures. This webinar series demonstrates how next‑generation Cadence digital implementation tools and methodologies help engineers: Shorten feedback loops at RTL Improve timing prediction from RTL through signoff Automate complex DFT tasks within synthesis Achieve faster convergence with better PPA outcomes Each session delivers practical, designer‑focused guidance grounded in real design scenarios. Webinar Summary Date Product Page CadenceTECHTALK: Inserting Gate-Level DFT in Genus after DFT Instrumentation at RTL This webinar presents the key Genus Synthesis Solution features for DFT insertion using a design in which most DFT logic has already been added at RTL. 21 April 2026 Genus CadenceTECHTALK: Faster Turnaround, Better QoR - Timing Correlation Recipes Across RTL to GDS This webinar present the key factors that influence timing predication and timing correlation and introduce proven methodologies and tools that can be applied from the early design phases through to Cadence Innovus Implementation System’s postRoute tool to Cadence Tempus Timing Solution’s signoff closure. 14 April 2026 Innovus CadenceTECHTALK: Design Faster, Debug Smarter - Transform RTL Productivity with Cadence RTL Design Studio This webinar presents existing capabilities of RTL Design Studio, showcasing how its unified cockpit, rapid prototyping, and rich analysis features help designers quickly identify issues, understand root causes, and refine RTL with greater confidence. 07 April 2026 Joules RTL Design Studio CadenceTECHTALK: Conformal Equivalence Checker Advanced Debug This webinar presents a step-by-step method to address issues, in particular non-equivalences and aborts, with a focus on the most recent and advanced features. 31 March 2026 Conformal Equivalency Checker CadenceTECHTALK: Stylus Compare - A Comprehensive Utility for Comparison of Common UI Databases Using Innovus and Other Back-End Tools This webinar presents the main features of Stylus Compare, a utility to run a detailed database comparison in Common UI. 24 March 2026 Innovus Webinar Recordings CadenceTECHTALK: Inserting Gate-Level DFT in Genus after DFT Instrumentation at RTL CadenceTECHTALK: Faster Turnaround, Better QoR - Timing Correlation Recipes Across RTL to GDS CadenceTECHTALK: Design Faster, Debug Smarter - Transform RTL Productivity with Cadence RTL Design Studio CadenceTECHTALK: Conformal Equivalence Checker Advanced Debug CadenceTECHTALK: Stylus Compare - A Comprehensive Utility for Comparison of Common UI Databases Using Innovus and Other Back-End Tools Conclusion The Accelerate Design Productivity: Next‑Gen Cadence Digital Implementation Tools webinar series delivers practical methodologies and tool insights to help design teams keep pace with growing complexity. By bringing smarter analysis, stronger correlation, and automation earlier into the flow, engineers can reduce risk, improve QoR, and meet aggressive tape‑out schedules with confidence.https://community.cadence.com/cadence_blogs_8/b/fv/posts/nvme-2-0-explained-what-s-new-and-why-it-mattersWed, 01 Jul 2026 11:18:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364202Vishal Patel/cadence_blogs_8/b/fv/posts/nvme-2-0-explained-what-s-new-and-why-it-matters0Non-Volatile Memory Express (NVMe) has become the dominant protocol for high-performance storage across client SSDs, enterprise drives, and hyperscale data centers. With NVMe 2.0, the specification expands beyond traditional block-based SSD access with new command sets, broader media support, improved transport organization, and enhancements for modern deployments. This post explores what is new in NVMe 2.0, why these additions matter, and how they impact storage architects, implementers, and verification teams. Why Was NVMe 2.0 Needed? NVMe 1.4, while powerful, centered on a largely monolithic base specification - a single large document covering the PCIe transport, queuing model, admin and I/O commands, and command-set behavior together. As the ecosystem expanded beyond SSDs into new domains (computational storage, key-value stores, zoned namespaces), the single-spec model became unsustainable: Specification bloat: Adding every new feature to one document made it unwieldy for implementers who only needed a subset. New transport needs: NVMe was no longer PCIe-only. Fabric transports such as RDMA and TCP had grown important enough to require separate, dedicated NVMe transport specifications. Diverse command sets: As NVMe evolved, emerging command sets such as Zoned Namespaces (ZNS) and Key-Value (KV) storage required independent specifications and lifecycle management rather than being maintained as extensions within a single evolving specification family. Industry velocity: Cloud, edge, automotive, and AI/ML workloads demanded faster iteration on specific features without revising the entire specification. Some Key Enhancements in NVMe 2.0 1. Modular Specification Architecture NVMe 2.0 breaks the monolithic spec into a family of focused documents: Document Purpose NVMe Base Specification Core architecture, admin commands, queuing model NVMe Command Set Specifications NVM (block), ZNS, KV command sets - each independent NVMe Transport Specifications PCIe, RDMA, TCP - each independent NVMe Management Interface (NVMe-MI) Out-of-band device management Why it matters: An implementer building a ZNS SSD over TCP can focus primarily on the Base specification, ZNS command set, and TCP transport specification instead of navigating one large monolithic document. Under NVMe 1.4, a single errata or feature addition required revising the entire specification, coordinating across all stakeholders. Under 2.0: A new transport can be standardized as an independent document instead of being folded into one monolithic specification. A new command set , such as computational storage or other emerging models, can evolve through its own specification. Spec revisions are scoped - a change to ZNS doesn't require re-review of the NVM command set or TCP transport. 2. Zoned Namespaces (ZNS) - Independent Command Set ZNS evolved through the NVMe technical proposal process and became an independent command set specification in the NVMe 2.0 family. Exposes the internal zone structure of flash to the host. Reduces write amplification and over-provisioning. Gives the host direct control over data placement. Result: Higher endurance, reduced write amplification, more predictable latency, and potentially lower cost per GB for suitable workloads. 3. I/O Command Set Independence and Namespace Types NVMe 2.0 formalizes the concept of I/O command sets as independent, pluggable modules. Each namespace is now associated with a specific command set identifier (NVM, ZNS, KV). Controllers can advertise support for multiple command sets simultaneously. Enables future command sets to be added without revising the base specification. 4. Simple Copy Command Enables offloaded data copy within a namespace without host-side data movement. Reduces host CPU and memory usage during copy-heavy tasks such as garbage collection, deduplication, and snapshots. The device performs the copy operation without requiring the host to read and rewrite the payload data across PCIe. 5. Rotational Media Support NVMe 2.0 broadens the architecture so that rotational media such as HDDs can be represented within the NVMe ecosystem. Helps enable a more common NVMe-based command interface across flash and rotational media. Helps simplify software stacks by using a more consistent NVMe-based interface across different media types. 6. Vendor-Specific I/O Command Sets NVMe 2.0’s command set model provides a cleaner path for vendor-specific or future command-set extensions. Vendors can introduce proprietary capabilities while maintaining alignment with the broader NVMe architecture. Keeps the ecosystem open while allowing differentiation. 7. Persistent Memory Region (PMR) Enhancements NVMe 2.0 carries forward and refines Persistent Memory Region support. Defines clearer behavior for host access to controller-side persistent memory. PMR can be used by software designed to exploit controller-resident persistent memory for applications such as metadata acceleration, journaling, or write-ahead logging. Who Benefits from NVMe 2.0? Cloud and hyperscalers: ZNS reduces TCO through lower write amplification and over-provisioning. Database and KV Stores: Native KV command support reduces unnecessary block-layer translation. Storage vendors: Modular spec allows focused implementation and faster time-to-market. Enterprise IT: Modular specifications and command-set flexibility simplify the adoption of new NVMe capabilities while maintaining long-term scalability. Automotive and edge: Leaner implementations by adopting only the needed command set and transport. Verification Challenges NVMe 2.0 adds verification complexity because the protocol is no longer tied to one monolithic specification or one block-oriented command model. A controller may support different combinations of base functionality, command sets, namespace types, transports, multipath behavior, and optional features, so verification must cover both individual features and their interactions. Command set selection: Ensuring the controller correctly advertises and enables supported I/O command sets such as NVM, ZNS, and vendor-specific command sets. Namespace association: Verifying that each namespace is mapped to the correct command set identifier and that unsupported commands are rejected with the appropriate status. ZNS behavior: Checking zone state transitions, sequential write rules, zone append handling, reset behavior, and error cases for invalid zone operations. Feature interaction: Covering combinations such as Simple Copy, PMR behavior, and rotational media support across different controller configurations. Cadence’s NVMe Verification IP addresses these challenges with configurable host and subsystem models, protocol checkers, constrained-random traffic, error injection, coverage, and debug support. The VIP helps teams validate NVMe 2.0 features such as command set independence, namespace management, ZNS behavior, PRP/SGL handling, and transport-specific scenarios across IP, SoC, and system-level environments. In addition, the NVMe VIP testsuite provides reusable building blocks that make it easier for users to create targeted verification scenarios, configure traffic patterns, exercise feature-specific behavior, and inject error conditions as needed for their environment. As NVMe evolves toward modular, workload-specific storage architectures, comprehensive verification support is essential for compliance, interoperability, and faster time-to-market. More information on Cadence NVMe Verification IP is available at Simulation VIP for NVMe | Cadence . Reach out to Cadence Verification IP experts at talk_to_vip_expert@cadence.com with any questions.https://community.cadence.com/cadence_blogs_8/b/pcb/posts/understanding-cadence-licensing-floating-vs-single-user-sulWed, 01 Jul 2026 09:11:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364156Shikha Jain/cadence_blogs_8/b/pcb/posts/understanding-cadence-licensing-floating-vs-single-user-sul0In PCB design teams today, the way licenses are managed can have a direct impact on productivity, infrastructure complexity, and how quickly engineers can get started. Floating licenses have been the standard for years, mainly because they allow teams to efficiently share a common license pool. However, as workflows have shifted towards remote work, distributed teams, and increased mobility, this model can sometimes slow things down due to dependencies on VPNs, license servers, and network availability. To support these changing needs, Cadence introduced Single User Licensing (SUL) —a simpler, workstation‑based licensing model that focuses on reliability and independence. The biggest advantage of SUL is simple: your tools just work—anytime, anywhere. There is no need to connect to a license server or VPN, and no dependency on network availability. Whether you are traveling, working remotely, or in a low-connectivity environment, you can access your Cadence tools without interruption. This post kicks off the Cadence SUL Series , where we will walk through what SUL is, where it fits, and how it can simplify your day‑to‑day work. What Is Cadence Single User Licensing (SUL)? Cadence Single User Licensing is designed for one user on one machine, giving you dedicated and uninterrupted access to your Cadence tools. It is well-suited for engineers working on personal or remote workstations, or anyone who prefers a setup that simply works without relying on a network license server. What Sets SUL Apart Work on the Go – No Connection to a Corporate License Server Needed : One of the biggest advantages of SUL is its flexibility. Whether you are traveling, working from home, or at a customer site, your tools remain fully available. No VPN. No server check-ins. No connectivity concerns. Dedicated Access : Each user has their own license, so there is no contention or waiting when launching tools. Simple Setup : There is no need to install or configure a FlexNet license server. Activation happens during installation, making the setup quick and straightforward. Cost Predictability : Licenses are tied to individuals rather than shared pools, making it easier to plan and manage costs, especially for smaller teams. Floating License vs. Single User License: What Works Best? If you are using Cadence tools such as OrCAD X PCB Editor, OrCAD X PCB Layout, or OrCAD X Capture, the license model you choose can affect your workflow. Floating licenses work well for teams that benefit from shared access, while SUL is better suited for individuals who need consistency and independence. Here’s a quick comparison: Feature Floating License Single User License (SUL) Access Model Shared across multiple users One user Licensing Setup Requires a license server Automatically set up during installation Network Dependency Yes No License Availability May face contention Always available Ideal For Larger teams Individuals or remote users Cost Model Optimized for shared resources Predictable for individuals Conclusion Single User Licensing is not just an alternative licensing model—it is a practical option for engineers who want a more predictable and flexible way to work. By removing dependencies on license servers and network access, SUL helps keep workflows simple and consistent, especially in remote or mobile environments. Currently, SUL is available for selected OrCAD X products, including OrCAD X Capture, OrCAD X PCB Editor, OrCAD X PCB Layout, and PSpice A/D. In the next post in this series, we will walk through the installation and activation steps so you can get up and running quickly. Contact Us For any feedback or topics you would like us to include in our blogs, write to us at pcbbloggers@cadence.com . Subscribe to stay updated about upcoming blogs. About BoardSurfers The BoardSurfers series provides solutions for various tasks related to PCB design creation and management using Allegro platform products. The name and logo of this series are designed to resonate with the vision of making the design and manufacturing tasks enjoyable, just like surfing the waves. Regular, new blog posts by experts cover every aspect of the PCB design process, such as library management, schematic design, constraint management, stack up design, placement, routing, artwork, verification, and much more.https://community.cadence.com/cadence_blogs_8/b/di/posts/mastering-advanced-debug-in-conformal-lec-mapping-to-ai-driven-abort-resolutionWed, 01 Jul 2026 04:53:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364232sakshin/cadence_blogs_8/b/di/posts/mastering-advanced-debug-in-conformal-lec-mapping-to-ai-driven-abort-resolution0From manual debugging to AI-assisted resolution-LEC (logical equivalence checking) debug is evolving. Join us to explore how traditional Conformal Equivalence Checker (LEC) and next-generation Conformal AI Equivalence technologies can transform the way you handle non-equivalences (NEQs) and aborts. CadenceTECHTALK: Conformal Equivalence Checker Advanced Debug What This Training Covers The presentation is structured around a clear, methodical debug flow that mirrors real‑world LEC challenges encountered during RTL‑to‑netlist and hierarchical comparisons. A. Mapping: The Foundation of Successful LEC The training emphasizes mapping as the first checkpoint before diving into deeper debug. Participants are introduced to: Mapping resolution charts Common causes of unmapped points Best practices for resolving naming, modeling, and data consistency issues Correct mapping ensures that corresponding key points between golden and revised designs are paired accurately, forming the basis for meaningful equivalence analysis. While automated out-of-box mapping has improved dramatically in the new Conformal AI Studio product line, this continues to be a critical step in the flow to avoid false NEQs and aborts. B. Debugging Non‑Equivalences with Structured Resolution Charts Once mapping is validated, the focus shifts to non‑equivalent compare points. The training categorizes non‑equivalences into: False non‑equivalences caused by setup, constraint, modeling, or mapping issues True non‑equivalences resulting from real functional differences Attendees learn how to use non‑equivalence resolution charts to triage failures, investigate schematics, validate constraints, and identify when issues originate from synthesis optimizations or RTL behavior. C. Abort Analysis and Resolution Aborts are highlighted as a distinct class of LEC challenges—compare points that cannot be proven equivalent or non equivalent within allocated runtime. The session explains: Typical causes of aborts, such as large combinational cones, resource sharing, and X‑assignments Why aborts should be debugged only after resolving non‑equivalences How abort resolution charts guide engineers toward effective next steps This structured approach helps reduce guesswork and accelerates convergence. Conformal approaches to analyzing and solving aborts have been evolving over the last decade. Multiple technologies are available in traditional LEC, while some of the newest automated approaches require Conformal AI Equivalence. D. Leveraging Conformal LEC and Smart LEC To address runtime and scalability challenges, the training introduces advanced features including: Conformal LEC techniques for improving performance Conformal Smart LEC capabilities such as multithreading, smart instance selection, and distributed parallel analysis These features are positioned as key enablers for faster turnaround time, especially on large, hierarchical designs. E. AI‑Driven Automated Abort Resolution with CAR The session culminates with a look at Conformal AI Equivalence and the CAR (Conformal Abort Resolution) flow. By leveraging historical run data, machine learning models, and automated recipe exploration, CAR significantly reduces the time required to resolve stubborn aborts. CAR uses the Cerebrus reinforcement learning architecture to explore and manage multiple Conformal scenarios in parallel to find the optimal resolving recipes for any aborting modules. This represents a shift from manual trial‑and‑error toward data‑driven, intelligent debug, especially valuable for complex designs with recurring abort patterns. Conclusion The Conformal Equivalence Checker Advanced Debug training equips engineers with a clear, repeatable methodology for tackling some of the toughest LEC challenges. By combining proven resolution charts, performance‑enhancing features like Smart LEC, and next‑generation AI‑driven flows such as CAR, the session demonstrates how advanced debug can move from reactive troubleshooting to proactive optimization. For engineers who already understand the fundamentals of LEC and want to debug smarter, converge faster, and scale with confidence, this training provides both the mindset and the tools to do exactly that.https://community.cadence.com/cadence_blogs_8/b/fv/posts/understanding-usb4-retimers-and-their-role-in-gen2-and-gen3---link-trainingWed, 01 Jul 2026 04:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364188SS202605248717/cadence_blogs_8/b/fv/posts/understanding-usb4-retimers-and-their-role-in-gen2-and-gen3---link-training0USB4 systems rely on retimers to enable reliable high-speed communication across complex topologies where maintaining signal integrity over extended channels is a significant challenge. Retimers act as intermediate elements that restore signal quality at each hop by performing clock and data recovery (CDR) and retransmitting a clean, regenerated signal. The USB4 link bring-up process follows a structured sequence from initial connectivity to high-speed operation. The process begins with lane initialization, where routers establish connectivity with the link partner through sideband communication. During this phase, the required parameters for link operation are exchanged and configured. Once initialization is complete, the router drives the transition into link training, where the link progresses toward stable high-speed communication. The retimer operates based on its channel state machine, which follows router lane initialization and link training and performs corresponding state transitions based on link conditions on both sides. Router: Lane Initialization USB4 lane initialization is divided into five phases, where routers control link configuration and parameters synchronization across the topology. Figure 1: Five-stage lane initialization Phase 1 and Phase 2 – Electrical Initialization: Sideband signaling is used to establish USB4 mode, lane orientation, polarity, and electrical readiness. Retimers forward these signals to maintain continuity across the link. Phase 3 – Capability Exchange (Router Controlled): Routers exchange capability information such as supported link speeds, lane bonding configuration, and adapter capabilities. During this phase, the retimer does not actively participate in protocol decision-making and remains transparent, forwarding sideband transactions without modification. Phase 4 – Parameter Distribution (Broadcast RT): Routers distribute final link parameters using Broadcast RT transactions, including link speed and lane configuration. Retimers update their internal configuration based on these broadcasts and propagate them across their upstream and downstream ports to ensure consistency across the topology. When a Retimer detects an LT_Resume Transaction on any USB4 Port, it shall transition to phase 5. Phase 5 – Equalization (TxFFE Negotiation): Equalization is performed using addressed RT transactions between directly connected link partners. TxFFE parameters are negotiated independently for each segment, allowing per-hop optimization before high-speed training. Retimers detect the receiver SLOS symbol and begin transmitting CL_WAKE1.X using a local clock once Rx Active is detected. After completing training across all segments and meeting the required clock switch conditions, the retimer transitions from the local clock to the recovered clock. It then stops generating training symbols and begins forwarding the received bit stream, moving the link into steady-state data operation. Retimers: Channel State Machine The retimers follow a channel state machine that aligns with the router-driven link initialization and training flow, tracking receiver activity and adapting as the link progresses. They align with the incoming signal and transition toward stable data transfer as training completes. As shown in the figure below, this sequence ensures proper synchronization before steady-state data forwarding. Figure 2: Retimer channel state machine CLd (Channel Detect): State where retimers wait for receiver activity and detect the presence of a valid signal on the channel. Bit Lock: Retimers enter this state once activity is detected on the receiver side. In this state, the receiver achieves clock/data recovery (CDR) and ensures reliable sampling of the incoming data, enabling proper Rx equalization and further link training progression. Bit Forwarding: In this state, retimers use the recovered clock and forward the received bit stream directly from receiver to transmitter without modifying the data. Training Sequence Flow: Retimers The table illustrates the packet flow during link initialization and transition into link training between two routers with two retimers present in the path. Step Router A Retimer 1 Retimer 2 Router B 1 Broadcast RT-> Update-> Update-> 2 Forward-> Forward-> Detect 4 Detect CL_WAKE1.1-> CL_WAKE1.2-> 6 8 SLOS1 -> SLOS1 -> SLOS1 10 <-SLOS1 <-SLOS1 <-SLOS1 <-SLOS1 11 Link Training (forwarding state) Link Training (forwarding state) Link Training (forwarding state) Link Training (forwarding state) Table 1: Packet flow in retimers Steps 1 – 2 (RT Broadcast and Update propagation): Router A initiates link bring-up by broadcasting RT packets. Retimers receive these packets and update the information before propagating it toward Router B. The same update flow is mirrored back from Router B toward Router A. Steps 3 – 4 (LT_Resume handshake and detection): Router A sends LT_Resume to trigger link initialization. Retimers transparently forward this signal, enabling Router B to detect link activity. The acknowledgment follows the reverse path through retimers. Steps 5 – 8 (CL_WAKE exchange through retimers): CL_WAKE ordered sets are generated by the retimer with each retimer, sending CL_WAKE1 corresponding to its retimer index. This stage ensures link partners are synchronized before progressing further. Steps 9 – 10 (SLOS1 exchange): SLOS1 ordered sets are transmitted and propagated across both retimers without modification. At this stage, retimers primarily act in forwarding mode, maintaining the integrity of training sequences. Step 11 (Transition to Link Training): Once ordered set exchanges are complete, all components (routers and retimers) transition into link training. Retimers operate in forwarding mode, directly passing received bits to the transmitter without alteration. Verification Challenges for the Retimers Verification of USB4 retimer topologies presents challenges in ensuring the correct propagation of training sequences across multiple segments. Each retimer must receive, regenerate, and forward sequences while maintaining signal integrity and timing alignment. Retimer identification and topology discovery ensure correct mapping of logical indices across the chain. Any mismatch can lead to incorrect targeting of training transactions. Lack of proper verification of retimer behavior can lead to link instability or failure in multi-retimer topologies. If such issues are identified post-silicon, time-to-market is impacted due to the additional effort required for debug and re-verification. Cadence has a mature verification IP solution for the verification of various topologies of retimers in a USB4 design, with verification capabilities provided to do a comprehensive verification of these topologies. Learn more about Simulation VIP or reach out to our Cadence Verification IP experts for further information.https://community.cadence.com/cadence_blogs_8/b/artificial-intelligence/posts/the-feedback-loop-is-the-moat-480749506Tue, 30 Jun 2026 20:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364224HS202601273724/cadence_blogs_8/b/artificial-intelligence/posts/the-feedback-loop-is-the-moat-4807495060Every verification and design team I talk to is building agents right now. The demos are genuinely impressive: point an LLM at some RTL, ask it to write assertions or close coverage or root-cause a failure, and it produces something that looks right. Then the same teams hit the same wall: Can I trust it? Will it give me the same quality answer tomorrow, on a different block, under a slightly different condition? In production, what matters is reliability, consistency, and the quality of the result, and that is exactly where generic LLM-based agents fall apart. The instinct is to reach for a better prompt or a bigger model. I want to argue that this instinct is wrong. The reliability ceiling of a chip design agent is not set by the model. It is set by the quality of the feedback the agent can get from the EDA tools underneath it. Deep integration with those tools is what separates a demo from a deployable agent, and it is the real, durable moat in this space. LLMs Are Feedback Engines, Not Oracles Start with what an LLM actually is in this context. It is not a database of truths about your design. It does not know your FIFO depths, your reset sequence, your reachable states, or which of your tests actually exercises which piece of logic. It is a reasoning engine that operates on the context you give it and the feedback it gets back. Hand it nothing but RTL and a question, and it will produce a confident, plausible, and frequently wrong answer, not because it cannot reason, but because it has nothing to check that reasoning against. It is working from inference, not measurement. This is why I tell people that building a reliable agent is not a prompting problem; it is a feedback problem. The entire craft is closing the loop: the agent proposes something, a tool gives it real feedback, the agent reasons over that feedback and refines, and you repeat until you converge. The more feedback you give, and the richer it is, the better, the more consistent, and the higher-quality the result. This is the single most important principle in the whole field, and almost everything else follows from it. But not all feedback is equal, and the distinction is what this whole argument turns on. The first kind is verdict feedback : Did it pass or fail? Did the test compile, did the assertion prove, what is the coverage number? This is necessary, but it is low-bandwidth. A pass/fail bit or a single percentage tells the agent almost nothing about why , and an agent that only sees verdicts is reduced to guess-and-check. It will eventually stumble onto answers, burning compute and wall-clock time, and it will do so inconsistently. The second kind is diagnostic and structural feedback : not just whether something failed, but why it failed and what the structure of the problem actually is. Which testbench knob corresponds to which coverage hole? Which logic sits in the cone of influence of the signal you care about? What the FSM looks like and which of its states are reachable. This feedback is high-bandwidth, and it is precisely what deep EDA integration unlocks, and what a shallow LLM-plus-RTL wrapper can never produce. Figure 1: Reliability is a feedback problem: the agent proposes, the EDA engine returns ground-truth feedback, and the loop repeats until the result converges. Example 1: The Coverage Closure Agent Take a coverage closure agent. After a regression, you are left with a set of uncovered items, cover points, bins, and the crosses that are always the hardest to hit. The agent's job is to generate the stimulus, the configuration, or the constraints that close them. The shallow approach is to feed the LLM the RTL, the list of uncovered items, and maybe the testbench, and ask it to reason about why each item is uncovered and what would hit it. And the LLM genuinely can reason structurally here: it can look at a cover point and infer that hitting it requires some signal high while the design is in a particular state, which in turn requires a particular sequence of transactions. For shallow logic and simple cover points, this works. But the moment you are dealing with deep pipelines, rich cross coverage, or holes gated by rare microarchitectural conditions, the LLM is flying blind. It has no idea what your existing tests actually do, which items are genuinely reachable versus structurally dead, or how your stimulus knobs map onto coverage. So it produces plausible stimulus that frequently does not move the needle, and you find that out the expensive way, by spending regression cycles to confirm the guess was wrong. That is the reliability ceiling, and no amount of prompt engineering raises it, because the missing ingredient is not reasoning. It is data about your design that simply is not in the RTL. Now wire that same agent into something like Cadence Verisium SimAI . SimAI learns, from your actual regression history, the correlation between testbench components and stimulus configuration on one side and coverage outcomes on the other. Instead of the agent guessing which knob might matter, it can ask a model that has measured it: which tests and which configurations correlate with this cover item, which uncovered items are likely reachable and which are probably dead, and what ranked stimulus is predicted to hit a given target. And because it answers from a learned model rather than a fresh regression, the agent gets that feedback in seconds rather than waiting days to find out. Suddenly, the LLM is not guessing; it is reasoning over ground-truth correlation data and proposing changes grounded in what has actually been observed to drive coverage in your environment. The loop closes. Convergence improves, the agent stops chasing dead items, and, critically, it does so consistently, run after run, block after block. Figure 2: In coverage closure, the LLM reasons and SimAI supplies measured stimulus-to-coverage correlation learned from regression history. Neither half closes the loop alone. Notice the division of labor, because it is the whole point. The LLM is the reasoner: it decides what to try, how to compose knobs, and how to phrase a constraint. SimAI is the feedback oracle: it supplies the measured correlation that tells the reasoner whether an idea has any chance of working. Neither is sufficient alone. And SimAI's correlation model is not something you can prompt your way to or scrape off the RTL, it is built on the simulation engine, the coverage database, and the regression data underneath it. You only get it through deep integration. That is not an incidental detail. That is the moat, showing up in the very first example. Example 2: The Formal Verification Agent Formal makes the same point even more sharply, because formal is unforgiving in a way simulation is not. The defining problem in formal is convergence. You write a property, the engine runs, and instead of a clean proof or counterexample, you get a bounded result or an inconclusive one if the state space is too large for the engine to reach a verdict. The agent's job is to make properties converge, and the levers are well known: assumptions and constraints to prune illegal state space, abstractions to shrink complexity, and helper assertions or lemmas to decompose the problem so the engine can finish. The shallow approach, RTL plus property, asks the LLM for assumptions and helpers, which is not just unreliable here; it is dangerous. Without understanding the design's structure, the LLM proposes generic constraints. It may over-constrain and quietly prune away legal behavior, which produces a "proven" result that is actually vacuous, a false green that is worse than no answer at all, because you will ship on it. It may propose helper assertions that do not lie anywhere along the logical path to the target and so do nothing to help the engine converge. The model does not know your state encodings, your FIFO depths, the cone of influence of the target, or the protocols at your interfaces, and in formal, that ignorance does not produce a wrong number you can double-check. It produces an unsound proof you will trust. Now give the agent access to Cadence Jasper Formal Verification Platform 's design intelligence. Before it proposes anything, it can extract real structure from the design: the FSMs and their reachable states, the FIFOs and memories, and the control logic around them, the cone of influence (COI) of the target signals, the interface protocols, and the structural complexity that is actually driving the blow-up. With that in hand, every lever changes character. For assumption generation , the agent stops guessing constraints and starts deriving them from the reachable FSM states and the protocol rules at the interfaces, constraints that prune genuinely illegal space without touching legal behavior. And because it knows the cone of influence of the target, it can check that an assumption is not constraining away the very logic under proof, which is exactly the mistake that creates vacuous results. For abstraction , structure tells the agent what to abstract and what to leave alone. The cone of influence identifies the logic that is irrelevant to the property and can be cut away; FIFO and counter detection identify exactly where data abstraction, counter abstraction, or memory abstraction is both safe and high-leverage. Instead of mindlessly abstracting and destroying precision, the agent targets the specific structures that are exploding the state space. For helper assertions , knowing the FSM and the cone of influence lets the agent propose intermediate lemmas that actually sit on the proof's logical path, prove that an internal FSM reaches a given state, and the engine can lean on that to converge on the top-level property. These are decomposition steps grounded in the design's structure, not lucky guesses. Figure 3, Jasper's structural intelligence (FSMs, FIFOs, COI, protocols) grounds all three formal levers, turning guesses into structure-driven, sound transformations that converge. The pattern is identical to the coverage case. The LLM supplies the reasoning and the creativity, which abstraction, which lemma, how to phrase an assumption. Jasper supplies the structural ground truth that makes that reasoning both correct and sound. Strip Jasper out, and the agent is reasoning in the dark, and in formal, reasoning in the dark does not just slow you down, it produces results you cannot trust. Wire it in, and the proofs converge reliably and, just as importantly, soundly. The Principle Underneath Both Step back, and the two examples collapse into one principle. In both, the LLM is the reasoning engine, and the EDA tool is the source of high-bandwidth, ground-truth feedback, correlation data in one case, structural intelligence in the other. And in both, the agent's reliability, its consistency, and the quality of its output are a direct function of the richness of the feedback the tool exposes. An agent that sees only RTL and logs is stuck at verdict-level feedback and will always have a reliability ceiling. There is no prompt that conjures a signal the tool never produced. Feedback Also Has to Be Fast There is a second axis to feedback that matters just as much as richness, and teams consistently underestimate it: latency. EDA feedback is often slow. A full regression can run for hours or days. A formal proof can churn for a long time and still come back inconclusive. If every turn of the agent's loop costs a multi-day regression, it is not really a loop; the agent gets to try a handful of things, not the hundreds it would need to converge on a genuinely hard problem. So for the agent, speed can matter as much as accuracy, and, importantly, the agent usually does not need an exact answer to make progress. A fast, approximate signal that points in the right direction is enough for it to iterate: to rank ideas, prune the obviously bad ones, and concentrate effort where it is likely to pay off. We do not need full accuracy at every step. We need a usable signal, quickly. A good approximation in seconds beats an exact result in days. This is why I think one of the highest-leverage things we can build is fast prediction models for the expensive functions in the flow, surrogates that approximate what a slow engine would tell you, in a fraction of the time. The clearest example is coverage: a model that predicts the coverage impact of a proposed change in seconds, instead of launching a regression to find out. Give the agent that, and it can explore stimulus and configuration changes rapidly, guided at every step by a fast estimate of what will actually move coverage. The idea generalizes: a model that predicts whether a property is likely to converge, or which abstraction is likely to help, lets a formal agent try directions before paying for the engine. These surrogates do not replace the golden engines; they feed the agent. The pattern is an inner loop and an outer loop: the agent iterates many times, cheaply, against the fast predictor, and falls back to the exact, slow engine only to confirm the few candidates that survive. SimAI is already an instance of this; it answers "will this help coverage?" from a learned model, fast, without re-running the regression. The opportunity is to build that kind of fast, predictive feedback for more of the flow. Figure 4, Two loops: the agent iterates rapidly against a fast, approximate prediction model and confirms only the survivors against the slow, exact engine. Fast, approximate feedback is what makes the loop practical. Why This Is the Moat This is why I keep coming back to integration as the moat, and I mean that in a hard, structural sense, not as a slogan. Anyone can wrap a frontier model. The weights are a few API calls away, and they get better for everyone at the same time. If your agent is "LLM plus RTL," you have no durable advantage, you ride the model curve, the team across the street rides it too, and on the day a better model ships, you both get better together. There is nothing to defend. What is not commoditizing is the other side of the loop. SimAI's coverage correlation is built on a simulation engine, a coverage database, and years of regression data. Jasper's structural intelligence is built on world-class formal engines and decades of analysis technology. And the fast prediction models that keep the agent's loop quick, a coverage predictor, a convergence predictor, are built on those same engines and the same accumulated data. None of this is scrapable, promptable, or reproducible by a model, however large. It is the ground truth of the design, and it lives inside the EDA tools. So the moat is not the agent and it is not the model. It is the depth of integration into the EDA stack and the richness and speed of the feedback that the stack can expose. And it compounds: better engines and better prediction models produce richer, faster feedback; that feedback produces more reliable, higher-quality agents; more reliable agents drive more usage; more usage produces more data; and more data makes the engines and the predictors better still. An organization that owns both the engines and the agents and wires them together at depth sits on that flywheel. A pure-play wrapper or a generic coding agent pointed at RTL does not, and no amount of model progress changes that, because model progress is the one thing everyone shares. Figure 5: The integration flywheel: better engines and predictors yield richer, faster feedback, which yields more reliable, higher-quality agents, more usage, and more data, which improves the engines again. What This Means for EDA Tools This reframes what EDA tools have to become. They were built, for good historical reasons, around a human in the loop, GUIs, waveform viewers, and reports meant to be read by an engineer at 11pm. The next generation has to be built for an agent in the loop. That means exposing not just verdicts but diagnostics and structure as first-class, machine-readable feedback: coverage correlation, cones of influence, FSM and FIFO extraction, proof state, root-cause signals, the things a human debugs from, handed to an agent as data. It also means exposing feedback that is fast, not just rich: fast prediction models, for coverage impact, for convergence likelihood, that answer in seconds what an engine answers in days, so the agent can iterate against a surrogate and fall back to the golden engine only to confirm. And it means the agents have to be built to consume more and more of it, closing tighter loops as the tools open up deeper and faster signals. Those two roadmaps are the same roadmap. Tools expose richer feedback; agents close tighter loops around it; the loop gets tighter, and the results get more reliable; and that co-design, not a bigger model, not a cleverer prompt, is the future of chip design tools. The Bottom Line The teams that win the agent era in EDA will not be the ones with the cleverest prompt or the biggest model. Everyone gets the same models. The winners will be the ones who close the tightest, fastest feedback loop between the reasoning engine and the ground truth of the design, and get the reliability, consistency, and quality that comes with it. That ground truth, and the fast approximations that make it usable in a loop, live inside the EDA tools. Deep integration is not a feature. It is the moat, and it is the future. Learn more about Cadence's Design for AI and AI for Design strategy.https://community.cadence.com/cadence_blogs_8/b/di/posts/smarter-dft-starts-at-rtl-a-deep-dive-into-modern-dft-flows-with-genusTue, 30 Jun 2026 18:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364227sakshin/cadence_blogs_8/b/di/posts/smarter-dft-starts-at-rtl-a-deep-dive-into-modern-dft-flows-with-genus0As SoC designs become bigger in size and complexity, design‑for‑test (DFT) can no longer be treated as a late‑stage checkbox. Modern designs demand early, physically aware, and synthesis‑integrated DFT flows to meet aggressive power, performance, and area (PPA) targets—without compromising test coverage. In this webinar, we explore how DFT insertion in Cadence's Genus Synthesis Solution after RTL instrumentation enables exactly that: a scalable, production‑ready methodology that aligns logical DFT intent with physical implementation realities. Recording Available: In case you missed attending this webinar, you can watch the recording: CadenceTECHTALK: Inserting Gate-Level DFT in Genus After DFT Instrumentation at RTL Why DFT in Genus After RTL Instrumentation Matters Traditional DFT flows often introduce scan logic late, leading to: Unplanned congestion Timing regressions Multiple ECO cycles By contrast, inserting and managing DFT within the synthesis task allows teams to: Leverage early physical information Optimize scan stitching and wrapper placement Reduce iterations between synthesis and place‑and‑route What the session covers: Modern DFT flows vs. classic synthesis flows Preserving RTL‑inserted DFT IP during synthesis Test signal, scan chain, and abstract model definition IEEE 1500 wrapper insertion and scan stitching Physically aware test point insertion using Cadence's Genus, Innovus, and Modus technologies Practical scripting examples and DFT Analyzer insights Conclusion This webinar reinforced a clear message: modern DFT must be early, integrated, and physically aware. By inserting DFT in Genus after RTL instrumentation, design teams can achieve: Better PPA Cleaner scan architectures Faster convergence with fewer iterations For teams building complex SoCs, this approach is no longer optional, it's essential. Learn More Watch the internal Cadence training portal (ASK) webinar associated with this session: CadenceTECHTALK: Inserting Gate-Level DFT in Genus After DFT Instrumentation at RTLhttps://community.cadence.com/cadence_blogs_8/b/fv/posts/the-infineon-automotive-ecosystem-summit-2026Tue, 30 Jun 2026 17:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364226JEngblom/cadence_blogs_8/b/fv/posts/the-infineon-automotive-ecosystem-summit-20260The 2026 Infineon Automotive Ecosystem Summit took place in late June at the Infineon headquarters at am Campeon in Munich. The event brought together the ecosystem around Infineon's automotive microcontrollers , with a particular emphasis on software stacks and development tools. The event was very nicely produced. The exhibitor booths followed a common graphical style and physical setup with identical stands with a decorative blue LED strip. It was swelteringly hot in Munich during the event, but that did not deter the attendees from having intense and deep discussions. We ended the day with a beautiful sunset over the lake that surrounds the site. Themes The event featured speakers from both users of Infineon hardware, the partners that help build it, and the software ecosystem that unlocks the hardware functionality. There was a focus on RISC-V as that is the architecture that powers the next-generation microcontrollers from Infineon. Software-defined vehicle (SDV) is currently the big trend in the automotive industry. It affects all parts of the software stack on the central compute nodes and reaches out to the corners of the car through zonal architectures . Efficient software and system development for SDV and zonals requires that we free automotive developers from the constraints of hardware. The solution to that is to employ virtualization – simulating the hardware from individual IP blocks all the way up to networks of ECUs (central compute, zonals, controllers, and all the other electronics boxes found in the car). Virtualization supports both shift-left and long-term stretch-right software development and testing, particularly in combination with simulations of the vehicle and the world in which it operates. The Rust programming language continues to make inroads into the automotive industry. The promise of compile-time safety checking is very attractive to developers of safety- and security-critical systems. Such systems are found throughout a modern vehicle, and they become even more important with the emergence of software-defined vehicles. The event was an effective catalyst for interaction between representatives of companies that might not previously have known about each other. We had a great time explaining virtualization and how it applies across the product lifecycle and throughout the e/e architecture of a vehicle. The Mandatory Car It is an unspoken rule that every automotive-themed event must include a physical vehicle. In this case, we had a BMW Neue Klasse electric standing outside the main conference hall. It was a dark color that was really difficult to capture in a photo... The architecture of this car is a prime example of a modern SDV. There are four central compute nodes dealing with automated driving, infotainment, driving dynamics, and basic vehicle functions. These are connected to four zones: rear, roof, left, and right. Each zone has a zonal controller or two that handle the local ECUs, sensors, actuators, and other functions. Find out more about what we can offer at Cadence Automotive Solutions and VLABworks.com !https://community.cadence.com/cadence_blogs_8/b/life-at-cadence/posts/cadence-giving-foundation-leads-a-day-of-collective-community-impactTue, 30 Jun 2026 17:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364228Corporate/cadence_blogs_8/b/life-at-cadence/posts/cadence-giving-foundation-leads-a-day-of-collective-community-impact0On June 25, the Cadence Giving Foundation brought together an extraordinary coalition of companies, community leaders, and volunteers for the inaugural City Year Collective Impact Day, a powerful demonstration of what's possible when organizations come together in service of a shared purpose. Held at Mayfair Community Garden in San José, the event united 100 volunteers from 10 companies—AMD, Arm, Cadence, Cisco, EverPure Foundation, Fortinet, KLA Foundation, Palo Alto Networks, San Francisco 49ers, and ServiceNow—for a morning of hands-on service focused on strengthening a vital community space. More than a volunteer event, Collective Impact Day was designed to showcase the impact that can be achieved when collaboration extends beyond company walls. By bringing together different organizations, skill sets, and perspectives, the group demonstrated that meaningful, scalable change is possible when we act together. "Today is a powerful example of what's possible when we come together—not as individual companies, but as a collective force for good," said Phil Bishop, vice president of Corporate Marketing, Global Customer Success Team at Cadence. This spirit of collaboration was evident throughout the day, as volunteers worked side by side to create a more vibrant and welcoming space for local families. Volunteers completed a range of projects to enhance the Mayfair Community Garden, a space that supports the community through food access, education, and environmental stewardship. Together, they: Constructed 12 picnic tables and benches Laid nearly 15,000 square feet of mulch Repainted 660 feet of fencing Refreshed garden plots through weeding and new borders These efforts represent more than physical improvements; they reflect a shared investment in the long-term well-being of the San José community. This day would not have been possible without the leadership and partnership of City Year Bay Area, whose mission to expand educational access and develop future leaders through service continues to create lasting impact in communities across the country. Equally important was the City of San José's support, which helped bring this vision to life and underscored the importance of cross-sector partnerships in addressing community needs. Together, these partnerships exemplify how public, private, and nonprofit sectors can align to drive meaningful, community-centered outcomes. At Cadence, employee volunteerism is a core part of how we contribute to the communities where we live and work. Collective Impact Day reflects a broader commitment to mobilizing our employees, partners, and resources in ways that create lasting, positive change. By uniting these companies and volunteers, this event demonstrated that when we invest our time, talent, and energy together, we can create an impact far greater than any one organization could achieve alone. As the day concluded, one thing was clear: This was not just a single day of service—it was the beginning of a model for collective action that can continue to strengthen communities for years to come. Learn more about the Cadence Giving Foundation and how we're building stronger communities through volunteerism and philanthropy.https://community.cadence.com/cadence_blogs_8/b/life-at-cadence/posts/finding-our-voice-together-with-toastmastersTue, 30 Jun 2026 14:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364225Reela Samuel/cadence_blogs_8/b/life-at-cadence/posts/finding-our-voice-together-with-toastmasters0At Cadence, innovation begins with people. While breakthrough technologies, industry-leading products, and customer success define our business, it is the commitment to employee growth and development that helps make those achievements possible. Beyond technical excellence, we believe in creating opportunities for employees to build confidence, strengthen leadership skills, and continuously grow throughout their careers. The Cadence Bangalore Express Toastmasters (CETM) club is one example of that commitment in action. Recently, the club achieved an important milestone by earning Smedley Distinguished Club status , a prestigious recognition awarded to clubs that demonstrate exceptional membership growth and engagement. While the award itself is worth celebrating, what makes this achievement truly meaningful is the story behind it, a story of personal growth, shared learning, and a community committed to helping one another succeed. The Journey Behind the Recognition What happens when a room full of engineers, technologists, project managers, and professionals decides to challenge one of the most common human fears—public speaking? The answer lies not in trophies or certificates, but in the transformations that occur along the way. For some members, the journey began with something as simple as introducing themselves in a meeting. Others preferred to stay behind the slides rather than present them. Some avoided customer conversations altogether, worried about saying the wrong thing or not having all the answers. Today, many of those same individuals confidently address large audiences, lead important discussions, facilitate workshops, engage with customers, and represent their teams with conviction. The colleague who once avoided speaking in front of ten people is now presenting to hundreds. The employee who felt nervous entering a customer meeting is now building trusted relationships and leading complex discussions. The first-time speaker whose voice trembled during an introductory speech is now mentoring others and encouraging new members to take their first step. Anyone who has attended a club meeting has witnessed these transformations unfold—small moments of courage that, over time, become lasting confidence. These journeys are what make the club's achievement so meaningful. More Than Public Speaking Although Toastmasters is often associated with public speaking, its impact extends far beyond presentations. It is about confidently sharing ideas, leading discussions, facilitating collaboration across teams, and communicating effectively with customers and stakeholders. It is about listening actively, providing constructive feedback, thinking on your feet, and developing leadership skills that extend well beyond the meeting room. In today's collaborative and global work environment, these skills are invaluable. Whether presenting a technical solution, leading a cross-functional initiative, engaging with customers, or mentoring a colleague, effective communication helps turn good ideas into meaningful outcomes. A Reflection of One Cadence – One Team One of the defining strengths of the CETM Club is the diversity of perspectives it brings together. Members come from different functions, teams, backgrounds, and levels of experience. What unites them is a shared commitment to learning and helping one another grow. The club creates connections that extend beyond organizational boundaries and reinforces the principle that defines how we work every day as One Cadence – One Team . New members are welcomed with enthusiasm. Experienced members generously share their knowledge. Successes are celebrated, and challenges become opportunities to learn together. This spirit of collaboration and mutual support has helped create a thriving community where employees feel empowered to step outside their comfort zones, support one another's growth, and achieve more together than they could individually. Looking Ahead The Smedley Distinguished Club recognition marks an important milestone, but its greatest significance lies in the confidence it has helped build, the leaders it has helped develop, and the connections it has helped create. More importantly, it reflects something deeply embedded in Cadence's culture: the belief that when people are given opportunities to learn, collaborate, and grow, remarkable things can happen. The success of CETM demonstrates that professional growth is not limited to technical expertise. It is also shaped by the ability to communicate clearly, lead effectively, and inspire confidence in others. As we celebrate this achievement, we celebrate the people behind it and the culture that made it possible, a culture where employees are empowered to learn, lead, and help others succeed along the way. Congratulations to every member, mentor, officer, and supporter who contributed to this remarkable milestone. And somewhere in the audience at the next club meeting will be a future presenter, leader, mentor, or customer advocate who has not yet discovered their voice. If the club's journey so far is any indication, they are in exactly the right place to begin. Learn more about life at Cadence .https://community.cadence.com/cadence_blogs_8/b/di/posts/rtl-design-studio-bridging-rtl-design-and-physical-implementationFri, 26 Jun 2026 20:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364217sakshin/cadence_blogs_8/b/di/posts/rtl-design-studio-bridging-rtl-design-and-physical-implementation0Imagine this: your design looks perfect at RTL. Functional checks pass. Everything seems on track. But weeks later—during implementation—you hit unexpected timing violations, congestion hotspots, or power issues. Now the real cost begins: iteration, rework, delays. What if you could predict and fix all this much earlier—right at RTL? Welcome to the RTL Design Studio Training Webinar , where innovation meets efficiency, and guesswork is replaced with data-driven RTL intelligence. You can watch the recording at Cadence ASK portal with the given link: CadenceTECHTALK: Design Faster, Debug Smarter - Transform RTL Productivity with Cadence RTL Design Studio What Makes RTL Design Studio a Game-Changer? Part of Cadence's Digital Full Flow, RTL Design Studio enables: ✅ Early power estimation and reduction ✅ Fast and accurate PPAC insights (power, performance, area, congestion) ✅ Seamless integration with Genus and Innovus flows ✅ Strong RTL-to-implementation correlation This means you don't just design RTL—you design with implementation outcomes in mind. Webinar Spotlight: Key Topics You'll Explore Features and Capabilities of RTL Design Studio PPAC Optimization — Your Competitive Advantage Smarter Debugging with RDAS RDAS: Timing Debug RDAS: Power Debug RTL Design Studio Graphical User Interface What Is RDAS? RTL Debug Assistant System (RDAS) is a built-in debugging and analysis capability within Joules RTL Design Studio, designed to help engineers quickly identify and fix issues at the RTL stage. It helps analyze different types of RTL design problems, including: Timing issues – Identifies critical paths and potential violations. Congestion issues – Highlights areas that may cause routing problems later Power Issues – Supports Data gating, redundant reset analysis & improvements Structural issues – Detects inefficiencies or problematic RTL constructs Conclusion The RTL Design Studio Webinar is more than training—it's a paradigm shift. From reactive debugging to proactive optimization, from late discovery to early insight—this is how modern silicon design is done. ✅ Design smarter ✅ Debug faster ✅ Deliver better silicon References Enhance your learning with these training resources from Cadence Learning and Support: Joules RTL Design Studio: RTL Productivity and QoR Lab Demo: Analyzing Timing Issues Using RTL Debug Assistant System in Joules RTL Design Studio (Video) Lab Demo: Analyzing Structural Issues Using RTL Debug Assistant System in Joules RTL Design Studio (Video ) Lab Demo: Analyzing Congestion Issues Using RTL Debug Assistant System in Joules RTL Design Studio (Video) Analyze Pipeline Slack Using RTL Debug Assistant System in Joules RTL Design Studio (Video) Access Training Courses via Cadence Learning Management System (LMS).https://community.cadence.com/cadence_blogs_8/b/di/posts/conformal_5f00_lpecFri, 26 Jun 2026 20:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364196Atreya/cadence_blogs_8/b/di/posts/conformal_5f00_lpec0Background: Why Low-Power Equivalence Checking? In modern SoC design, advanced low-power techniques such as dynamic voltage and frequency scaling, fine-grained power gating, multiple voltage domains, and state retention introduce additional logic and complexity to the chip. Unified Power Format (UPF) or Common Power Format (CPF) files are used to capture the design's "power intent"—describing power domains, power states, special cells (isolation gates, level shifters, retention registers), and required supply conditions. These power-intent files guide EDA tools to automatically insert low-power structures into the netlist during synthesis and implementation, ensuring that circuits can safely power down or change voltage levels while preserving data or clamping signals. While essential, this process transforms the netlist beyond the plain RTL behavior, raising the question: is the low-power-augmented gate-level design still functionally equivalent to the original RTL? Traditional verification alone (e.g., simulating the design with power-emulation models) is insufficient to thoroughly validate low-power behavior. Full-chip gate-level simulations with power shut-off scenarios are extremely slow and often impractical for large designs. Instead, formal equivalence checking augmented for low power provides an exhaustive and faster approach. Cadence's solution—Conformal Low Power (CLP)—addresses this need by performing static structural and functional checks specifically for power-managed designs. It verifies that the power intent (from UPF/CPF) is correctly implemented and that no erroneous logic or mismatches have been introduced by adding power controllers and low-power cells. In general, LPEC tools like Cadence Conformal Low Power solve two key problems in modern flows: firstly, checking direct equivalence between a golden design (RTL or pre-power-optimized netlist) and a revised netlist that includes all power-management modifications (power-gating logic, inserted isolation/level shifter cells, etc.). This power-aware equivalence checking ensures the design's functional behavior remains unchanged in active (powered-up) states. Secondly, Conformal Low Power performs static rule checks to flag structural issues, such as missing or incorrectly connected isolation cells or retention control pins, as well as any inconsistencies between the power intent specification and the design implementation. By catching these errors early, Conformal Low Power reduces the risk of latent low-power bugs causing functional failures or silicon respins. Cadence Low-Power Equivalence Checking Solution LP Verify — Static Signoff Checks: 600+ static LP checks from RTL through P&R, electrical/leakage checks for LP cells, power-intent quality/syntax validation, advanced LP cell support, and Tcl waiver/filtering. LP Compare — Two-Design Consistency: Power intent, power grid/supply set, PST, crossing, and Liberty-vs-UPF consistency comparisons. LP-EC — Power-Aware Equivalence: Logic equivalence with virtual ISO insertion, ISO/RET/PSW control signal comparison, virtual logic connection per power intent, and PSW acknowledge signal checks. Usage of Cadence LPEC Many semiconductor teams utilize Cadence's low-power equivalence checking at critical verification milestones. A common practice is to run Conformal Low Power at the end of the design flow as part of final verification signoff, comparing the fully implemented gate-level netlist (with inserted power-management logic) against a golden RTL or gate-level model without those power optimizations. By doing so as a mandatory step before tapeout, teams catch any inadvertent functional divergences caused by low-power structures that might not have been caught during standard verification. This signoff usage aligns with industry recognition that low-power verification needs a formal signoff step similar to timing or functional signoff. However, more advanced users incorporate Conformal Low Power earlier in the flow as well, rather than waiting until the very end. Mature flows use CLP at multiple design stages (pre-synthesis, post-synthesis, and post-layout) as a layered defense against low-power bugs. Customers also leverage CLP's diagnostics to debug issues when an equivalence mismatch is found. What Is Lacking in Current Low-Power Verification Processes Despite the availability of static low-power verification tools like Conformal Low Power, many teams do not fully exploit them. Common gaps observed in current customer processes include: Applying low-power equivalence checking late in the flow rather than progressively. Many projects only run Conformal Low Power as a final step. This means if a logic bug was introduced by power optimizations (for example, an isolation cell clamping a signal erroneously), it may only be caught at the very end, causing late rework. Without early checks, some low-power mistakes remain hidden until final signoff. Limited coverage of power modes and corner cases. Often the formal equivalence checks are done only for the "all power domains on" state (to ensure the active-mode logic is preserved), but not all combinations of power states are considered. Some flows may not verify behaviors during transitions (powering domains on/off) except via simulation, which might not exhaustively cover all sequences. These coverage gaps leave risk that certain power-down modes or recovery sequences aren't fully validated. Recommended Improvements to LPEC Methodology To address the above gaps, the following improvements are recommended for teams using Cadence's low-power equivalence checking. These suggestions aim to ensure more thorough coverage, earlier bug detection, and smoother integration of CLP into the overall verification process: Incorporate CLP at multiple stages of the design flow: Run an initial static power intent consistency check once the UPF/CPF is written (to preempt structural mistakes). Perform an RTL-to-synthesis equivalence check after logic synthesis and after insertion of low-power structures, rather than waiting till the end. Finally, perform full-chip CLP at P&R signoff as a last line of defense. This multi-pass approach catches issues as early as possible, when fixes are less disruptive. Define metrics and a signoff checklist: Create explicit low-power verification signoff criteria. A structured checklist can formalize that the design has undergone thorough low-power verification before tape-out. Utilize Unified User Interface for Fast Debug Easy Diagnosis — LP Debug Manager, Power Intent Viewer, Domain Crossing Viewer, and PST Viewer for clear visualization. 100X+ faster PST analysis enables early-stage validation without a full netlist and supports AI diagnosis on project history. Root Cause Analysis auto-groups related violations by common cause and suggests fix actions. Multi-threading delivers scalable performance with minimal memory overhead. Distributed hierarchical flows (top-down, bottom-up, block-in-SoC-context) match flat full-chip results with automatic CPU/machine partitioning. Conclusion By systematically applying low-power equivalence checking with Cadence Conformal Low Power throughout the design cycle, verification teams can significantly reduce the risk of power-related functional bugs reaching silicon. Conformal Low Power formal approach provides exhaustive coverage of low-power scenarios and catches subtle errors that might slip past simulation. While many customers already leverage CLP for signoff, expanding its use earlier and refining processes around it will improve coverage and confidence in low-power designs. The improvements outlined in this report—from early integration to explicit verification metrics—will help organizations achieve robust low-power signoff and ultimately contribute to first-pass silicon success for power-efficient SoCs.https://community.cadence.com/cadence_blogs_8/b/cadence-support/posts/a-seamless-cadence-solution-for-rf-and-microwave-designersThu, 25 Jun 2026 21:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364016ErinGrant/cadence_blogs_8/b/cadence-support/posts/a-seamless-cadence-solution-for-rf-and-microwave-designers0As wireless technologies push into higher frequencies and tighter integration, RF, microwave, and millimeter-wave design demands have never been more rigorous. This Training Webinar recording walks through how Cadence's unified design ecosystem supports the full workflow, from initial system modeling to final manufacturing signoff. You'll see key capabilities across Cadence AWR Design Environment, Virtuoso Studio RF, and Multiphysics Verification Tools—and how they work together to help designers meet these requirements. WATCH NOW Want to Dive Deep Into the Topic? Enroll in our free online training course: Microwave Office for RF Designers Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe . Hungry for Training? Choose the Cadence Training Menu that's right for you. Or explore our Accelerated Learning option for faster skill-building. Related Resources Training Courses Planar EM Analysis in AWR Microwave Office 3D EM Analysis with Clarity in Microwave Office Clarity 3D Solver Training Byte Videos Yield Analysis in Microwave Office Controlling the Mesh for AXIEM in AWR Microwave Office Blogs The Power of Clarity in Microwave Office: Transforming 3D EM Simulation Training Webinar - Microwave Office and EM Simulation AWR Microwave Office to Allegro RF-PCB Design Flow *If you don't have an ASK account, go to Cadence User Registration and complete the requested information.https://community.cadence.com/cadence_blogs_8/b/pss/posts/everything-you-need-to-know-about-msc-nastran-2026-1Thu, 25 Jun 2026 21:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364222Cadence MSC Software/cadence_blogs_8/b/pss/posts/everything-you-need-to-know-about-msc-nastran-2026-10If you want your engineering team to get the most out of your simulation tools, MSC Nastran 2026.1 is a release worth paying close attention to. Whether your team is working through complex nonlinear contact problems, pushing topology optimization toward manufacturable designs, or running large-scale HPC jobs, this update delivers targeted improvements that reduce bottlenecks at every stage of the simulation workflow. Here's a breakdown of the enhancements we think matter most. Hybrid Contact in SOL 400: Fewer Setup Headaches, More Robust Results Contact modeling is one of the most common sources of solver failures and analyst frustration. The new hybrid Node-to-Segment (NTS) method in SOL 400 removes the need to manually define primary and secondary bodies and handles true double-sided contact natively. For complex scenarios like self-contact, large sliding, and stacked shell assemblies, this means a simpler model setup and a significantly reduced risk of convergence failures. New slip output capabilities add another layer of insight, tracking relative motion, slip rate, and accumulated slip at contact interfaces. For teams analyzing friction, wear, or joint behavior, this is data that may previously have required post-processing workarounds. Now it's built in. Multi-Part and Manufacturable Topology Optimization in SOL 200 NEO Two enhancements here work together to make topology optimization genuinely more useful in a product development context. Multi-part optimization allows multiple design regions to be solved simultaneously within a single model. The traditional sequential approach of optimizing one component, manually accounting for its neighbors, and then iterating could be slow and tended to miss system-level load-path interactions. Solving regions concurrently captures true part-to-part behavior during optimization, producing better designs in less time. The minimum gap constraint then ensures those designs are buildable. By enforcing minimum feature spacing directly within the optimization loop, it closes the gap between what the solver proposes and what manufacturing can actually produce. Fewer redesign cycles at the back end of the workflow. Amplitude-Dependent CBUSH Elements: Capturing Real-World Dynamic Behavior Bushings, dampers, and isolation systems don't behave linearly with respect to amplitude, but simulation models have historically treated them as if they did. The new amplitude-dependent CBUSH capability allows stiffness and damping properties to vary with excitation amplitude at each frequency, aligning simulation behavior with physical test results. For NVH, rotor dynamics, and vibration isolation applications, this level of fidelity directly reduces the number of physical prototype iterations needed to achieve correlation. ACMS Scalability and Robustness Improvements For teams running large models on HPC infrastructure, the ACMS enhancements address two practical pain points. Support for mildly indefinite matrices means models that previously failed or required manual intervention now solve more reliably, which is an important quality-of-life improvement when job failures are costly in both time and compute resources. Improved memory management and more efficient superelement processing mean larger models can run within existing infrastructure, with reduced risk of memory-related failures and smaller output files. Less time babysitting jobs means you can spend more time interpreting results. Convergence and Performance Gains in NLPERF The new stiffness update in SOL 400's high-performance nonlinear solver intelligently balances full and modified Newton-Raphson iterations. The practical effect is faster convergence on close-to-linear problems without sacrificing robustness on genuinely nonlinear ones. Enhanced convergence monitoring, including energy and work history output and logarithmic visualization, gives analysts better real-time visibility into solver behavior, enabling earlier intervention before a run goes off the rails. The Bottom Line for Engineering Teams MSC Nastran 2026.1 is a release focused on reducing the friction that slows simulation teams down: contact model failures, unmanufacturable optimization results, HPC job instability, and inaccurate dynamic models. At Cadence, we see these improvements as directly supporting faster design cycles, better upstream decision-making, and fewer costly late-stage surprises. If your team hasn't yet evaluated this release, now is the time. Don't miss the full list of everything included in this release over at SimCompanion !https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/the-three-phases-of-ai-adoptionThu, 25 Jun 2026 14:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364221Corporate/cadence_blogs_8/b/corporate-news/posts/the-three-phases-of-ai-adoption0Artificial intelligence is often discussed as if the industry is moving through a single technology cycle. But AI adoption is not unfolding as a single event; it is unfolding in waves. The first phase of AI adoption, infrastructure AI, is already reshaping the global technology economy. Driven by hyperscale computing, generative AI, agentic systems, and increasingly long-running reasoning models, this phase alone represents a multi-trillion-dollar market that continues to expand at extraordinary speed. Still, it represents only the first stage of a much broader transformation that will eventually extend from data centers to autonomous systems and scientific discovery itself. This broader view of AI adoption also reflects Cadence's long-standing systems-oriented approach to intelligent engineering, where infrastructure, computational software, and AI increasingly evolve as interconnected layers of innovation. Each wave introduces new opportunities and increasingly complex engineering challenges. The first phase centers on building the infrastructure required to power intelligence. The next step extends intelligence into systems that can perceive and interact with the physical world. Beyond that lies perhaps the most ambitious opportunity yet: applying AI to accelerate scientific discovery itself. Industry discussions have pointed to AI demand increasing by as much as over the next five years. Even assuming major advances in hardware and software efficiency—including more efficient models, mixed-precision computing, and improved accelerator architectures—the resulting growth rates could still translate into sustained annual expansion of roughly 30–60%. But the current AI buildout represents only the opening chapter. Each phase builds on the previous one while expanding the boundaries of what intelligent systems can do. Phase One: Infrastructure AI The first phase of AI adoption is the one reshaping entire industries today. Infrastructure AI includes the technologies required to train, deploy, and scale modern AI systems—advanced semiconductors, AI accelerators, high-bandwidth memory, hyperscale data centers, communications infrastructure, and edge computing. Demand for these systems continues to accelerate rapidly. The rise of agentic AI systems and long-running reasoning models is further accelerating infrastructure demand, increasing the need for compute capacity, memory bandwidth, networking performance, and system-level optimization across the AI stack. What makes this moment particularly significant is that AI demand is growing faster than traditional engineering productivity can scale. Yet building larger infrastructure is no longer simply a matter of increasing compute capacity. As AI models become larger and more complex, performance increasingly depends on optimizing entire systems rather than individual components. Chips, chiplets, packaging technologies, networking architectures, cooling systems, power delivery, and data center environments must operate as tightly integrated platforms. The challenge is shifting from building more infrastructure to building smarter infrastructure. This shift is already changing how engineering teams think about system design. Performance, efficiency, and scalability can no longer be optimized independently; they increasingly need to be addressed simultaneously across the entire stack. But intelligence does not stop at data centers. The next wave begins when AI moves from processing information to interacting directly with the physical world. Phase Two: Physical AI Until now, much of AI has lived inside data centers and software environments. Physical AI represents the next major shift: moving intelligence into machines and systems that can perceive, reason, and act within the real world. Physical AI introduces autonomous vehicles, drones, robotics, industrial systems, and intelligent edge platforms that are expected to reshape industries already measured in trillions of dollars. The automotive industry alone represents a multi-trillion-dollar market, while industry projections increasingly point to robotics becoming one of the largest technology categories ever created, with long-term opportunities potentially reaching tens of trillions of dollars. The opportunity extends across transportation, industrial automation, healthcare, logistics, and intelligent machines designed to operate alongside people and within complex environments. But enabling intelligence to operate in the physical domain introduces entirely new engineering challenges. Training an AI model inside a data center is fundamentally different from enabling a robot to navigate a factory floor or allowing an autonomous system to safely operate in dynamic environments. AI is no longer simply processing information; it is increasingly interacting directly with the world around it. Systems require more than compute power and inference capability. They must understand motion, physical interactions, environmental conditions, safety constraints, and unpredictable behavior. These requirements are increasing the importance of computational software and high-fidelity simulation because intelligent systems first need to understand reality before they can safely operate within it. Increasingly, simulation is evolving into broader digital twin environments that continuously connect virtual and physical behavior. Beyond modeling structural behavior, thermal effects, motion, and system interactions before deployment, digital twins help engineers validate, optimize, and refine performance across the lifecycle of increasingly complex systems. Closing the gap between simulation and operational behavior is becoming one of the defining engineering challenges of the physical AI era. As intelligence expands into physical systems, engineering itself becomes increasingly multidisciplinary. Phase Three: Sciences AI Beyond infrastructure and physical systems lies the third phase of AI adoption: applying intelligence to science itself. If infrastructure AI teaches machines to process information and physical AI enables machines to understand the world, sciences AI may help uncover knowledge that humans have not yet discovered. Over the long term, this may ultimately become the largest opportunity of all. Scientific problems often involve enormous search spaces and highly complex interactions that can take years—or even decades—to explore through traditional methods. AI has the potential to accelerate discovery across material science, molecular modeling, biology, and drug development in ways that were previously difficult to imagine. Many industry leaders believe life sciences may ultimately become one of the largest opportunities for AI-driven discovery, particularly as AI systems become increasingly capable of modeling biological complexity and accelerating molecular research. Rather than simply automating existing processes, AI begins helping researchers uncover entirely new possibilities. The same capabilities that enable intelligent systems, massive computational scale, physically grounded models, and intelligent exploration—can increasingly help scientists navigate complexity and identify patterns that may otherwise remain hidden. In this phase, AI shifts from helping humans perform tasks more efficiently toward helping discover solutions that may never have been considered before. The Future Extends Beyond AI Models These phases are not isolated technology trends. They represent a progression in how intelligence expands. Infrastructure AI creates the systems that power intelligence. Physical AI moves intelligence into the real world. Sciences AI applies intelligence to discovery itself. As new phases start, the previous ones do not stop. The compute required to generate and distribute the models and compute for physical AI and sciences AI only increase the opportunity for the designers of the silicon and systems infrastructure. Across all three phases, one principle remains constant: progress depends on more than AI alone. Increasingly capable systems require advances in computing infrastructure, computational software, and intelligent engineering working together. As AI systems become more sophisticated, engineering itself becomes more intelligent, creating a continuous cycle in which technology not only drives innovation but increasingly helps create it. The future of AI will not be defined solely by larger models or faster hardware. It will be defined by how effectively intelligence and engineering evolve together—and by how successfully we move from building intelligent systems to building systems that help create the next generation of intelligence itself. Explore the rest of this series to learn how Cadence’s Design for AI and AI for Design strategy, together with the Three-Layer Cake framework , helps connect infrastructure, intelligent systems, and the future of AI-driven engineering.https://community.cadence.com/cadence_blogs_8/b/pcb/posts/getting-started-with-skill-scripts-Thu, 25 Jun 2026 08:20:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364155anandd/cadence_blogs_8/b/pcb/posts/getting-started-with-skill-scripts-0Whether you are new to Allegro X PCB Expert or an experienced layout designer, you may have wondered how SKILL routines are installed and loaded into the tool. SKILL programs are widely used to automate repetitive tasks and improve productivity in PCB Design workflows. If you have programming experience, you can create your own SKILL routines. However, even if you are not a programmer, you can still benefit from many ready‑to-use SKILL scripts that are freely available and easy to apply. This blog shows you where to find useful SKILL scripts and how to access them. How SKILL Improves Productivity in Allegro X Cadence SKILL is a high‑level, interactive, functional programming language used to customize and automate tasks within Cadence tools. Like general-purpose programming languages such as C, Python, and Perl, SKILL supports automation and scripting. What makes it especially powerful is its deep integration with Cadence tools and APIs, allowing you to control and extend your design environment directly within Allegro X PCB Expert. Why Access to SKILL Scripts Matters It is important to ensure you can access scripts whenever you need them. In many real-world situations, having access to SKILL scripts is essential. When working at a customer site without access to internally developed scripts When upgrading or replacing your system and wanting to retain existing automation When improving productivity quickly, using proven scripts instead of building from scratch These scenarios highlight the need for easily accessible SKILL resources. To support these needs, let’s look at where you can find SKILL scripts. Finding Sample SKILL Scripts Here are some reliable ways to find and start using SKILL scripts. Cadence ASK Portal: Allegro SKILL Library The Cadence ASK portal provides a wide range of SKILL scripts that you can use directly in your design environment. You can access them from the Allegro PCB Editor SKILL Code Library on the Cadence ASK portal. Allegro X Scripting: SKILL Forum The Allegro X Scripting – SKILL Forum in the Cadence Community is another valuable resource. To access the SKILL forum, navigate to the Cadence Community Forums (PCB Design and IC Packaging) and select Allegro X Scripting – SKILL . This forum is an active space where users and experts share solutions, best practices, and useful scripts. Over time, it has become a useful repository of SKILL scripts. You can also post questions and get help from the community. Local Installation Examples Some SKILL scripts are included with your tool installation. You can find them under: /share/pcb/examples/skill/ A sample local installation directory is shown below: These examples are useful for learning SKILL syntax, understanding common automation scripts, and testing small scripts. Using SKILL Scripts Once you have a SKILL script, you can load and run it in Allegro X PCB Expert using the SKILL command window. You can also configure scripts to load automatically at startup by adding them to your environment or initialization files. This makes it easy to reuse frequently used scripts and integrate them into your daily workflow. Conclusion Finding and using the right SKILL scripts can significantly improve your efficiency in Allegro X PCB Expert. With resources such as the Cadence ASK portal, community forums, and local installation examples, you can quickly discover and apply proven scripts to your workflow. As you explore further, SKILL becomes a powerful tool that helps you automate repetitive tasks and focus more on design work, making your overall workflow faster and more efficient. To learn in detail about this course, enroll in the course Allegro X PCB Editor SKILL Programming Language Training on the Cadence ASK portal. Click the Training Bytes link or visit Cadence ASK and search for Free Online Training Bytes (Videos) under the video library. Want To Level Up Even Faster? If you want structured learning, pair the Training Bytes with Accelerated Learning , where you can test out of what you already know and focus only on areas that need attention—saving even more time. Cadence Training Services now offers free Digital Badges for all popular online training courses. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can add the digital badge to your email signature or any social media channels, such as Facebook or LinkedIn, to highlight your expertise. To find out more, see the blog post Take a Cadence Masterclass and Get a Badge . You might also be interested in the training Learning Map that guides you through recommended course flows as well as tool experience and knowledge-level training modules. To find information on how to get an account, visit the Cadence Learning and Support portal. SUBSCRIBE to the Cadence training newsletter to be updated about upcoming training, webinars, and much more. If you have any questions about courses, schedules, online training, blended/virtual live training, or public or onsite live training, reach out to us at Cadence Training . Related Training Bytes Using SKILL in the PCB Editor (Video Channel) Using Multiway Branching (Video) Writing Good SKILL Code (Video) Reading Data from a File (Video) Writing Data to a File (Video) Related Blogs Introduction to SKILL BoardSurfers: Creating GUIs Using Allegro SKILL BoardSurfers: Training Insights: Improve your ‘SKILL’ with Allegro PCB Editor BoardSurfers: The SKILL Cheat Sheet: All You Need to Know About SKILL Language BoardSurfers: Implementing SKILL Codehttps://community.cadence.com/cadence_blogs_8/b/data-center/posts/cadence-at-ashrae-advancing-ai-infrastructure-through-integrated-engineeringWed, 24 Jun 2026 22:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364220Corporate/cadence_blogs_8/b/data-center/posts/cadence-at-ashrae-advancing-ai-infrastructure-through-integrated-engineering0From June 27 to July 1, industry leaders will gather in Austin, Texas, for the 2026 ASHRAE Annual Conference —one of the most important forums shaping the future of the built environment and thermal management. As AI continues to drive unprecedented demand for data centers, this year's event comes at a critical moment for the industry. For decades, ASHRAE has played a central role in defining standards and best practices across HVAC, energy efficiency, and system design. Today, that mission is expanding. The rapid rise of AI infrastructure is pushing power density, cooling requirements, and system complexity to new extremes—requiring closer collaboration across mechanical, electrical, and digital engineering domains. Cadence will be actively participating in this year's conference, contributing to key discussions on modeling, simulation, and AI-driven optimization for next-generation data centers. Featured Sessions: Modeling and AI in Focus Cadence's Matthew Käufeler will present in two sessions that highlight the evolving intersection of physics-based modeling and artificial intelligence: Seminar 50: Machine Learning or Traditional Compact Modelling – What, When and Why? Seminar 62: Combining CFD-Informed AI with AI-Informed CFD for Enhanced Data Center Decision Making These sessions address a fundamental challenge facing engineers today: how to effectively model increasingly complex systems that span chip, system, and facility scales. Traditional compact models remain essential for their physical accuracy, interpretability, and reliability—particularly in early-stage design and validation. At the same time, AI is unlocking new capabilities, enabling faster simulations, adaptive optimization, and real-time operational insights. The conversation is no longer about choosing one approach over the other, but about combining them. Hybrid modeling strategies—where physics-based methods are augmented by AI—are emerging as a powerful way to balance accuracy, speed, and scalability. From Simulation to Real-Time Intelligence As AI factories scale toward hundreds of megawatts and beyond, static analysis alone is no longer sufficient. Data center operators need faster, more adaptive decision-making capabilities that extend beyond design into live operations. By integrating computational fluid dynamics (CFD) with AI, engineers can create intelligent workflows where simulation and data continuously inform each other. CFD-informed AI models enable near-real-time predictions, while AI-guided simulations focus computational effort where it has the greatest impact. This convergence is also foundational to digital twin approaches. Platforms such as the Cadence Reality Digital Twin Platform build on these principles, combining high-fidelity simulation with operational data to create continuously evolving models of infrastructure. The result is a more dynamic way to monitor performance, anticipate issues, and optimize systems across their full lifecycle. Engaging with the ASHRAE Community Cadence's participation in ASHRAE reflects a broader commitment to advancing industry dialogue around modeling innovation and AI-driven engineering workflows. Events like ASHRAE are critical because they bring together experts across traditionally separate disciplines. Solving the challenges of AI infrastructure—whether thermal constraints, power efficiency, or system integration—requires collaboration that spans chip design, facility engineering, and operations. Meet Us in Austin As the industry transitions toward highly integrated, AI-driven infrastructure, the importance of cross-domain collaboration and advanced modeling has never been greater. The ASHRAE Annual Conference provides a unique opportunity to engage with peers, exchange ideas, and explore emerging technologies shaping the future. We look forward to connecting with customers, partners, and industry experts in Austin. Join Cadence at the ASHRAE Annual Conference to learn how integrated modeling, AI, and digital twin approaches are enabling smarter, more efficient, and more scalable AI infrastructure. Learn more about the Cadence Reality Digital Twin Platform .https://community.cadence.com/cadence_blogs_8/b/corporate-news/posts/finding-what-truly-moves-you-honoring-alberto-sangiovanni-vincentelliWed, 24 Jun 2026 16:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364211Corporate/cadence_blogs_8/b/corporate-news/posts/finding-what-truly-moves-you-honoring-alberto-sangiovanni-vincentelli0"Finding what truly moves you is happiness. Success is measured in the lasting impact of your ideas." Alberto Sangiovanni-Vincentelli's words offer a fitting reflection of a career defined by vision, leadership, and enduring impact on the electronic design automation (EDA) industry. Industries are transformed by individuals who see further, think differently, and build what does not yet exist. Alberto Sangiovanni-Vincentelli is one of those rare visionaries. Celebrating Alberto Sangiovanni-Vincentelli's nomination for the UC Regents Innovation Awards in the Distinguished Lifetime Achievement category means celebrating a career that has left a lasting mark on the semiconductor industry—one best appreciated through the story in his own words , from five decades at UC Berkeley to the defining moments that helped shape modern EDA. Alberto's impact is remarkable not simply for its scale, but for its permanence. Through pioneering advances in circuit simulation, logic synthesis, and design automation, he helped establish the intellectual and technological foundations on which modern chip design continues to evolve. His contributions did more than solve difficult engineering problems; they expanded the possibilities of what engineers, researchers, and companies could imagine and ultimately achieve. What distinguishes Alberto's body of work is its rare breadth. He helped shape both the science of EDA and the industry that brought those innovations to scale. Over nearly 50 years at UC Berkeley, he guided generations of researchers and engineers, developed tools that proved critical in the era of Intel's landmark 386 chip, and stood at the center of one of EDA's defining entrepreneurial moments. Alberto stands among the very few who have shaped both theory and industry with such clarity, rigor, and lasting impact. That impact continues through leadership as much as innovation. As a member of the Cadence Board of Directors, Alberto has continued to help shape the future of the industry with the same depth of insight and sense of purpose that marked his pioneering career. This recognition honors more than a lifetime of achievement; it celebrates a remarkable record of innovation that continues to inspire across academia, industry, and the generations of innovators who will build on his example. We congratulate Alberto on this well-earned nomination! Watch "How I Co-Founded Two $100B Chip Giants: A Semiconductor Legend's Story"https://community.cadence.com/cadence_blogs_8/b/di/posts/what-changed-in-your-design-stop-guessing-let-stylus-compare-show-youWed, 24 Jun 2026 12:27:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364218sakshin/cadence_blogs_8/b/di/posts/what-changed-in-your-design-stop-guessing-let-stylus-compare-show-you0Introduction: When “Spot the Difference” Becomes a Design Bottleneck Every digital design engineer has faced it—two databases, countless changes, and one critical question: what actually changed ? Whether it’s a new ECO, a different tool version, or a late‑stage timing fix, manually tracking differences across runs can slow teams down and hide real issues. Stylus compare was built to solve this problem. Covered in Cadence's customer education training, this powerful utility turns database comparison into an interactive, visual, and highly productive experience —directly inside Innovus and other back‑end tools. Want to take a deep dive? Join our CadenceTECHTALK to identify the proven benefits of stylus compare. CadenceTECHTALK: Stylus Compare - A Comprehensive Utility for Comparison of Common UI Databases Using Innovus and Other Back-End Tools Why Stylus Compare Matters Traditional diff tools weren’t designed for physical layouts, timing paths, or hierarchical databases. Stylus compare fills that gap by enabling real‑time comparison of two stylus databases , helping engineers quickly understand what changed, where it changed, and why it matters . With support for Innovus, Tempus, Voltus , and mixed tool versions, stylus compare becomes a common cockpit for debug, ECO validation, and correlation analysis—without leaving your design environment. What the Training Covers This webinar walks through the benefits of stylus compare including: Implementation and ECO Comparison Detect ECO changes in instances, routing, layers, and timing Modify designs and re‑compare in the same session Physical and Connectivity Checks Floorplan, layers, nets, instances, cells, and multibit flops Visual markers and logs highlight differences instantly Support for post‑mask and base‑layer Timing Correlation and Debug Side‑by‑side timing path comparison with merged reports Identify missing cells, resized logic, and RC differences Hierarchical Design Support Compare block vs. top‑level designs in context and validate timing Support for master/clone hierarchies and 3D‑IC flows Conclusion: Compare Smarter, Not Harder Stylus compare transforms design comparison from a tedious task into a fast, visual, and repeatable workflow . By bringing physical, timing, and attribute comparisons into a single environment, it empowers engineers to focus on fixing issues—not finding them. If your work involves frequent design iterations, ECOs, or tool correlations, stylus compare is no longer optional—it’s essential .https://community.cadence.com/cadence_blogs_8/b/di/posts/from-rtl-to-gds-why-timing-correlation-makes-or-breaks-your-tapeoutWed, 24 Jun 2026 11:48:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1364219sakshin/cadence_blogs_8/b/di/posts/from-rtl-to-gds-why-timing-correlation-makes-or-breaks-your-tapeout0When “Clean Timing” Isn’t Really Clean Your synthesis run looks perfect—no major violations, healthy slack. But weeks later, signoff won’t converge. If this sounds familiar, you’ve hit the hidden cost of poor timing correlation. Timing correlation isn’t just a signoff issue—it spans the entire RTL-to-GDS flow. When it breaks, teams waste cycles debating mismatches, ECO loops grow, and QoR suffers. Want to fix it? Join our Cadence TECHTALK to learn proven strategies to close the gap early. CadenceTECHTALK: Faster Turnaround, Better QoR - Timing Correlation Recipes Across RTL to GDS Where Correlation Breaks RTL and synthesis: Missing physical effects, inconsistent models Pre- to post-route: RC, SI, and metal fill differences Constraints and analysis: SDC mismatches, derates, GBA vs. PBA gaps How Cadence Helps You Fix It Correlation improves when physical reality is introduced earlier in the flow: Joules: Early PPAC visibility at RTL Genus + Innovus: Better pre-route timing prediction Key techniques covered in the webinar: Early Clock Flow (ECF) and Detailed Routing Integrated Virtual Metal Fill (IVMF) Early PBA (ePBA) Integrated Signoff Closure (ISC) What You’ll Learn in This TECHTALK In this session, you’ll discover: Proven methods to debug mismatches step by step Techniques to improve pre-route to signoff alignment How AI-driven optimization reduces over-constraint References Innovus to Tempus Timing Correlation https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od00000066PvSEAU Ostrich RC Correlation https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050M9EAI Timing Correlation using TimeEx 3.0 https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000050WcEAI Integrated Virtual Metal Fill RAK (IVMF) https://support.cadence.com/apex/articleattachmentportal?id=a1O3w000009kuIgEAI Statistical On-Chip Variation (SOCV) with Spatial Timing Derates in Tempus https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009EWOcUAO Stylus Compare 23.1 (CUI) RAK https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V0000091CiDUAU