VLSI IEEE Project Center in Chennai

VLSI IEEE 2017 TOPICS

2018-04-04T14:54:00.000+05:30

VLSI PROJECT TOPICS

2003

DCT-Based Image Watermarking Using Subsampling- Verilog with Matlab
VLSI Implementation of Invisible Digital Watermarking Algorithms- Verilog with Matlab

2004

An FPGA-based Architecture for Real Time Image Feature Extraction- Verilog with Matlab
Contrast Enhancement of Color Images using Tunable Sigmoid Function- Verilog with Matlab
Robust DWT-SVD Domain Image Watermarking Embedding Data in All Frequencies
Shift Invert Coding (SINV) for Low Power VLSI
VLSI Implementation of Discrete Wavelet Transform (DWT) and IDWT for Image Compression- Verilog with Matlab

2005

A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)- Verilog with Matlab
Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
Visual Attention Driven Image to Video Adaptation- Verilog with Matlab

2006

A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
A Verilog Implementation of UART Design with BIST Capability
An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing
Image Compression with Different Types of Wavelets- Verilog with Matlab

2007

A Low-Power Multiplier With the Spurious Power Suppression Technique
A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier
Design and Implementation of a low complexity real lossless Image compression method for wireless endoscopy capture system- Verilog with Matlab
Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation
Low-power and high-quality Cordic-based Loefﬂer DCT for signal processing
Low-Power Built-In Logic Block Observer Realization for BIST Applications-VHDL
Video Adaptation for Small Display Based on Content Recomposition- Verilog with Matlab
VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application

2008

A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
FPGA Based Design of a Novel Enhanced Error Detection And Correction Technique
FPGA Implementation of USB Transceiver Macrocell Interface with USB2.0 Specifications
FPGA Implementation of a Scalable Encryption Algorithm
Fuzzy based PID Controller using Verilog HDL for Transportation Application
Implementation of 64 Point FFT using Vedic Multiplier
Implementation of IEEE 802.11 a WLAN Baseband Processor
Multiplier design based on ancient Indian vedic muliplier
Research on Fast Super-resolution Image Reconstruction Base on Image Sequence-Verilog with Matlab
VLSI Implementation of an Edge-Oriented Image Scaling Processor- Verilog with Matlab

2009

3D Discrete Wavelet Transform VLSI Architecture for Image Processing- Verilog with Matlab
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM- Convolutional Encoders
Biometric Encryption using Fingerprint Fuzzy Vault for FPGA-based Embedded Systems- Verilog with Matlab
CSI Multimedia Architecture
Fast Scaling in the Residue Number System
Design and Implementation of Boundary-Scan Circuit
FPGA Based Power Efficient Channelizer For Software Defined Radio
FPGA-Based Face Detection System Using Haar Classifiers- Verilog with Matlab
Hardware Algorithm for Variable Precision Multiplication on FPGA
Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL- Verilog with Matlab
VLSI Implementations of the Cryptographic Hash Functions MD6

2010

FPGA Implementations of the Hummingbird Cryptographic Algorithm
A High-speed 32-bit Signed Unsigned Pipelined Multiplier
Software-Defined Radio for OFDM Transceivers
VLSI Implementation of Fully Pipelined Multiplier less 2D DCT IDCT Architecture for JPEG- Verilog with Matlab
Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip
High Speed and Low Space Complexity FPGA Based ECC
FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms- Verilog with Matlab
FPGA Implementation of Modular Multiplication methods using Cellular Automata
FPGA Implementation of High Performance LDPC Decoder using Modified 2-bit
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
Coherent Amplitude Modulated QAM-QPSK
A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform- Verilog with Matlab
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modiﬁed Booth Algorithm
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264AVC- Verilog with Matlab
A High Performance Binary to BCD Converter for Decimal Multiplication
An Efficient Architecture for 3 D Discrete Wavelet Transform-Verilog HDL with Matlab

2011

A New Reversible Design of BCD Adder
A Multichannel Watermarking DCT-DWT- Verilog with Matlab
An Efficient Implementation of Floating Point Multiplier
An implementation of a 2D FIR filter using the signed-digit number system- Verilog with Matlab
Automatic Road Extraction using High Resolution Satellite Images based on Mean Shift Method- Verilog with Matlab
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
Design and FPGA Implementation of CORDIC-based 8-point 1D DCT Processor
Design and Implementation of APB Bridge based on AMBA 4.0
Design and VLSI implementation of high-performance face-detection engine for mobile applications- Verilog with Matlab
Design Enhancement of Combinational Neural Networks Using HDL based FPGA Framework for Pattern Recognition- Verilog with Matlab
Efficient VLSI Architecture for Discrete Wavelet Transform- Verilog with Matlab
FPGA based FFT Algorithm Implementation in WiMAX Communications System
FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise Two Approaches- Verilog with Matlab
High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
Image Encryption Based On AES Key Expansion- Verilog with Matlab
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA- Verilog with Matlab
PCFICH Channel Design for LTE using FPGA- Verilog with Matlab
Pipelined Architecture for FPGA Implementation of Lifting-Based DWT- Verilog with Matlab

2012

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform- Verilog with Matlab
A Region Merging Approach for Image Segmentation on FPGA- Verilog with Matlab
An Efficient Viterbi Decoder
Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
Design of Low Power TPG Using LP-LFSR
FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization- Verilog with Matlab
HDL Design for Image Segmentation using Gabor filter for Disease Detection- Verilog with Matlab
High Speed and Area Efficient Vedic Multiplier
High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers
Improved Architectures for a Fused Floating-Point Add-Subtract Unit
Low-Power and Area-Efficient Carry Select Adder
Low-Power Variation-Aware Flip Flop
Modified Architecture for Real-Time Face Detection using FPGA- VHDL with Matlab
Very Low Resolution Face Recognition Problem- Verilog with Matlab
Viterbi-Based Efficient Test Data Compression
VLSI Architecture of Arithmetic Coder Used in SPIHT- Verilog with Matlab
FPGA Implementation of MIMO-OFDM STBC Systems-Verilog with Matlab

2013

Cordic for Fixed Angle Rotation
Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
Design Of High Speed Floating Point Mac Using Vedic Multiplier And Parallel Prefix Adder
Design of High Speed Low Power Multiplier using Reversible logic-a Vedic Mathematical Approach
Design of High-speed low power Reversible Logic BCD Adder Using HNG gate
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic Techniques for Compensating Memory Errors in JPEG2000- Verilog with Matlab
Visible and Infrared Image Fusion using the Lifting Wavelets- VHDL with Matlab
VLSI Implementation of an Adaptive Edge -Enhanced Image Scalar for RealTime Multimedia Applications- Verilog with Matlab
VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications- Verilog with Matlab
Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform Neural Network Architecture- Verilog with Matlab
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm-Verilog with Matlab
Design and simulation of Gabor filter using Verilog HDL-Verilog HDL with Matlab

2014

A Distributed Canny Edge Detector Algorithm and FPGA Implementation- Verilog with Matlab
A New Secure Image Transmission Technique via Secret-Fragment-Visible Mosaic Images- Verilog with Matlab
Design and Implementation of Orthogonal Code Convolution Using Enhanced Error Control Technique
FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm
High Speed Convolution and Deconvolution Algorithm (Based on Ancient Indian Vedic Mathematics)
SW-HW Implementation of Image Covariance Descriptor For Person Detection Systems
VLSI Based Image Zooming Application by a Novel Adaptive Edge Enhancement Technique- Verilog with Matlab
Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform-Verilog with Matlab
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay-Verilog with Matlab
ASIC Implementation of Two Stage Pipelined Multiplier
Hardware Software Co-Simulation of Edge Detection for Image Processing System-Verilog with Matlab
Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform-Verilog with Matlab
An Embedded System-on-Chip Architecture for Real-time Visual Detection and Matching-Verilog HDL with Matlab

2015

Reviewing High-Radix Signed-Digit Adders
A New-High Speed-Low Power-Carry Select adder Using Modified GDI
Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
A Modified Partial Product Generator for Redundant Binary Multipliers
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
Design and Analysis of Approximate Compressors for Multiplication
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

2016

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
A Low Power 16 Bit Vedic Divider for High Speed VLSI Applications- Verilog HDL
High Performance VLSI Architecture for 3-D Discrete Wavelet Transfor-Verilog HDL with Matlab
An Analysis of Image Compression Techniques In Wireless Multimedia Sensor Networks-Verilog HDL with Matlab
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m)on FPGA
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
On Efficient Retiming of Fixed-Point Circuits
Hybrid LUT/Multiplexer FPGA Logic Architectures
Concept, Design, and Implementation of Reconfigurable CORDIC
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes

2017

Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT
An Efficient Signature Verification Method Based on an Interval Symbolic Representation and Fuzzy Similarity Measure
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction
Reconfigurable Constant Multiplication for FPGAs
Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT

The above listed topics are just for reference. If you have any new Ideas/Papers send to us at info@verilogcourseteam.com or Call +91 98942 20795

Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform

2017-04-10T10:58:00.001+05:30

Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform

Abstract—An efficient dual-scan parallel flipping architecture for a lifting-based 2-D discrete wavelet transform is presented. The proposed novel algorithm is based on a flipping technique to implement a modular and hardware-efficient architecture with a very simple control path. In the proposed algorithm, the serial operation of the lifting data flow is optimized using parallel computations of independent paths in advance with pipeline operation to minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency.

LIFTING SCHEME
The basic principle is to break up the polyphase matrix of the wavelet filters into a sequence of alternating upper and lower triangular matrices and a diagonal normalization matrix. According to the basic principle, the polyphase matrix of a 9/7 lifting filter is expressed as,

(1)

where α(1 + z−1) and γ(1 + z−1) are the predict polynomials, β(1 + z) and δ(1 + z) are the update polynomials, and K is the scale normalization factor. The 9/7 lifting filter coefficients are α = −1.586134342, β=−0.052980118, γ=0.8829110762, and δ=0.4435068522, and the scaling coefficient is K = 1.149604398. Given input sequence x(n), with n = 0, 1, . . . , N − 1, the lifting algorithm steps are given by,

Outputs di and si are the high-pass and low-pass wavelet coefficients.

Fig. 1. Architecture block diagram.

Equations (2)–(4) and (6) can be written after rearranging as,

Project Design Flow,

Select input image
Convert into pixel values using Matlab
Select even and odd location pixels
Choose filter type and take the α,β,γ,δ values
Apply DWT filter process according to equation 10-15
Get the values of Si and di
Repeat the same process for whole image
Display Wavelet Image

Simulation Video Demo

Cordic based Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

2017-04-07T11:35:00.001+05:30

Cordic based Floating Point Butterfly Architecture Based on Binary Signed Digit Representation

Abstract—Fast Fourier transform (FFT) co-processor, having a significant impact on the performance of communication systems, has been a hot topic of research for many years. The FFT function consists of consecutive multiply add operations over complex numbers, dubbed as butterfly units. Applying floating-point (FP) arithmetic to FFT architectures, specifically butterfly units, has become more popular recently. It offloads compute-intensive tasks from general-purpose processors by dismissing FP concerns (e.g., scaling and overflow/underflow). However, the major downside of FP butterfly is its slowness in comparison with its fixed-point counterpart. This reveals the incentive to develop a high-speed FP butterfly architecture to mitigate FP slowness. This brief proposes a fast FP butterfly unit using a devised FP fused-dot product- add (FDPA) unit, to compute AB ± CD ±E, based on binary signed- digit (BSD) representation. The FP three-operand BSD adder and the FP BSD constant multiplier are the constituents of the proposed FDPA unit. A carry-limited BSD adder is proposed and used in the three-operand adder and the parallel BSD multiplier so as to improve the speed of the FDPA unit. Moreover, modified Booth encoding is used to accelerate the BSD multiplier. The design is developed based on Cordic Algorithm using Floating Point Butterfly.The result results show that the proposed FP butterfly architecture is much faster than previous counterparts but at the cost of more area.

FFT butterfly architecture with expanded complex numbers

A butterfly architecture using redundant FP arithmetic, which is useful for FP FFT co-processors and

contributes to digital signal processing applications. Although there are other works on the use of redundant FP number systems, they are not optimized for butterfly architecture in which both redundant FP multiplier and adder are required. The novelties and techniques used in the proposed design include the following.
1) All the significands are represented in binary signed digit (BSD) format and the corresponding carry-limited adder is designed.
2) Design of FP constant multipliers for operands with BSD significands.
3) Design of FP three-operand adders for operands with BSD significands.
4) Design of FP fused-dot-product-add (FDPA) units (i.e., AB ± CD ± E) for operands with BSD significands.

Simulation Video Demo

Design and Simulation of Gabor filter using verilog HDL

2017-04-05T11:13:00.000+05:30

Design and Simulation of Gabor filter using verilog HDL

Abstract- The most important measurement element in fingerprint recognition process is the texture of the fingerprint. The computational complexity of a fingerprint recognition process depends on fingerprint enhancement. The quality of the fingerprint image can be enhanced using Gabor filter. The objective of Gabor Filter in fingerprint recognition is to segment the texture of fingerprint. This includes the design of a single filter to segment multiple textures and the design of multiple filters to segment multiple textures. The computational efficiency becomes increasingly important as the size of images, number of Gabor prefilters, number of Gaussian postfilters, and number of textures increases.This project is developed using Verilog HDL with Matlab.The input image is converted into pixel values and stored in text file.Gabor Filter Algorithm is developed using Verilog HDL and the input image pixel values are passed to the Verilog HDL design.The filtered values are converted into image format using Matlab.

Project Design Flow

Kernel Values

Simulation Video Demo

FPGA Implementation of MIMO-OFDM STBC Systems

2017-04-04T11:03:00.002+05:30

FPGA Implementation of MIMO-OFDM STBC Systems

Multiple-input multiple-output (MIMO) combined with Orthogonal Frequency Division Multiplexing (OFDM) techniques has been received a great attention in recent years. It is also well-known that Space-Time Block Coding (STBC) is the typical approach to significantly increase diversity gain. In this project, we present design of MIMO-OFDM STBC systems based on VLSI platform which consists of Verilog HDL and Matlab Program. The project is designed based on MIMO OFDM STBC system using Radix-4 256 Point FFT and 4QAM modulation with different numbers of receiver antennas in MIMO multipath fading environments. Radix-4 FFT is used to achieve low power design. The design is simulated using Matlab with Modelsim and performance is evaluated based of BER for various inputs such as image and text.

MIMO STBC

A block diagram of a MIMO STBC system with 2 transmit antennas and NR receive antennas is shown in below Fig.

Block diagram of a MIMO STBC system

At transmitter side, input data is encoded by Alamouti STBC as follows:

x₁(T)=s(T)

x₂(T)=s(T+1) (3.1)

x₁(T+1) =-s*(T+1)

x₂(T+1) =s*(T) (3.2)

Where s(T) and s(T+1) denote input data symbols at symbol duration T and T+1, x(T) and x(T+1) denote encoded data symbols at the symbol duration T and T+1. Encoded data then are transmitted through two transmit antennas.

At the receive side, received signals at the symbol duration T and T+1 are given by:

r_i(T)=r_i1.x₁(T)+h_i2.x₂(T)+n_i(T)

=h_i1s(T)+h_i2s(T+1) +n_i(T) (3.3)

r_i(T+1) =h_i1.x₁(T)+h_i2.x₂(T+1) +n_i(T+1)

=h_i1s*(T+1) +h_i2s*(T) +n_i(T+1) (3.4)

where yi(T) and yi(T+1) denote received signals obtained at the ith receive antenna at the duration T and T+1, hij denotes the channel response from the jth transmit antenna to the ith receive antenna, ni(T) and ni(T+1) denote AWGN noise at the ith receive antenna at the duration T and T+1.

After simply exchanging in (3) and (4), we can get following equations:

h_i1*r_i(T). h_i2*r_i(T+1)=(| h_i1|²+| h_i2|²)s(T)+ h_i1*n_i(T)+ h_i2*n_i(T+1) (3.5)

h_i2*r_i(T). h_i1*r_i(T+1)=(| h_i1|²+| h_i1|²)s(T+1)+ h_i2*n_i(T)+ h_i1*n_i(T+1) (3.6)

Here, we can see the advantage of the STBC technique is that we can get transmitted signals without any inter-symbol interference with a simple process at transmitter side and receive side. The signal to noise at the ith receive antenna is given by:

γ_i= (| h_i1|²+| h_i2|²)P_s/P_n(3.7)

The summation of signal to noise ratio of NR receive antennas in the system is thus given by:

(3.8)

MIMO-OFDM STBC block diagram

A block diagram of MIMO-OFDM STBC systems is shown in above figure. At the transmit side, a high-speed input data stream is divided into many sub-streams according to the number of subcarriers of the systems. On each subcarrier, input data will be encoded by STBC encoder, then data on each transmit antenna will be processed by IFFT before transmitting. At the receive side, received signals will be done by an FFT process and applied STBC decoder on each subcarrier. The decoded data will be multiplexed to obtain transmitted data. MIMO OFDM STBC is divided into two,

Transmitter Side

Receiver Side

Block diagram of 2x2 MIMO-OFDM STBC hardware system

Simulation Video Demo

An Efficient Architecture for 3-D Discrete Wavelet Transform

2017-03-31T10:45:00.003+05:30

An Efficient Architecture for 3-D Discrete Wavelet Transform

Abstract-This project presents an architecture of the lifting based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-D DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput. The proposed architecture has been designed using Verilog HDL with Matlab and Simulated using Modelsim/Matlab Softwares.The input videos are converted as frames using Matlab and corresponding pixel values are stored.3D-DWT architectures is developed using Verilog HDL and even number of frame are taken as input to DWT.

Fig. Spatio-temporal wavelet decomposition with proposed architecture. (a) Original frame sequence. (b) After 1 level spatial transform. (c) Lowpass frames after the temporal transform. (d) Highpass frames after the temporal transform.

Simulation Video Demo

A Low Power 16 Bit Vedic Divider for High Speed VLSI Applications

2017-03-29T10:43:00.004+05:30

Abstract.

This project proposes the implementation of a low power and high speed Vedic Divider based on ancient Indian Vedic mathematics. In this project, an algorithm based on the “ParavartyaYojayet” is applied, throughout this sutra the propagation delay and power consumption are reduced to an extent. As considered, division operation is more complex in the computation of the digital applications. The most significant aspect of this paper is to reduce the power consumption and provide high speed. In this work decimal and binary number division algorithms are performed with filtering application to show the performance improvement of Paravartya Sutra over normal divider .The project is developed using Verilog HDL with MatLab and simulation is performed using Modelsim/MatLab Software. Synthesis results are calculated using Xilinx ISE. The simulated results for proposed Vedic divider shows a reduction in delay and power consumption against other division methods.

Division algorithm for decimal numbers is implemented based on “Paravartya-Yojayet – Transpose and Apply” see in table 1. Decimal division provides easier and logically simple implementation as illustrated using an example Paravartya Yojayet (Transpose and Apply).

Table:1 Vedic Division using 'PY'Sutra

Simulation Video Demo

High Performance VLSI Architecture for 3-D Discrete Wavelet Transform

2017-03-28T10:59:00.002+05:30

High Performance VLSI Architecture for 3-D Discrete Wavelet Transform-Verilog HDL with Matlab

Abstract-This project presents a high-speed memory efficient VLSI architecture for three dimensional (3-D) discrete wavelet transform. A major strength of the proposed architecture lies in reducing the number and period of clock cycles for the computation of wavelet transform. This five stage pipelined architecture shares the partial load of the next stage with the present stage to reduce computational load at the next stage and critical path delay (CPD). The proposed architecture has replaced the multiplications by optimized shift and add operations to reduce the CPD. Implementation results show that the proposed architecture benefits from the features of reduced memory, low power consumption, low latency, and high throughput over several existing designs.

Block diagram for 3-D discrete wavelet transform

The project is design using Verilog HDL with Matlab, where the input videos are converted into frames. Frame values are stored in memory using Matlab Program. DWT architecture design is developed using Verilog HDL.

Simulation Video Demo

VLSI IEEE PROJECTS 2017

2017-03-10T15:42:00.000+05:30

VLSI PROJECT TOPICS

2003

DCT-Based Image Watermarking Using Subsampling- Verilog with Matlab
VLSI Implementation of Invisible Digital Watermarking Algorithms- Verilog with Matlab

2004

An FPGA-based Architecture for Real Time Image Feature Extraction- Verilog with Matlab
Contrast Enhancement of Color Images using Tunable Sigmoid Function- Verilog with Matlab
Robust DWT-SVD Domain Image Watermarking Embedding Data in All Frequencies
Shift Invert Coding (SINV) for Low Power VLSI
VLSI Implementation of Discrete Wavelet Transform (DWT) and IDWT for Image Compression- Verilog with Matlab

2005

A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)- Verilog with Matlab
Digital Design of DS-CDMA Transmitter Using Verilog HDL and FPGA
Visual Attention Driven Image to Video Adaptation- Verilog with Matlab

2006

A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
A Verilog Implementation of UART Design with BIST Capability
An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing
Image Compression with Different Types of Wavelets- Verilog with Matlab

2007

A Low-Power Multiplier With the Spurious Power Suppression Technique
A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier
Design and Implementation of a low complexity real lossless Image compression method for wireless endoscopy capture system- Verilog with Matlab
Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation
Low-power and high-quality Cordic-based Loefﬂer DCT for signal processing
Low-Power Built-In Logic Block Observer Realization for BIST Applications-VHDL
Video Adaptation for Small Display Based on Content Recomposition- Verilog with Matlab
VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application

2008

A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
FPGA Based Design of a Novel Enhanced Error Detection And Correction Technique
FPGA Implementation of USB Transceiver Macrocell Interface with USB2.0 Specifications
FPGA Implementation of a Scalable Encryption Algorithm
Fuzzy based PID Controller using Verilog HDL for Transportation Application
Implementation of 64 Point FFT using Vedic Multiplier
Implementation of IEEE 802.11 a WLAN Baseband Processor
Multiplier design based on ancient Indian vedic muliplier
Research on Fast Super-resolution Image Reconstruction Base on Image Sequence-Verilog with Matlab
VLSI Implementation of an Edge-Oriented Image Scaling Processor- Verilog with Matlab

2009

3D Discrete Wavelet Transform VLSI Architecture for Image Processing- Verilog with Matlab
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM- Convolutional Encoders
Biometric Encryption using Fingerprint Fuzzy Vault for FPGA-based Embedded Systems- Verilog with Matlab
CSI Multimedia Architecture
Fast Scaling in the Residue Number System
Design and Implementation of Boundary-Scan Circuit
FPGA Based Power Efficient Channelizer For Software Defined Radio
FPGA-Based Face Detection System Using Haar Classifiers- Verilog with Matlab
Hardware Algorithm for Variable Precision Multiplication on FPGA
Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL- Verilog with Matlab
VLSI Implementations of the Cryptographic Hash Functions MD6

2010

FPGA Implementations of the Hummingbird Cryptographic Algorithm
A High-speed 32-bit Signed Unsigned Pipelined Multiplier
Software-Defined Radio for OFDM Transceivers
VLSI Implementation of Fully Pipelined Multiplier less 2D DCT IDCT Architecture for JPEG- Verilog with Matlab
Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip
High Speed and Low Space Complexity FPGA Based ECC
FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms- Verilog with Matlab
FPGA Implementation of Modular Multiplication methods using Cellular Automata
FPGA Implementation of High Performance LDPC Decoder using Modified 2-bit
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder
Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
Coherent Amplitude Modulated QAM-QPSK
A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform- Verilog with Matlab
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modiﬁed Booth Algorithm
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264AVC- Verilog with Matlab
A High Performance Binary to BCD Converter for Decimal Multiplication
An Efficient Architecture for 3 D Discrete Wavelet Transform-Verilog HDL with Matlab

2011

A New Reversible Design of BCD Adder
A Multichannel Watermarking DCT-DWT- Verilog with Matlab
An Efficient Implementation of Floating Point Multiplier
An implementation of a 2D FIR filter using the signed-digit number system- Verilog with Matlab
Automatic Road Extraction using High Resolution Satellite Images based on Mean Shift Method- Verilog with Matlab
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
Design and FPGA Implementation of CORDIC-based 8-point 1D DCT Processor
Design and Implementation of APB Bridge based on AMBA 4.0
Design and VLSI implementation of high-performance face-detection engine for mobile applications- Verilog with Matlab
Design Enhancement of Combinational Neural Networks Using HDL based FPGA Framework for Pattern Recognition- Verilog with Matlab
Efficient VLSI Architecture for Discrete Wavelet Transform- Verilog with Matlab
FPGA based FFT Algorithm Implementation in WiMAX Communications System
FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise Two Approaches- Verilog with Matlab
High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
Image Encryption Based On AES Key Expansion- Verilog with Matlab
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA- Verilog with Matlab
PCFICH Channel Design for LTE using FPGA- Verilog with Matlab
Pipelined Architecture for FPGA Implementation of Lifting-Based DWT- Verilog with Matlab

2012

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform- Verilog with Matlab
A Region Merging Approach for Image Segmentation on FPGA- Verilog with Matlab
An Efficient Viterbi Decoder
Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits
Design of Low Power TPG Using LP-LFSR
FPGA Based Real Time Face Detection using Adaboost and Histogram Equalization- Verilog with Matlab
HDL Design for Image Segmentation using Gabor filter for Disease Detection- Verilog with Matlab
High Speed and Area Efficient Vedic Multiplier
High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers
Improved Architectures for a Fused Floating-Point Add-Subtract Unit
Low-Power and Area-Efficient Carry Select Adder
Low-Power Variation-Aware Flip Flop
Modified Architecture for Real-Time Face Detection using FPGA- VHDL with Matlab
Very Low Resolution Face Recognition Problem- Verilog with Matlab
Viterbi-Based Efficient Test Data Compression
VLSI Architecture of Arithmetic Coder Used in SPIHT- Verilog with Matlab
FPGA Implementation of MIMO-OFDM STBC Systems-Verilog with Matlab

2013

Cordic for Fixed Angle Rotation
Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA
Design Of High Speed Floating Point Mac Using Vedic Multiplier And Parallel Prefix Adder
Design of High Speed Low Power Multiplier using Reversible logic-a Vedic Mathematical Approach
Design of High-speed low power Reversible Logic BCD Adder Using HNG gate
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic Techniques for Compensating Memory Errors in JPEG2000- Verilog with Matlab
Visible and Infrared Image Fusion using the Lifting Wavelets- VHDL with Matlab
VLSI Implementation of an Adaptive Edge -Enhanced Image Scalar for RealTime Multimedia Applications- Verilog with Matlab
VLSI Implementation of an Adaptive Edge-Enhanced Color Interpolation Processor for Real-Time Video Applications- Verilog with Matlab
Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform Neural Network Architecture- Verilog with Matlab
A High-Performance Energy-Efficient Architecture for FIR Adaptive Filter Based on New Distributed Arithmetic Formulation of Block LMS Algorithm-Verilog with Matlab
Design and simulation of Gabor filter using Verilog HDL-Verilog HDL with Matlab

2014

A Distributed Canny Edge Detector Algorithm and FPGA Implementation- Verilog with Matlab
A New Secure Image Transmission Technique via Secret-Fragment-Visible Mosaic Images- Verilog with Matlab
Design and Implementation of Orthogonal Code Convolution Using Enhanced Error Control Technique
FPGA Implementation of the C-Mantec Neural Network Constructive Algorithm
High Speed Convolution and Deconvolution Algorithm (Based on Ancient Indian Vedic Mathematics)
SW-HW Implementation of Image Covariance Descriptor For Person Detection Systems
VLSI Based Image Zooming Application by a Novel Adaptive Edge Enhancement Technique- Verilog with Matlab
Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform-Verilog with Matlab
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay-Verilog with Matlab
ASIC Implementation of Two Stage Pipelined Multiplier
Hardware Software Co-Simulation of Edge Detection for Image Processing System-Verilog with Matlab
Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform-Verilog with Matlab
An Embedded System-on-Chip Architecture for Real-time Visual Detection and Matching-Verilog HDL with Matlab

2015

Reviewing High-Radix Signed-Digit Adders
A New-High Speed-Low Power-Carry Select adder Using Modified GDI
Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications
A Modified Partial Product Generator for Redundant Binary Multipliers
A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT
Design and Analysis of Approximate Compressors for Multiplication
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

2016

A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
A Low Power 16 Bit Vedic Divider for High Speed VLSI Applications- Verilog HDL
High Performance VLSI Architecture for 3-D Discrete Wavelet Transfor-Verilog HDL with Matlab
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m)on FPGA
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
On Efficient Retiming of Fixed-Point Circuits
Hybrid LUT/Multiplexer FPGA Logic Architectures
Concept, Design, and Implementation of Reconfigurable CORDIC
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes

The above listed topics are just for reference. If you have any new Ideas/Papers send to us at info@verilogcourseteam.com or Call +91 98942 20795

SIMULATION MODEL OF VISIBLE WATERMARKING FOR JPEG IMAGE (3 D) USING VLSI/MATLAB

2009-11-13T15:33:00.002+05:30

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This project presents a new very large scale integration (VLSI) architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework.

Two fundamental operations performed by a digital camera are image capturing and storing. The images are subsequently transmitted in various forms over appropriate media. These images are always vulnerable to various forms of copyright attacks and ownership issues. The watermarking object may be an image, audio, video, or text .Whether the host data is in spatial domain, discrete cosine-transformed, or wavelet-transformed, watermarks of varying degree of visibility are added to present media as a guarantee of authenticity, ownership, source, and copyright protection.

According to human perception, the digital watermarks can be divided into four categories:

1) visible;

2) invisible-robust;

3) invisible-fragile;

4) dual

A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a casual viewer on careful inspection. The invisible-robust watermark is embedded in such a way that modifications made to the pixel value is perceptually not noticed, and it can be recovered only with appropriate decoding mechanism. The invisible-fragile watermark is embedded in such a way that any manipulation or modification of the image would alter or destroy the watermark. A dual watermark is a combination of a visible and an invisible watermark . In this type of watermark, an invisible watermark is used as a back-up for the visible watermark. There are numerous software-based watermarking schemes available in literature. A vast research community involving experts from computer science, cryptography, signal processing, and communications, etc., are working together to develop watermarks that can withstand different possible forms of attacks, each one of which has its own applications and thus is equally important. There is a gap between the image capture and image transmission in thewaywatermarking is used presently. Once the images are acquired,watermarks are inserted in them offline, and then images are made available. The objective of this research work is to implement hardware-based watermarking schemes so as to bridge that gap. The watermark chip will be fitted in the devices that acquire the image and watermark the images in real time while capturing.

VIDEO DEMO

SIMULATION OF HARDWARE BASED EDGE DETECTION

2009-11-13T15:09:00.000+05:30

INTRODUCTION:

Edge detection is a fundamental tool used in most image processing applications to obtain information from the frames before feature extraction and object segmentation. This process detects outlines of an object and boundaries between objects and the background in the image. Beyond that, Edge Detection refers to the process of identifying and locating sharp discontinuities in intensities in an image. The discontinuities are abrupt changes in pixels intensity which characterize boundaries of objects in a scene structure. This process significantly reduces the amount of date in the image, while preserving the most important structural feature of that image. Edge detection is considered to be the ideal algorithm for images that are corrupted with white noise. The Edge is characterized by its height, slope angle,and horizontal coordinate of the slope midpoint. An ideal Edge Detector should produce an edge indication localized to a single pixel located at the midpoint of the slope.There are many ways to perform Edge detection. However, the majority of different methods may be grouped into two categories, gradient and Laplacian. The basic Edge detection operator is a matrix area gradient operation that determines the level of variance between different pixels. The edge detection operator is calculated by forming a matrix centered on a pixel chosen as the centre of the matrix area. If the value of the matrix area is above a given threshold, then the middle pixel is classified as an edge. Examples of gradient based edge detectors are Roberts, Prewitt and Sobel operators. All the gradient –based algorithms have Kernel operators that calculate the strength of the slope in directions that are orthogonal to each other, generally horizontal and vertical.
The requirements that the algorithms must meet are:
a) Show the effectiveness and the noise resistance for remote sensing image.
b) Satisfying real time-constraints, and minimizing hardware resources in order to meet embedding requirements.
c) Significantly reducing the amount of date and filters out useless information.

Classically, Edge detection algorithms are implemented on software. With advances in the VLSI technology hardware implementation has become an attractive alternative. Assigning complex computation tasks to hardware and exploiting the parallelism and pipelining in algorithm yield significant speedup in running times. Implementation image processing on reconfigurable hardware minimizes the time-to-market cost, enables rapid prototyping of complex algorithm and simplifies debugging and verification.

VIDEO DEMO

Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

2009-11-13T15:00:00.000+05:30

INTRODUCTION

The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data rate requirements of 802.11a standard. Although software based solutions are more attractive due to the lower cost, shorter development time, and higher flexibility, it is still a challenge to meet the high-data-rate requirements of 802.11a by software. In this project, we simulate (Modelsim/Matlab) a software-based 802.11a digital baseband transmitter using Verilog HDL /Matlab. The transmitter can operate over all data rates defined in the 802.11a standard and are compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been used in the software implementation to achieve the high-data-rate:

1) parallelizing the scrambler function and

2) concatenating the FEC encoder, puncturing, and inter leaver functions.

Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard, they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements.

802.11A DIGITAL BASEBAND TRANSMITTER

The OFDM modulation scheme used in 802.11a distributes the data over 52 subcarriers on a 20MHz channel to mitigate the effects of multipath. Among the 52 subcarriers, 48 are for data and 4 are for pilot signals used for tracking. Each subcarrier is 312.5kHz wide, giving raw data rates from 125kbits/s to 1.125Mbits/s per subcarrier depending on the modulation type – binary phase shift keying (BPSK), quaternary PSK (QPSK), 16-quadrature amplitude modulation (QAM), or 64-QAM – and the error-correcting code rate (1/2, 2/3, or 3/4). The composite signal therefore has a data rate ranging from 6Mbits/s to 54Mbits/s in the 20MHz channel.

Table 1 lists the mode-dependent parameters for the 802.11a standard.

The block diagram of a digital baseband transmitter defined in 802.11a standard is shown in Fig. 1, which produces one OFDM symbol at a time based on the parameters in Table 1. The input bit stream is first randomized by a scrambler and encoded by a convolution encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time domain signals. Finally the resulting time domain signals are cyclically extended to form the guard interval for each OFDM symbol.

A FULLY PIPELINED ARCHITECTURE FOR THE LOCO-I COMPRESSION ALGORITHM

2009-11-13T14:53:00.002+05:30

INTRODUCTION

One of the most challenging test stands for wearable computer and remote sensor systems is the transmission of images. In fact, the amount of memory needed for the storage of color video images and the high speed required for their transmissions make the performance/ cost tradeoff difficult to attain. As a consequence, compression techniques are mandatory to sensibly reduce the amount of data needed for frame transmission. As far as static images are concerned,1 the best performance and compression rates are obtained by lossy algorithms, such as JPEG or JPEG2000. However, specific applications may prefer low-complex lossless schemes, especially if the quality of the transmitted image is a mandatory constraint. Among all others, Lossless JPEG , FELICS, and CALIC are few examples of lossless compression algorithms, but the coding scheme that features the best complexity/compression rate tradeoff is LOCO-I (low complexity lossless compression for images), the core of the JPEG-LS standard.

In this project, we present an efficient implementation of the LOCO-I algorithm tailored for field-programmable gate-array (FPGA) applications. The design takes fully advantage of the sequential nature of the LOCO-I compression scheme and results into a pipelined architecture for both encoder and decoder circuits. Consequently, significant performance improvements can be obtained with respect to previous nonpipelined designs without modifying the original compression scheme.

VLSI IMPLEMENTATION OF AN EDGE-ORIENTED IMAGE SCALING PROCESSOR

2009-11-13T14:50:00.002+05:30

INTRODUCTION

IMAGE scaling is widely used in many fields, ranging from consumer electronics to medical imaging. It is indispensable when the resolution of an image generated by a source device is different from the screen resolution of a target display. For example, we have to enlarge images to fit HDTV or to scale them down to fit the mini-size portable LCD panel. The most simple and widely used scaling methods are the nearest neighbor and bilinear techniques. In recent years, many efficient scaling methods have been proposed in the literature.

According to the required computations and memory space, we can divide the existing scaling methods into two classes: lower complexity and higher complexity scaling techniques. The complexity of the former is very low and comparable to conventional bilinear method. The latter yields visually pleasing images by utilizing more advanced scaling methods. In many practical real-time applications, the scaling process is included in end-user equipment, so a good lower complexity scaling technique, which is simple and suitable for low-cost VLSI implementation, is needed. In this project, we consider the lower complexity scaling techniques only. Kim presented a simple area-pixel scaling method. It uses an area-pixel model instead of the common point-pixel model and takes a maximum of four pixels of the original image to calculate one pixel of a scaled image. By using the area coverage of the source pixels from the applied mask in combination with the difference of luminosity among the source pixels, Andreadis proposed a modified area-pixel scaling algorithm and its circuit to obtain better edge preservation. Both obtain better edge-preservation but require about two times more of computations than the bilinear method. To achieve the goal of lower cost, we present an edge-oriented area-pixel scaling processor in this paper. The area-pixel scaling technique is approximated and implemented with the proper and low-cost VLSI circuit in our design. The proposed scaling processor can support floating-point magnification factor and preserve the edge features efficiently by taking into account the local characteristic existed in those available source pixels around the target pixel. Furthermore, it handles streaming data directly and requires only small amount of memory: one line buffer rather than a full frame buffer. The experimental results demonstrate that the proposed design performs better than other lower complexity image scaling methods in terms of both quantitative evaluation and visual quality.

DIGITAL DESIGN OF DS-CDMA TRANSMITTER USING VERILOG AND FPGA

2009-11-13T14:47:00.002+05:30

INTRODUCTION

In recent years, there has been a significant amount of research performed in both industry and academia into the development of CDMA systems. A clear description of a CDMA has been elusive, since it has a different meaning to every researcher involved in the topic. DS-CDMA is a type of spread-spectrum communication system in which multiple signal channels occupy the same frequency band, being distinguished by the use of different spreading codes CDMA communication is employed in, for example, digital cellular telephone systems and personal communication services. In these systems, a base station communicates with a plurality of mobile stations, one frequency band being used for all of the up-links from the mobile stations to the base station, and another frequency band being used for all of the down-links from the base station to the mobile stations.

This project describes the design and a circuit for pseudo random PN coding and synchronization of a wireless transmitter for DS-CDMA using Verilog HDL. The circuit for the transmitter is comprised of basic digital components, such as flip-flops, oscillators, shift registers, PN coder and a BPSK modulator. XILINX/ALTEAR FPGA to implement this circuit.

VLSI IMPLEMENTATIONS OF THE CRYPTOGRAPHIC HASH FUNCTIONS MD6 AND ïrRUPT

2009-11-13T14:43:00.002+05:30

INTRODUCTION

Cryptographic hash functions are ubiquitous algorithm used in numerous schemes like digital signatures, public-key encryption, or MAC's. Hash functions process an arbitrary-length message to produce a small fixed-length digital fingerprint, and should satisfy a variety of security properties (preimage resistance, collision resistance, pseudorandomness, etc.). In the last years, a wide range of attacks have been applied to the previous standards MD5 and SHA-1, to break their collision resistance . Although only collisions in reduced versions of the current standard SHA-2 are known , researchers are skeptical about its long-term security. As a response, the U.S. National Institute of Standards and Technologies (NIST) recently launched a call for candidate functions for a new cryptographic hash algorithm (SHA-3) family . The hash functions MD6 (by the author of MD5) and ïrRUPT have been accepted as Round 1 candidates. Besides a high security, the new hash standard should be suitable for implementations on a wide range of applications. In particular, hardware efficiency will be crucial to determine the future SHA-3, because hardware resources are often limited, whereas on high-end PC's it does not matter much in general; indeed, even the slowest hash function has acceptable performance on a PC. Furthermore, hash function designers seldom study the hardware performance. It is thus necessary to independently study implementations of future candidates on ASIC and FPGA, and determine their suitability for resource limited environments.

This project presents a hardware architectures for the hash functions MD6 and ïrRUPT. Particular attention has been drawn in the analysis of the round process to exploit parallelism, to maximize the circuit speed.

AN EFFICIENT DIGITAL VLSI IMPLEMENTATION OF GAUSSIAN MIXTURE MODELS-BASED CLASSIFIER

2009-11-13T14:40:00.002+05:30

INTRODUCTION

THE GAUSSIAN mixture models (GMM) classifier has gained increasing attention in the pattern recognition community. GMM can be classified as a semi-parametric density estimation method since it defines a very general class of functional forms for the density model. In this mixture model, a probability density function is expressed as a linear combination of basis functions. Improved classification performances have been demonstrated in many pattern recognition applications . Performance figures of more than 95% have already been reported for applications such as electronic nose and gas identification. Another interesting property of GMM is that the training procedure is done independently for each class in turn by constructing a Gaussian mixture of a given class. Adding a new class to a classification problem does not require retraining the whole system and does not affect the topology of the classifier making it attractive for pattern recognition applications. While GMM provides very good performances and interesting properties as a classifier, it presents some problems that may limit its practical use in real-time applications. One problem is that GMM can require large amounts of memory to store various coefficients and can require complex computations mainly involving exponential calculations. Thus, this scheme can be put to efficient practical use only if good hardware implementation strategies are developed.

In this project, we propose an efficient digital VLSI implementation that we believe can meet the computational requirement of GMM-based classifiers. First, after analyzing the complexity of the GMM classifier it was found that the vector-matrix multiplication and the exponential calculations are the most critical operations in the classifier. A good tradeoff between real-time processing and hardware resources requirements is obtained using a serial-parallel architecture and an efficient pipelining strategy. Second, a linear piecewise function (LPF) is proposed to replace the exponential calculation. Implementing LPF-based GMM, also permits to avoid the need for using area consuming look-up table (generally used in digital implementation) to implement the exponential function. The effect of both limited precision and the mixture models approximation using LPF on the classification performance is investigated using seven different data-sets. These data-sets are also used to compare the performance of GMM with other benchmark classifiers.

AN OPTIMUM ORA BIST FOR MULTIPLE FAULT FPGA LOOK-UP TABLE TESTING

2009-11-13T14:37:00.002+05:30

Introduction

Field Programmable Gate Arrays (FPGAs) have been widely used for rapid prototyping and manufacturing of complex digital systems, such as microprocessors and high speed telecommunication chips. FPGAs are suitable for prototypes of systems whose correct operation is necessary for the evaluation of new architectures. This requires changing the architecture during the design cycle with many reconfigurations of the same FPGA. The frequent reconfiguration of an FPGA makes it more fault-prone.There are many components of an FPGA to test for ensuring reliable usage of this device.

In this projecy, we only consider test of LEs and focus on LUTs within LEs. There are different methods for LE testing. One may use I/O pins for applying test vectors to LEs and collecting test results. But, usage of I/O pins for test decreases the number of I/O pins available for normal operation. If detailed information for JTAG implementation was available, usage of JTAG pins as an interface to apply test vectors and retrieve LEs' results would be suitable . A Built-In-Self-Test (BIST) architecture has been proposed for LEs testing, which eliminates the usage of I/O and JTAG pins. In this paper we address this approach for LUT testing of LEs. Our objective is to propose a BIST architecture with a good balance between various costs. Test time, test area and granularity are such trade-offs.

A SYMBOL-RATE TIMING SYNCHRONIZATION METHOD FOR LOW POWER WIRELESS OFDM SYSTEMS

2009-11-13T14:33:00.002+05:30

INTRODUCTION

TRADEOFF between system performance and power dissipation is one of the most critical issues in the design of a wireless portable device. Timing synchronization plays an important role in ensuring good signal decoding performance, since it determines the sampling timing and frequency of the analog-to-digital converter (ADC) on incoming signals or packets. Existing design approaches apply multirate sampling the incoming waveform with a fixed high-rate clock source that drives an ADC circuit. Those high-rate sampled signals are then calculated by an interpolation algorithm to yield a symbol-rate signal stream for data decoding. This design methodology to designing power-thirsty portable devices is facing increasing difficulty, because both the ADC circuits and the interpolation circuits are operated at a higher processing rate, resulting in higher power consumption.

To enable power reduction with symbol-rate sampling, both Mueller–Muller detection (MMD) and MMD-based timing recovery methods have been proposed under a pulse amplitude modulation (PAM) scheme for best sampling timing search within a sample period. The literature explores the timing synchronization issue in orthogonal frequency-division multiplexing (OFDM) systems based on the best block-boundary search for each fast Fourier transform (FFT) window.

Accordingly, multirate sampling,schemes have been developed to maintain system performance; hence the high-rate operations significantly increase power dissipation. To maintain system performance and, in the meantime, to reduce power dissipation, this work presents a dynamic sampletiming control (DSTC) scheme for symbol-rate synchronization in OFDM systems, where the optimal sampling timing within a symbol-period interval can be calculated. Unlike multirate sampling methods, this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC for low-power wireless applications.

IMPROVEMENT OF THE ORTHOGONAL CODE CONVOLUTION CAPABILITIES USING FPGA IMPLEMENTATION

2009-11-13T14:26:00.002+05:30

INTRODUCTION

When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability of these data. Error detection and correction techniques are therefore required. Some of those techniques can only detect errors, such as the Cyclic Redundancy Check , others are designed to detect as well as correct errors, such as Salomon Codes. However, the existing techniques are not able to achieve high efficiency and to meet bandwidth requirements, especially with the increase in the quantity of data transmitted.

Orthogonal Code is one of the codes that can detect errors and correct corrupted data. Our objective in this paper is to enhance the error control capabilities of orthogonal codes by means of Field Programmable Gate Array (FPGA) implementation.

ORTHOGONAL CODES
Orthogonal codes are binary valued and they have equal number of 1’s and 0’s. An n-bit orthogonal code has n/2 1’s and n/2 0’s; i.e., there are n/2 positions where 1’s and 0’s differ . Therefore, all orthogonal codes will generate zero parity bits. The concept is illustrated by means of an 8- bit orthogonal code as shown in Fig.1. It has 8-orthogonal codes and 8-antipodal codes for a total of 16-biorthogonal codes. Antipodal codes are just the inverse of orthogonal codes; they are also orthogonal among themselves.

FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM

2009-11-13T13:44:00.001+05:30

INTRODUCTION

Scalable encryption algorithm (SEA) is a parametric block cipher for resource constrained systems (e.g., sensor networks, RFIDs) that has been introduced . It was initially designed as a low-cost encryption/ authentication routine (i.e., with small code size and memory) targeted for processors with a limited instruction set (i.e., AND, OR, XOR gates, word rotation, and modular addition). Additionally and contrary to most recent block ciphers (e.g., the DES and AES Rijndael , the algorithm takes the plaintext, key, and the bus sizes as parameters and, therefore, can be straightforwardly adapted to various implementation contexts and/or security requirements. Compared to older solutions for low-cost encryption like tiny encryption algorithm (TEA) or Yuval’s proposal , SEA also benefits from a stronger security analysis, derived from recent advances in block cipher design/cryptanalysis.

In practice, SEA has been proven to be an efficient solution for embedded software applications using microcontrollers, but its hardware performances have not yet been investigated. Consequently, and as a first step towards hardware performance analysis, this letter explores the features of a low-cost field-programmable gate array (FPGA) encryption/ decryption core for SEA. In addition to the performance evaluation, we show that the algorithm’s scalability can be turned into a fully generic VHDL/Verilog design, so that any text, key, and bus size can be straightforwardly reimplemented without any modification of the hardware description language, with standard synthesis and implementation tools.

TECHNICAL INFORMATION - ACADEMIC PROJECT

2009-08-05T16:21:00.011+05:30

Dear Students,

Now you can get Technical Information for your Academic Projects from

http://www.verilogcourseteam.com/academic-solutions

Students can also sent their Ideas with related documents/IEEE Papers to

info@verilogcourseteam.com

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IMPLEMENTATION OF RIJNDAEL S-BOX USING COMBINATIONAL LOGIC

2009-01-26T14:06:00.002+05:30

Introduction

This Project presents a combinational logic based Rijndael S-Box implementation for the SubByte transformation in the Advanced Encryption Standard (AES) algorithm for Field Programmable Gate Arrays (FPGAs). Recent publications on AES implementation have shown that the combinational logic based S-Box is proven for its small area occupancy and high throughput, given the fact that pipelining can be applied to this S-Box implementation as compared to the typical ROM based lookup table implementation which access time is fixed and unbreakable.

The Project deals with a brief introduction to the Advanced Encryption Standard, the SubByte and InvSubByte transformation, and finally a short discussion on the previous h ardware implementations of the SubByte/InvSubByte transformation.

The Advanced Encryption Standard

The AES algorithm has a fixed block size of 128 bits and a key length of 128, 192 or 256 bits. It generates its key from an input key using the Key Expansion function. The AES operates on a 4x4 array of bytes which is called a state. The state undergoes 4 transformations which are namely the AddRoundKey, SubByte, ShiftRow and MixColumn transformation.The AddRoundKey transformation involves a bitwise XOR operation between the state array and the resulting Round Key that is output from the Key Expansion function.

SubByte transformation is a highly non-linear byte substitution where each byte in the state array is replaced with another from a lookup table called an S-Box. ShiftRow transformation is done by cyclically shifting the rows in the array with different offsets. Finally, MixColumn transformation is a column mixing operation, where the bytes in the new column are a function of the 4 bytes of a column in the state array.Of all the transformation above, the SubByte transformation is the most computationally heavy.The SubByte and InvSubByte Transformation The SubByte transformation is computed by taking the multiplicative inverse in GF(28) followed by an affine transformation. For its reverse, the InvSubByte transformation, the inverse affine transformation is applied first prior to computing the multiplicative inverse.

The steps involved for both transformation is shown below.

SubByte: Multiplicative Inversion in GF(28) ->Affine Transformation

InvSubByte:Inverse Affine Transformation ->Multiplicative Inversion in GF(2*8)

A VHDL/VERILOG MODEL OF A IEEE1451.2 SMART SENSOR:CHARACTERIZATION AND APPLICATIONS

2009-01-19T21:55:00.003+05:30

INTRODUCTION

New sensors are required to be small, cheap, and smart. This project deals with intelligent sensors embedded in a single chip: a Verilog/VHDL model of an IEEE1451.2 Smart Sensor is proposed to obtain a portable STIM block suitable for customizable compact solutions and allowing low-cost, large-scale production. In order to evaluate performances of the proposed model, working prototypes have been built and some tests have been carried out in a real case (chemical detection sensors). The proposed Verilog/VHDL model has been compared with traditional, software-based, microcontroller solutions showing that a timing performance improvement greater than 50% can be obtained. Finally, to exemplify effectiveness of a portable VHDL model, a single-chip sensor with USB interface and integrated IEEE1451 structures has been realized and experimentally characterized.

In this projectaper, IEEE 1451 Standards are considered. Nowadays, some vendors supply smart sensors adherent to IEEE1451.2, the standard part that describes Smart Transducer Interface Module (STIM), Transducer Electronic DataSheet (TEDS), and Transducer Independent Interface (TII). Generally, these sensors have a microprocessor-centered architecture, where the CPU is devoted both to handle sensing element signal and to support IEEE1451.2 structure .However, it is said that few commercial products (e.g., Telemonitor TMI931A) are currently supporting IEEE1451.2 because of its relatively high cost; actually vendors prefer IEEE1451.4 , a simpler and cheaper standard solution. It is suitable for analog transducers (e.g., ENDEVCO i-TEDS accelerometers), since it defines only TEDS and requires a small number of additional components. In order to obtain a fast and more compact system, the systemon-chip (SoC) approach can be pursued; C (microcontroller), conditioning electronics, and even sensors can be integrated in one chip, reducing overall cost and simplifying assembly procedures .

A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE

2009-01-18T22:02:00.005+05:30

Introduction

This project describes a novel architecture of Universal Asynchronous Receiver Transmitter (UART) based on Recursive Running Sum (RRS) filter. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The robust UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one third of required bit period. The intermediate data bit is decoded using magnitude comparator. A majority voter is used to decode actual data bit from three intermediate data bits.

Universal Asynchronous Receiver Transmitter (UART) is used for asynchronous serial data communication between remote embedded systems. Standard UART cores three mid-bit samples to decode the serial data bit and the sampling rate is derived from external timer module. But if the physical channel is noisy then data bits get corrupted during transmission and it leads to wrong data decoding at receiver. To overcome the noise problem a digital low pass filter based architecture is proposed in this project.

Recursive Running Sum (RRS) is simple low pass filter, it can be used to remove noise samples from data samples at receiver .Serial receive data signal is directly sampled with system clock and samples are fed to RRS filter. The window size of the filter is user programmable and it decides baud rate. The robust UART core can be designed using Verilog HDL and can be implemented on Xilinx/ALTERA FPGA .

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