VLSI Projects

VLSI IEEE PROJECT TOPICS

2009-11-18T12:57:00.021+05:30

VLSI IEEE PROJECT TOPICS

DCT-Based Image Watermarking Using Subsampling-2003
Shift Invert Coding (SINV) for Low Power VLSI-2004
Robust DWT-SVD Domain Image Watermarking: Embedding Data in All Frequencies-2004
Digital Design of DS-CDMA Transmitter Using VHDL and FPGA-2005
Design of Edge Detection Systems
A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design (Corrected)-2005
A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture-2006
An FPGA-based Architecture for Real Time Image Feature Extraction-2004
Image Compression with Different Types of Wavelets-2006

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2007 Topics

A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth MultiplierLow-power and high-quality Cordic-based Loeffler DCT for signal processing
Implementation of a Multi-channel UART Controller Based on FIFO Technique and FPGA
A Low-Power Multiplier With the Spurious Power Suppression Technique
FPGA Implementation(s) of a Scalable Encryption Algorithm

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2008 Topics

Fuzzy based PID Controller using VHDL for Transportation Application Research on Fast Super-resolution Image Reconstruction Base on Image Sequence
A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance
FPGA Implementation Of Usb Transceiver Macrocell Interface With USB2.0 Specifications
Multiplier design based on ancient Indian Vedic Mathematics
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
Design Exploration of a Spurious Power Suppression Technique (SPST) and Its Applications
Implementation of IEEE 802.11 a WLAN Baseband Processor

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2009 Topics

The CSI Multimedia Architecture
Design and Implementation of Boundary-Scan Circuit for FPGA
Hardware Algorithm for Variable Precision Multiplication on FPGA
VLSI Implementations of the Cryptographic Hash Functions MD6 and ïrRUPT
VLSI Implementation of an Edge-Oriented Image Scaling Processor
FPGA-Based Face Detection System Using Haar Classifiers
An Effective Fast and Small-Area Parallel-Pipeline Architecture for OTM-Convolutional Encoders
Fast Scaling in the Residue Number System
VLSI Architecture and Chip for Combined Invisible Robust Watermarking
Implementing Gabor Filter for Fingerprint Recognition Using Verilog HDL
An Area-Efficient Universal Cryptography Processor for Smart Cards
FPGA Based Power Efficient Channelizer for Software Defined Radio
Improvement of the Orthogonal Code Convolution Capabilities Using FPGA Implementation

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2010 Topics

Design of Low-Cost High-performance Floating-point Fused Multiply-Add with Reduced Power
Image Edge Detection Based on FPGA
A High-speed 32-bit Signed/Unsigned Pipelined Multiplier
A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm
FPGA Implementations of the Hummingbird Cryptographic Algorithm
FPGA Implementation(s) of a Scalable Encryption Algorithm
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
Contrast Enhancement of Color Images using Tunable Sigmoid Function
Image Compression with Different Types of Wavelets
Performance Efficient FPGA Implementation of Parallel 2-D MRI Image Filtering Algorithms using Xilinx System Generator
Design and FPGA Implementation of Modular Multiplication methods using Cellular Automata
Product Reed-Solomon Codes for Implementing NAND Flash Controller on FPGA chip
A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
VLSI Implementation of Fully Pipelined Multiplierless 2D DCT/IDCT Architecture for JPEG
VLSI Implementation of Autocorrelator and CORDIC algorithm for OFDM based WLAN
Improvisation of Gabor Filter design using Verilog HDL

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2011 Topics

An Efficient Implementation of Floating Point Multiplier
A Distributed Canny Edge Detector And Its Implementation on FPGA
A blind digital watermarking algorithm based on wavelet transform
Design and Simulation of UART Serial Communication Module Based on VHDL
Design and VLSI implementation of high-performance face-detection engine for mobile applications
Design and Implementation of Area-optimized AES based on FPGA
Design of Low Power And High Speed Configurable Booth Multiplier
Digital watermarking using Bidimensional Empirical Mode Decomposition
Face detection and recognition method based on skin color and depth information
High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
A New Reversible Design of BCD Adder
Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA
A Very Fast and Low Power Carry Select Adder Circuit
Feature Extraction of Digital Aerial Images by FPGA based implementation of edge detection algorithms
An Efficient Architecture Design for VGA Monitor Controller
An Implementation of a 2D FIR Filter Using the Signed-Digit Number System
Design and Characterization of Parallel Prefix Adders using FPGAs
FPGA based FFT Algorithm Implementation in WiMAX Communications System
FPGA Design of AES Core Architecture for Portable Hard Disk
FPGA Implementation of RS232 to Universal serial bus converter
Image Encryption Based On AES Key Expansion
Curve Fitting Algorithm FPGA implementation
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
Design of Low Power Column Bypass Multiplier using FPGA
Design of Serial Communication Interface Based on FPGA
Design and Implementation of an FPGA-based Real-Time Face Recognition System
VHDL Design and FPGA Implementation of Weighted Majority Logic Decoders

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SIMULATION MODEL OF VISIBLE WATERMARKING FOR JPEG IMAGE (3 D) USING VLSI/MATLAB

2009-11-13T15:33:00.002+05:30

Watermarking is the process that embeds data called a watermark, a tag, or a label into a multimedia object, such as images, video, or text, for their copyright protection. According to human perception, the digital watermarks can either be visible or invisible. A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a viewer on a careful inspection. The invisible watermark is embedded in such a way that the modifications made to the pixel value is perceptually not noticed, and it can be recovered only with an appropriate decoding mechanism. This project presents a new very large scale integration (VLSI) architecture for implementing two visible digital image watermarking schemes. The proposed architecture is designed to aim at easy integration into any existing digital camera framework.

Two fundamental operations performed by a digital camera are image capturing and storing. The images are subsequently transmitted in various forms over appropriate media. These images are always vulnerable to various forms of copyright attacks and ownership issues. The watermarking object may be an image, audio, video, or text .Whether the host data is in spatial domain, discrete cosine-transformed, or wavelet-transformed, watermarks of varying degree of visibility are added to present media as a guarantee of authenticity, ownership, source, and copyright protection.

According to human perception, the digital watermarks can be divided into four categories:

1) visible;

2) invisible-robust;

3) invisible-fragile;

4) dual

A visible watermark is a secondary translucent image overlaid into the primary image and appears visible to a casual viewer on careful inspection. The invisible-robust watermark is embedded in such a way that modifications made to the pixel value is perceptually not noticed, and it can be recovered only with appropriate decoding mechanism. The invisible-fragile watermark is embedded in such a way that any manipulation or modification of the image would alter or destroy the watermark. A dual watermark is a combination of a visible and an invisible watermark . In this type of watermark, an invisible watermark is used as a back-up for the visible watermark. There are numerous software-based watermarking schemes available in literature. A vast research community involving experts from computer science, cryptography, signal processing, and communications, etc., are working together to develop watermarks that can withstand different possible forms of attacks, each one of which has its own applications and thus is equally important. There is a gap between the image capture and image transmission in thewaywatermarking is used presently. Once the images are acquired,watermarks are inserted in them offline, and then images are made available. The objective of this research work is to implement hardware-based watermarking schemes so as to bridge that gap. The watermark chip will be fitted in the devices that acquire the image and watermark the images in real time while capturing.

VIDEO DEMO

SIMULATION OF HARDWARE BASED EDGE DETECTION

2009-11-13T15:09:00.000+05:30

INTRODUCTION:

Edge detection is a fundamental tool used in most image processing applications to obtain information from the frames before feature extraction and object segmentation. This process detects outlines of an object and boundaries between objects and the background in the image. Beyond that, Edge Detection refers to the process of identifying and locating sharp discontinuities in intensities in an image. The discontinuities are abrupt changes in pixels intensity which characterize boundaries of objects in a scene structure. This process significantly reduces the amount of date in the image, while preserving the most important structural feature of that image. Edge detection is considered to be the ideal algorithm for images that are corrupted with white noise. The Edge is characterized by its height, slope angle,and horizontal coordinate of the slope midpoint. An ideal Edge Detector should produce an edge indication localized to a single pixel located at the midpoint of the slope.There are many ways to perform Edge detection. However, the majority of different methods may be grouped into two categories, gradient and Laplacian. The basic Edge detection operator is a matrix area gradient operation that determines the level of variance between different pixels. The edge detection operator is calculated by forming a matrix centered on a pixel chosen as the centre of the matrix area. If the value of the matrix area is above a given threshold, then the middle pixel is classified as an edge. Examples of gradient based edge detectors are Roberts, Prewitt and Sobel operators. All the gradient –based algorithms have Kernel operators that calculate the strength of the slope in directions that are orthogonal to each other, generally horizontal and vertical.
The requirements that the algorithms must meet are:
a) Show the effectiveness and the noise resistance for remote sensing image.
b) Satisfying real time-constraints, and minimizing hardware resources in order to meet embedding requirements.
c) Significantly reducing the amount of date and filters out useless information.

Classically, Edge detection algorithms are implemented on software. With advances in the VLSI technology hardware implementation has become an attractive alternative. Assigning complex computation tasks to hardware and exploiting the parallelism and pipelining in algorithm yield significant speedup in running times. Implementation image processing on reconfigurable hardware minimizes the time-to-market cost, enables rapid prototyping of complex algorithm and simplifies debugging and verification.

VIDEO DEMO

Optimized Software Implementation of a Full-Rate IEEE 802.11a Compliant Digital Baseband Transmitter on a Digital Signal Processor

2009-11-13T15:00:00.000+05:30

INTRODUCTION

The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high-speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data rate requirements of 802.11a standard. Although software based solutions are more attractive due to the lower cost, shorter development time, and higher flexibility, it is still a challenge to meet the high-data-rate requirements of 802.11a by software. In this project, we simulate (Modelsim/Matlab) a software-based 802.11a digital baseband transmitter using Verilog HDL /Matlab. The transmitter can operate over all data rates defined in the 802.11a standard and are compatible with the high-rate portions of the 802.11g standard. Two major optimizations have been used in the software implementation to achieve the high-data-rate:

1) parallelizing the scrambler function and

2) concatenating the FEC encoder, puncturing, and inter leaver functions.

Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems. Although DSPs have been used to implement the 802.11a standard, they can only support limited data rates due to the lack of global parallelism found at the application level. Hence, it is still a major challenge to develop a software implementation for the 802.11a standard on a DSP to meet the high-data-date requirements.

802.11A DIGITAL BASEBAND TRANSMITTER

The OFDM modulation scheme used in 802.11a distributes the data over 52 subcarriers on a 20MHz channel to mitigate the effects of multipath. Among the 52 subcarriers, 48 are for data and 4 are for pilot signals used for tracking. Each subcarrier is 312.5kHz wide, giving raw data rates from 125kbits/s to 1.125Mbits/s per subcarrier depending on the modulation type – binary phase shift keying (BPSK), quaternary PSK (QPSK), 16-quadrature amplitude modulation (QAM), or 64-QAM – and the error-correcting code rate (1/2, 2/3, or 3/4). The composite signal therefore has a data rate ranging from 6Mbits/s to 54Mbits/s in the 20MHz channel.

Table 1 lists the mode-dependent parameters for the 802.11a standard.

The block diagram of a digital baseband transmitter defined in 802.11a standard is shown in Fig. 1, which produces one OFDM symbol at a time based on the parameters in Table 1. The input bit stream is first randomized by a scrambler and encoded by a convolution encoder at a coding rate of 1/2. Puncturing is used to obtain code rates other than 1/2. The bit stream is then interleaved and mapped to complex numbers representing frequency domain signals of the OFDM subcarriers based on modulation rules. After the pilot signals are inserted, an Inverse Fast Fourier Transform (IFFT) is performed to convert frequency domain signals to time domain signals. Finally the resulting time domain signals are cyclically extended to form the guard interval for each OFDM symbol.

A FULLY PIPELINED ARCHITECTURE FOR THE LOCO-I COMPRESSION ALGORITHM

2009-11-13T14:53:00.002+05:30

INTRODUCTION

One of the most challenging test stands for wearable computer and remote sensor systems is the transmission of images. In fact, the amount of memory needed for the storage of color video images and the high speed required for their transmissions make the performance/ cost tradeoff difficult to attain. As a consequence, compression techniques are mandatory to sensibly reduce the amount of data needed for frame transmission. As far as static images are concerned,1 the best performance and compression rates are obtained by lossy algorithms, such as JPEG or JPEG2000. However, specific applications may prefer low-complex lossless schemes, especially if the quality of the transmitted image is a mandatory constraint. Among all others, Lossless JPEG , FELICS, and CALIC are few examples of lossless compression algorithms, but the coding scheme that features the best complexity/compression rate tradeoff is LOCO-I (low complexity lossless compression for images), the core of the JPEG-LS standard.

In this project, we present an efficient implementation of the LOCO-I algorithm tailored for field-programmable gate-array (FPGA) applications. The design takes fully advantage of the sequential nature of the LOCO-I compression scheme and results into a pipelined architecture for both encoder and decoder circuits. Consequently, significant performance improvements can be obtained with respect to previous nonpipelined designs without modifying the original compression scheme.

VLSI IMPLEMENTATION OF AN EDGE-ORIENTED IMAGE SCALING PROCESSOR

2009-11-13T14:50:00.002+05:30

INTRODUCTION

IMAGE scaling is widely used in many fields, ranging from consumer electronics to medical imaging. It is indispensable when the resolution of an image generated by a source device is different from the screen resolution of a target display. For example, we have to enlarge images to fit HDTV or to scale them down to fit the mini-size portable LCD panel. The most simple and widely used scaling methods are the nearest neighbor and bilinear techniques. In recent years, many efficient scaling methods have been proposed in the literature.

According to the required computations and memory space, we can divide the existing scaling methods into two classes: lower complexity and higher complexity scaling techniques. The complexity of the former is very low and comparable to conventional bilinear method. The latter yields visually pleasing images by utilizing more advanced scaling methods. In many practical real-time applications, the scaling process is included in end-user equipment, so a good lower complexity scaling technique, which is simple and suitable for low-cost VLSI implementation, is needed. In this project, we consider the lower complexity scaling techniques only. Kim presented a simple area-pixel scaling method. It uses an area-pixel model instead of the common point-pixel model and takes a maximum of four pixels of the original image to calculate one pixel of a scaled image. By using the area coverage of the source pixels from the applied mask in combination with the difference of luminosity among the source pixels, Andreadis proposed a modified area-pixel scaling algorithm and its circuit to obtain better edge preservation. Both obtain better edge-preservation but require about two times more of computations than the bilinear method. To achieve the goal of lower cost, we present an edge-oriented area-pixel scaling processor in this paper. The area-pixel scaling technique is approximated and implemented with the proper and low-cost VLSI circuit in our design. The proposed scaling processor can support floating-point magnification factor and preserve the edge features efficiently by taking into account the local characteristic existed in those available source pixels around the target pixel. Furthermore, it handles streaming data directly and requires only small amount of memory: one line buffer rather than a full frame buffer. The experimental results demonstrate that the proposed design performs better than other lower complexity image scaling methods in terms of both quantitative evaluation and visual quality.

DIGITAL DESIGN OF DS-CDMA TRANSMITTER USING VERILOG AND FPGA

2009-11-13T14:47:00.002+05:30

INTRODUCTION

In recent years, there has been a significant amount of research performed in both industry and academia into the development of CDMA systems. A clear description of a CDMA has been elusive, since it has a different meaning to every researcher involved in the topic. DS-CDMA is a type of spread-spectrum communication system in which multiple signal channels occupy the same frequency band, being distinguished by the use of different spreading codes CDMA communication is employed in, for example, digital cellular telephone systems and personal communication services. In these systems, a base station communicates with a plurality of mobile stations, one frequency band being used for all of the up-links from the mobile stations to the base station, and another frequency band being used for all of the down-links from the base station to the mobile stations.

This project describes the design and a circuit for pseudo random PN coding and synchronization of a wireless transmitter for DS-CDMA using Verilog HDL. The circuit for the transmitter is comprised of basic digital components, such as flip-flops, oscillators, shift registers, PN coder and a BPSK modulator. XILINX/ALTEAR FPGA to implement this circuit.

VLSI IMPLEMENTATIONS OF THE CRYPTOGRAPHIC HASH FUNCTIONS MD6 AND ïrRUPT

2009-11-13T14:43:00.002+05:30

INTRODUCTION

Cryptographic hash functions are ubiquitous algorithm used in numerous schemes like digital signatures, public-key encryption, or MAC's. Hash functions process an arbitrary-length message to produce a small fixed-length digital fingerprint, and should satisfy a variety of security properties (preimage resistance, collision resistance, pseudorandomness, etc.). In the last years, a wide range of attacks have been applied to the previous standards MD5 and SHA-1, to break their collision resistance . Although only collisions in reduced versions of the current standard SHA-2 are known , researchers are skeptical about its long-term security. As a response, the U.S. National Institute of Standards and Technologies (NIST) recently launched a call for candidate functions for a new cryptographic hash algorithm (SHA-3) family . The hash functions MD6 (by the author of MD5) and ïrRUPT have been accepted as Round 1 candidates. Besides a high security, the new hash standard should be suitable for implementations on a wide range of applications. In particular, hardware efficiency will be crucial to determine the future SHA-3, because hardware resources are often limited, whereas on high-end PC's it does not matter much in general; indeed, even the slowest hash function has acceptable performance on a PC. Furthermore, hash function designers seldom study the hardware performance. It is thus necessary to independently study implementations of future candidates on ASIC and FPGA, and determine their suitability for resource limited environments.

This project presents a hardware architectures for the hash functions MD6 and ïrRUPT. Particular attention has been drawn in the analysis of the round process to exploit parallelism, to maximize the circuit speed.

AN EFFICIENT DIGITAL VLSI IMPLEMENTATION OF GAUSSIAN MIXTURE MODELS-BASED CLASSIFIER

2009-11-13T14:40:00.002+05:30

INTRODUCTION

THE GAUSSIAN mixture models (GMM) classifier has gained increasing attention in the pattern recognition community. GMM can be classified as a semi-parametric density estimation method since it defines a very general class of functional forms for the density model. In this mixture model, a probability density function is expressed as a linear combination of basis functions. Improved classification performances have been demonstrated in many pattern recognition applications . Performance figures of more than 95% have already been reported for applications such as electronic nose and gas identification. Another interesting property of GMM is that the training procedure is done independently for each class in turn by constructing a Gaussian mixture of a given class. Adding a new class to a classification problem does not require retraining the whole system and does not affect the topology of the classifier making it attractive for pattern recognition applications. While GMM provides very good performances and interesting properties as a classifier, it presents some problems that may limit its practical use in real-time applications. One problem is that GMM can require large amounts of memory to store various coefficients and can require complex computations mainly involving exponential calculations. Thus, this scheme can be put to efficient practical use only if good hardware implementation strategies are developed.

In this project, we propose an efficient digital VLSI implementation that we believe can meet the computational requirement of GMM-based classifiers. First, after analyzing the complexity of the GMM classifier it was found that the vector-matrix multiplication and the exponential calculations are the most critical operations in the classifier. A good tradeoff between real-time processing and hardware resources requirements is obtained using a serial-parallel architecture and an efficient pipelining strategy. Second, a linear piecewise function (LPF) is proposed to replace the exponential calculation. Implementing LPF-based GMM, also permits to avoid the need for using area consuming look-up table (generally used in digital implementation) to implement the exponential function. The effect of both limited precision and the mixture models approximation using LPF on the classification performance is investigated using seven different data-sets. These data-sets are also used to compare the performance of GMM with other benchmark classifiers.

AN OPTIMUM ORA BIST FOR MULTIPLE FAULT FPGA LOOK-UP TABLE TESTING

2009-11-13T14:37:00.002+05:30

Introduction

Field Programmable Gate Arrays (FPGAs) have been widely used for rapid prototyping and manufacturing of complex digital systems, such as microprocessors and high speed telecommunication chips. FPGAs are suitable for prototypes of systems whose correct operation is necessary for the evaluation of new architectures. This requires changing the architecture during the design cycle with many reconfigurations of the same FPGA. The frequent reconfiguration of an FPGA makes it more fault-prone.There are many components of an FPGA to test for ensuring reliable usage of this device.

In this projecy, we only consider test of LEs and focus on LUTs within LEs. There are different methods for LE testing. One may use I/O pins for applying test vectors to LEs and collecting test results. But, usage of I/O pins for test decreases the number of I/O pins available for normal operation. If detailed information for JTAG implementation was available, usage of JTAG pins as an interface to apply test vectors and retrieve LEs' results would be suitable . A Built-In-Self-Test (BIST) architecture has been proposed for LEs testing, which eliminates the usage of I/O and JTAG pins. In this paper we address this approach for LUT testing of LEs. Our objective is to propose a BIST architecture with a good balance between various costs. Test time, test area and granularity are such trade-offs.

A SYMBOL-RATE TIMING SYNCHRONIZATION METHOD FOR LOW POWER WIRELESS OFDM SYSTEMS

2009-11-13T14:33:00.002+05:30

INTRODUCTION

TRADEOFF between system performance and power dissipation is one of the most critical issues in the design of a wireless portable device. Timing synchronization plays an important role in ensuring good signal decoding performance, since it determines the sampling timing and frequency of the analog-to-digital converter (ADC) on incoming signals or packets. Existing design approaches apply multirate sampling the incoming waveform with a fixed high-rate clock source that drives an ADC circuit. Those high-rate sampled signals are then calculated by an interpolation algorithm to yield a symbol-rate signal stream for data decoding. This design methodology to designing power-thirsty portable devices is facing increasing difficulty, because both the ADC circuits and the interpolation circuits are operated at a higher processing rate, resulting in higher power consumption.

To enable power reduction with symbol-rate sampling, both Mueller–Muller detection (MMD) and MMD-based timing recovery methods have been proposed under a pulse amplitude modulation (PAM) scheme for best sampling timing search within a sample period. The literature explores the timing synchronization issue in orthogonal frequency-division multiplexing (OFDM) systems based on the best block-boundary search for each fast Fourier transform (FFT) window.

Accordingly, multirate sampling,schemes have been developed to maintain system performance; hence the high-rate operations significantly increase power dissipation. To maintain system performance and, in the meantime, to reduce power dissipation, this work presents a dynamic sampletiming control (DSTC) scheme for symbol-rate synchronization in OFDM systems, where the optimal sampling timing within a symbol-period interval can be calculated. Unlike multirate sampling methods, this DSTC requires aided circuits in a clock source design to generate a phase-tunable clock waveform that corresponds to the best sampling instance as calculated by the DSTC. A digitally-controlled oscillator (DCO) design concept is applied to the phase-tunable clock generator (PTCG) design to enable this symbol-rate DSTC for low-power wireless applications.

IMPROVEMENT OF THE ORTHOGONAL CODE CONVOLUTION CAPABILITIES USING FPGA IMPLEMENTATION

2009-11-13T14:26:00.002+05:30

INTRODUCTION

When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability of these data. Error detection and correction techniques are therefore required. Some of those techniques can only detect errors, such as the Cyclic Redundancy Check , others are designed to detect as well as correct errors, such as Salomon Codes. However, the existing techniques are not able to achieve high efficiency and to meet bandwidth requirements, especially with the increase in the quantity of data transmitted.

Orthogonal Code is one of the codes that can detect errors and correct corrupted data. Our objective in this paper is to enhance the error control capabilities of orthogonal codes by means of Field Programmable Gate Array (FPGA) implementation.

ORTHOGONAL CODES
Orthogonal codes are binary valued and they have equal number of 1’s and 0’s. An n-bit orthogonal code has n/2 1’s and n/2 0’s; i.e., there are n/2 positions where 1’s and 0’s differ . Therefore, all orthogonal codes will generate zero parity bits. The concept is illustrated by means of an 8- bit orthogonal code as shown in Fig.1. It has 8-orthogonal codes and 8-antipodal codes for a total of 16-biorthogonal codes. Antipodal codes are just the inverse of orthogonal codes; they are also orthogonal among themselves.

FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM

2009-11-13T13:44:00.001+05:30

INTRODUCTION

Scalable encryption algorithm (SEA) is a parametric block cipher for resource constrained systems (e.g., sensor networks, RFIDs) that has been introduced . It was initially designed as a low-cost encryption/ authentication routine (i.e., with small code size and memory) targeted for processors with a limited instruction set (i.e., AND, OR, XOR gates, word rotation, and modular addition). Additionally and contrary to most recent block ciphers (e.g., the DES and AES Rijndael , the algorithm takes the plaintext, key, and the bus sizes as parameters and, therefore, can be straightforwardly adapted to various implementation contexts and/or security requirements. Compared to older solutions for low-cost encryption like tiny encryption algorithm (TEA) or Yuval’s proposal , SEA also benefits from a stronger security analysis, derived from recent advances in block cipher design/cryptanalysis.

In practice, SEA has been proven to be an efficient solution for embedded software applications using microcontrollers, but its hardware performances have not yet been investigated. Consequently, and as a first step towards hardware performance analysis, this letter explores the features of a low-cost field-programmable gate array (FPGA) encryption/ decryption core for SEA. In addition to the performance evaluation, we show that the algorithm’s scalability can be turned into a fully generic VHDL/Verilog design, so that any text, key, and bus size can be straightforwardly reimplemented without any modification of the hardware description language, with standard synthesis and implementation tools.

TECHNICAL INFORMATION - ACADEMIC PROJECT

2009-08-05T16:21:00.011+05:30

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IMPLEMENTATION OF RIJNDAEL S-BOX USING COMBINATIONAL LOGIC

2009-01-26T14:06:00.002+05:30

Introduction

This Project presents a combinational logic based Rijndael S-Box implementation for the SubByte transformation in the Advanced Encryption Standard (AES) algorithm for Field Programmable Gate Arrays (FPGAs). Recent publications on AES implementation have shown that the combinational logic based S-Box is proven for its small area occupancy and high throughput, given the fact that pipelining can be applied to this S-Box implementation as compared to the typical ROM based lookup table implementation which access time is fixed and unbreakable.

The Project deals with a brief introduction to the Advanced Encryption Standard, the SubByte and InvSubByte transformation, and finally a short discussion on the previous h ardware implementations of the SubByte/InvSubByte transformation.

The Advanced Encryption Standard

The AES algorithm has a fixed block size of 128 bits and a key length of 128, 192 or 256 bits. It generates its key from an input key using the Key Expansion function. The AES operates on a 4x4 array of bytes which is called a state. The state undergoes 4 transformations which are namely the AddRoundKey, SubByte, ShiftRow and MixColumn transformation.The AddRoundKey transformation involves a bitwise XOR operation between the state array and the resulting Round Key that is output from the Key Expansion function.

SubByte transformation is a highly non-linear byte substitution where each byte in the state array is replaced with another from a lookup table called an S-Box. ShiftRow transformation is done by cyclically shifting the rows in the array with different offsets. Finally, MixColumn transformation is a column mixing operation, where the bytes in the new column are a function of the 4 bytes of a column in the state array.Of all the transformation above, the SubByte transformation is the most computationally heavy.The SubByte and InvSubByte Transformation The SubByte transformation is computed by taking the multiplicative inverse in GF(28) followed by an affine transformation. For its reverse, the InvSubByte transformation, the inverse affine transformation is applied first prior to computing the multiplicative inverse.

The steps involved for both transformation is shown below.

SubByte: Multiplicative Inversion in GF(28) ->Affine Transformation

InvSubByte:Inverse Affine Transformation ->Multiplicative Inversion in GF(2*8)

A VHDL/VERILOG MODEL OF A IEEE1451.2 SMART SENSOR:CHARACTERIZATION AND APPLICATIONS

2009-01-19T21:55:00.003+05:30

INTRODUCTION

New sensors are required to be small, cheap, and smart. This project deals with intelligent sensors embedded in a single chip: a Verilog/VHDL model of an IEEE1451.2 Smart Sensor is proposed to obtain a portable STIM block suitable for customizable compact solutions and allowing low-cost, large-scale production. In order to evaluate performances of the proposed model, working prototypes have been built and some tests have been carried out in a real case (chemical detection sensors). The proposed Verilog/VHDL model has been compared with traditional, software-based, microcontroller solutions showing that a timing performance improvement greater than 50% can be obtained. Finally, to exemplify effectiveness of a portable VHDL model, a single-chip sensor with USB interface and integrated IEEE1451 structures has been realized and experimentally characterized.

In this projectaper, IEEE 1451 Standards are considered. Nowadays, some vendors supply smart sensors adherent to IEEE1451.2, the standard part that describes Smart Transducer Interface Module (STIM), Transducer Electronic DataSheet (TEDS), and Transducer Independent Interface (TII). Generally, these sensors have a microprocessor-centered architecture, where the CPU is devoted both to handle sensing element signal and to support IEEE1451.2 structure .However, it is said that few commercial products (e.g., Telemonitor TMI931A) are currently supporting IEEE1451.2 because of its relatively high cost; actually vendors prefer IEEE1451.4 , a simpler and cheaper standard solution. It is suitable for analog transducers (e.g., ENDEVCO i-TEDS accelerometers), since it defines only TEDS and requires a small number of additional components. In order to obtain a fast and more compact system, the systemon-chip (SoC) approach can be pursued; C (microcontroller), conditioning electronics, and even sensors can be integrated in one chip, reducing overall cost and simplifying assembly procedures .

A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE

2009-01-18T22:02:00.005+05:30

Introduction

This project describes a novel architecture of Universal Asynchronous Receiver Transmitter (UART) based on Recursive Running Sum (RRS) filter. UARTs are used for asynchronous serial data communication between remote embedded systems. If physical channel is noisy then, serial data bits get corrupted during transmission. The robust UART core described here, utilizes recursive running sum filter to remove noisy samples. Input data signal is directly sampled with system clock and samples are accumulated over a window size. The window size is user programmable and it should be set to one third of required bit period. The intermediate data bit is decoded using magnitude comparator. A majority voter is used to decode actual data bit from three intermediate data bits.

Universal Asynchronous Receiver Transmitter (UART) is used for asynchronous serial data communication between remote embedded systems. Standard UART cores three mid-bit samples to decode the serial data bit and the sampling rate is derived from external timer module. But if the physical channel is noisy then data bits get corrupted during transmission and it leads to wrong data decoding at receiver. To overcome the noise problem a digital low pass filter based architecture is proposed in this project.

Recursive Running Sum (RRS) is simple low pass filter, it can be used to remove noise samples from data samples at receiver .Serial receive data signal is directly sampled with system clock and samples are fed to RRS filter. The window size of the filter is user programmable and it decides baud rate. The robust UART core can be designed using Verilog HDL and can be implemented on Xilinx/ALTERA FPGA .

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ROBUST DWT-SVD DOMAIN IMAGE WATERMARKING:

2009-01-12T11:36:00.001+05:30

INTRODUCTION

Watermarking (data hiding) is the process of embedding data into a multimedia element such as image, audio or video. This embedded data can later be extracted from, or detected in, the multimedia for security purposes. A watermarking algorithm consists of the watermark structure, an embedding algorithm, and an extraction, or a detection, algorithm. Watermarks can be embedded in the pixel domain or a transform domain. In multimedia applications, embedded watermarks should be invisible, robust, and have a high capacity. Invisibility refers to the degree of distortion introduced by the watermark and its affect on the viewers or listeners. Robustness is the resistance of an embedded watermark against intentional attacks, and normal A/V processes such as noise, filtering (blurring, sharpening, etc.), resampling, scaling, rotation, cropping, and lossy compression. Capacity is the amount of data that can be represented by an embedded watermark. The approaches used in watermarking still images include least-significant bit encoding, basic M-sequence, transform techniques, and image-adaptive techniques.An important criterion for classifying watermarking schemes isthe type of information needed by the detector:

• Non-blind schemes: Both the original image and the secret key(s) for watermark embedding.

• Semi-blind schemes: The secret key(s) and the watermarkbit sequence.

• Blind schemes: Only the secret key(s).

Typical uses of watermarks include copyright protection (identification of the origin of content, tracing illegally distributed copies) and disabling unauthorized access to content. Requirements and characteristics for the digital watermarks in these scenarios are different, in general. Identification of the origin of content requires the embedding of a single watermark into the content at the source of distribution. To trace illegal copies, a unique watermark is needed based on the location or identity of the recipient in the multimedia network. In both of these applications, non-blind schemes are appropriate as watermark extraction or detection needs to take place in a special laboratory environment only when there is a dispute regarding the ownership of content. For access control, the watermark should be checked in every authorized consumer device used to receive the content, thus requiring semi-blind or blind schemes. Note that the cost of a watermarking system will depend on the intended use, and may vary considerably. Two widely used image compression standards are JPEG and JPEG2000. The former is based on the Discrete Cosine Transform (DCT), and the latter the Discrete Wavelet Transform (DWT).

In recent years, many watermarking schemes have been developed using these popular transforms. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee.In all frequency domain watermarking schemes, there is a conflict between robustness and transparency. If the watermark is embedded in perceptually most significant components, the scheme would be robust to attacks but the watermark may be difficult to hide. On the other hand, if the watermark is embedded in perceptually insignificant components, it would be easier to hide the watermark but the scheme may be least resistant to attacks. In image watermarking, two distinct approaches have been used to represent the watermark. In the first approach, the watermark is generally represented as a sequence of randomly generated real numbers having a normal distribution with zero mean and unity variance. This type of watermark allows the detector to statistically check the presence or absence of the embedded watermark. In the second approach, a picture representing a company logo or other copyright information is embedded in the cover image. The detector actually reconstructs the watermark, and computes its visual quality using an appropriate measure.

VIDEO DEMO

SIMULATION MODEL OF INVISIBLE ROBUST WATERMARKING USING VLSI/MATLAB

2009-01-03T10:32:00.000+05:30

INTRODUCTION

Owing to the usage of Internet, concerns about protecting and enforcing intellectual property (IP) rights of the digital content are mounting. Unauthorized replication and manipulation of digital content is relatively easy and can be achieved with inexpensive tools. Digital rights management (DRM) systems address issues related to ownership rights of digital content. Various aspects of content management – namely, content identification, storage,representation, and distribution – and IP rights management are highlighted in DRM.

Although unauthorized access of digital content is being prevented by implementing encryption technologies, these approaches do not prevent an authorized user from illegally replicating the decrypted content. igital watermarking is one of the key technologies that can be used in DRM systems for establishing ownership rights, tracking usage, ensuring authorized access,preventing illegal replication, and facilitating content authentication. Therefore, a two-layer protection mechanism utilizing both watermarking and encryption is needed to build effective DRM systems that can address IP rights and copyright issues .

In this project, the invisible watermarking aspect of DRM. Digital watermarking is the process of
embedding data, called a watermark, into a multimedia object such that the watermark can be detected whenever needed for DRM. The object may be an image, audio, video, text, or graphics. However, in this project“image” is the primary multimedia object, but similar work can be undertaken for other multimedia objects. In general, any watermarking algorithm consists of three parts: the watermark, the encoder (insertion algorithm), and the decoder and comparator (verification or extraction or detection algorithm). An entity, called the watermark key, which is unique and exhibits a one-to-one correspondence with every watermark, is also used during the process of embedding and detecting the watermark.

The key is private and known only to authorized parties,eliminating the possibility of illegal usage of digital content.Watermarks and watermarking techniques can be divided into different categories in various ways.Watermarks can be embedded in various domains, including the spatial and the frequency domains. The various transformations that have been used extensively as alternatives to the spatial domain are the discrete cosine transform (DCT), the Fourier transform (FT), and the wavelet transform (WT). Frequency-based methods have several advantages over spatial domain methods.For example, DCT domain techniques are more robust to attacks, and the perceptible quality of DCT domain watermarked images is better. On the other hand, spatial domain watermarking algorithms have less computational overhead than frequency domain algorithms. Spatial domain watermarking algorithms can also be faster in terms of computational time and hence are more suitable for real-time applications. Thus, we have focused on spatial domain watermarking because our ultimate goal is to develop VLSI architectures and chips such that real-time watermarking in the framework of electronic components would be possible.Digital watermarks can be divided into visible and invisible types, based on human perception.

A visible watermark is a secondary translucent image overlaid onto the primary image. An invisible watermark, on the other hand, is completely imperceptible. An invisible robust watermark is embedded in such a way that alterations made to the pixel value are not noticeable and can be recovered only with the appropriate decoding mechanism. An invisible fragile watermark is embedded in such a way that any manipulation or modification of the image would alter the watermark.

INVISIBLE WATERMARKING ALGORITHMS

Invisible robust image watermarking algorithm and an invisible fragile image watermarking algorithm whose VLSI architecture and chips are described in subsequent sections. The algorithms selected are simple and effective and, with modifications, can result in high-performance hardware that can perform watermarking in real time. We discuss the insertion and detection methods in brief, with the modifications necessary to facilitate hardware implementation.

VIDEO DEMO

A REAL-TIME IMPLEMENTATION OF CHAOTIC CONTOUR TRACING AND FILLING OF VIDEO OBJECTS ON RECONFIGURABLE HARDWARE

2009-01-01T11:09:00.003+05:30

INTRODUCTION

Contour tracing is a method that links connected neighborhood pixels in a binary edge frame, whereas contour filling fills the area inside a contour with a specific integer value, uniquely labeling each objects in an image. Contour tracing and filling are a fundamental element in many video and image processing applications such as video surveillance, medical image processing, computer vision and pattern recognition. Recently, solutions for robust contour tracing and filling methods have been considerably investigated using the state of the-art general purpose sequential processors.

However, these software-based implementations are too slow to archive real-time performance due to the high computational and memory bandwidth inherently required in contour tracing and filling algorithms. As such, an efficient hardware acceleration is inevitable. Although traditional full custom Application Specific Integrated Circuits (ASICs) provide high performance with low power and area, they suffer from flexibility, longer development time and expensive engineering cost.

In contrast, emerging FPGAs with embedded multipliers, memory blocks and high pin counts, are increasingly employed on hardware platforms in many signal/video processing applications. In this project, a proposed real-time, scalable and compact FPGA-based architecture for contour analysis. We utilize the FPGA heterogeneous resources efficiently, and employ advanced design techniques such as heavy pipelining and data parallelism to achieve high throughput but minimizing area and power dissipation.

ROBUST IMAGE WATERMARKING BASED ON MULTIBAND WAVELETS AND EMPIRICAL MODE DECOMPOSITION

2008-12-27T17:23:00.002+05:30

INTRODUCTION

With the rapid development of internet and wireless networks, multimedia security and digital rights management (DRM) are becoming increasingly important issues,.Te watermarking system has been viewed as a possible solution to control unauthorized duplication and redistribution of those multimedia data. Robustness, perceptually invisibility,and security are the basic requirements for a robust watermarking system. Seeking new watermark embedding strategy to achieve performance is a very challenging problem. In this project, a proposed new blind image watermarking scheme, which is based on the multiband wavelet transform and the empirical mode decomposition.

The watermark bits can be embedded either in the spatial domain or in the transform domain, while the latter watermark embedding strategy has been demonstrated to be more robust against most of attacks. We take that latter watermarking embedding strategy in our image watermark embedding scheme, particularly we embed watermark bits indirectly in the multiband wavelet domain with the dilation factor M>2 . For M=2 , there are lots of watermarking schemes available. For instance, Prayoth et al. introduced a semi-blind watermarking scheme based on the two-band multiwavelet transform.Hsieh et al proposed a nonblind watermarking scheme based on the two-band wavelet transform and the qualified significant wavelet tree (QSWT), which is robust to JPEG compression, image cropping, median filter etc., Lahouari et al suggested a watermarking algorithm based on the balanced two-band multiwavelet transform and the well-established perceptual model, which is adaptive and highly robust.

Ng et al put forward a maximum-likelihood detection scheme that is based on modelling the distribution of the image DWT coefficients using a Laplacian probability distribution function. In Bao et al. proposed a watermarking scheme by using a quantization-index-modulation (QIM) process via wavelet domain singular value decomposition (SVD). That scheme is robust against JPEG compression but extremely sensitive to filtering and random noising.

In this project, we use the multiband wavelet domain, instead of the two-band wavelet domain, to embed the watermark bits for the reason that the multiband wavelet domain provides more capacity for watermarking and more flexible tiling of the scale-space plane. Particularly, applying the MWT with the dilation factor an image is decomposed into subimages with narrower frequency bandwidth in different scales and directions. The subimages thus generated with middle frequency are favorable blocks to embed watermark bits in our watermark embedding strategy due to the robustness against JPEG compression and various noise attacks.

For the robustness of an image watermarking system, the watermark bits are usually embedded in the perceptually significant components, mostly the low or middle frequency components of the image . he EMD, first proposed in and later demonstrated to be very useful in many areas , provides a self-adaptive decomposition of a signal, and the mean trend, the coarsest component, of the signal is highly robust under noise attack and JPEG compression. So, we select the mean trend of each subimage in the multiband wavelet domain, instead of the subimage itself, to embed the watermark bits. Our experimental results show that the watermarking based on the MWT and EMD is robust against JPEG compression, Gaussian noise, Salt and Pepper noise, median filtering and ConvFilter (Gaussian filtering and sharpening) attacks.

HIGH-SPEED BOOTH ENCODED PARALLEL MULTIPLIER DESIGN

2008-12-24T23:48:00.002+05:30

INTRODUCTION

IN various computing and signal processing applications, parallel multiplier has been a basic building block for many algorithms. Many high performance algorithms and architectures have been proposed to accelerate multiplication. Multiplication can be divided into three steps:
generating partial products,

summing up all partial products until only two rows remain,
and adding the remaining two rows of partial products by using a carry propagation adder.

In the first step, two methods are commonly used to generate partial products. The first method generates partialproduct directly by using a 2-input AND gate. The second one uses radix-4 modified Booth encoding (MBE) to generate partial products. Radix-4 MBE has been widely used in parallel multipliers to reduce the number of partial products by a factor of two. In the speed performance of using radix-4 MBE was denied. However, it is found herein that these results depend on the implementation of MBE scheme.

After generating partial products, a partial product reduction tree (PPRT) is used to sum up all the partial products efficiently. The Wallace tree and Carry-save tree were developed to solve this problem. Both approaches employ 3:2 counter, i.e., full adder, as their basic element. Generally, a counter compresses (n-1) rows of partial products into log2(n)rows of partial products. However, the delay of an n ÿ 1 : log2n(n)counter is still proportional to log2(n) 1 times of a full adder (FA) as the inputs are assumed to arrive simultaneously. Therefore, using larger counters to build PPRT is not beneficial. The introduction of 4:2 compressor was a departure from the counter-based scheme. As the delay paths are well balanced, the latency for a 4:2 compressor is only three XOR delays, rather than two full adder delays. Note that the difference between the compressor and the traditional balanced delay tree is that the compressor considers the fast path and the slow path of a full adder. To further speed up, a search algorithm, Three-Dimensional- reduction-Method (TDM) , was proposed.

The TDM algorithm finds optimal PPRT by carefully modeling the delay paths of a counter and constructing n:2 column compressor according to inputs arrival time. Owing to the effectiveness of the column compressor, the PPRT constructed by using TDM algorithm outperforms the conventional designs. However, few studies have been done on using TDM with MBE. This paper examines the performance of parallel multiplier constructed with TDM and MBE. According to our results, such a design can be faster and occupy a smaller area than a non-Booth design.To generate the product in 2's complement format, a fast carry-propagation adder is required to add the final two rows of partial products from the PPRT.

The problem of designing a final adder is that the input signals do not arrive simultaneously, unlike the ordinary carry-propagation adder design that assumes all the inputs arrive simultaneously. Several techniques have been developed to eliminate or reduce the final adder delay. The Left-to-Right-Carry-Free algorithm proposed in requires n-level conversions to generate n-bit MSB products. It was improved in by reducing the levels required. However, this approach still cannot fully exploit the unequal delay profile because it applies to the MSB-part only. In a hybrid adder structure, which consists of ripple-carry adder, carry-skip adder, and conditional-sum adder blocks, was proposed. However, their empirical methodology is not general enough and requires many trials to determine the final adder partition boundary for different sizes of multiplier, thus increasing design effort. In this project, a propose design methodology for high-speed Booth encoded parallel multiplier.

SYNCHRONIZATION IN SOFTWARE RADIOS - CARRIER AND TIMING RECOVERY USING FPGAS

2008-12-24T23:43:00.002+05:30

Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, forward error control and protocol management. While there is a plethora of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and configurability.

Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper is about carrier and timing synchronization in SDRs using FPGA based signal processors. We describe and examine a QPSK Costas loop for performing coherent demodulation, and report on the implications of an FPGA mechanization. Symbol timing recovery is addressed using a differential matched filter control system. A tutorial style approach is adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined.

Introduction

The ever-increasing demand for mobile and portable communication requires high-performance systems employing advanced signal processing techniques to allow operation as close as possible to the Shannon information theoretic bound. However,not only must these systems provide exceptional performance, but due to market and fiscal pressures, they must be flexible enough to allow the rapid tracking of evolving and fluid standards. Software defined radios (SDRs) are emerging as a viable solution for meeting the conflicting demands in this arena. SDRs support multimode and multiband modes of operation to allow service providers an economic means of futureproofing these increasingly complex and costly systems.

During the last decade or so, radio system functionality has migrated from analog to digital implementations. We have observed, and continue to observe, the migration of the digital portion of a receiver along the signal conditioning chain, moving ever closer to the antenna. The implementation of these high-performance digital communication systems has been made possible by advances in semiconductor process technology, that has allowed the concept of system on a chip to become a reality.

In a communication environment the hardware platform must execute sophisticated source coding algorithms, modulation, demodulation, power control, channel coding, multiple access (TDMA, FDMA, CDMA) schemes and many levels of synchronization, starting at the physical layer, and moving up through the open system interconnection (OSI) protocol stack.

FPGA-BASED QPSK TRANSCEIVER DESIGN

2008-12-24T23:39:00.000+05:30

Software defined radios (SDR) are wireless devices which support multiple communication standards via a reconfigurable hardware platform. Due to the high programming flexibility, performance and efficiency, Field Programmable Gate Array (FPGA) has been employed to implement the SDR devices for seamless communication across different modulation modes and codec schemes.

System generator is a design tool which provides Simulink blockset for model building and hardware co-simulation. Meanwhile, it allows the translation from the simulink design to other intermediate formats such as HDL or netlist files. Furthermore, these files can be used for hardware implementation in other design tools.

The objective of this study is to explore the feasibility to implement a Quadrature Phase Shift Keying (QPSK) transceiver on a Xilinx FPGA platform by using system generator tools. In this project, direct digital synthesizer will be utilized to construct the digital upconverter and downconverter.

A sequence generator will be designed to generate a pseudo random sequence for system testing. Moreover, the carrier recovery and timing synchronization will be examined.

CANONICAL HUFFMAN CODE

2008-12-09T15:14:00.001+05:30

INTRODUCTION

A canonical Huffman code is a particular type of Huffman code which has the property that it can be very compactly described. Data compressors generally work in one of two ways. Either the decompressor can infer what codebook the compressor has used from previous context, or the compressor must tell the decompressor what the codebook is. Since a canonical Huffman codebook can be stored especially efficiently, most compressors start by generating a "normal" Huffman codebook, and the convert it to canonical Huffman before using it.

Algorithm

The normal Huffman coding algorithm assigns a variable length code to every symbol in the alphabet. More frequently used symbols will be assigned a shorter code. For example, suppose we have the following non-canonical codebook:

A = 11

B = 0

C = 101

D = 100

Here the letter A has been assigned 2 bits, B has 1 bit, and C and D both have 3 bits. To make the code a canonical Huffman code, the codes are renumbered. The bit lengths stay the same with the code book being sorted first by codeword length and secondly by alphabetical value:

B = 0

A = 11

C = 101

D = 100

Each of the existing codes are replaced with a new one of the same length, using the following algorithm:

• The first symbol in the list gets assigned a codeword which is the same length as the symbol's original codeword but all zeros. This will often be a single zero ('0').

• Each subsequent symbol is assigned the next binary number in sequence, ensuring that following codes are always higher in value.

• When you reach a longer codeword, then after incrementing, append zeros until the length of the new codeword is equal to the length of the old codeword. This can be thought of as a left shift.

By following these three rules, the canonical version of the code book produced will be:

B = 0

A = 10

C = 110

D = 111

Encoding the Codebook

The whole advantage of a canonical Huffman tree is that one can encode the description (the codebook) in fewer bits than a fully-described tree. Let us take our original Huffman codebook:

A = 11

B = 0

C = 101

D = 100

There are several ways we could encode this Huffman tree. For example, we could write each symbol followed by the number of bits and code:

('A',2,11), ('B',1,0), ('C',3,101), ('D',3,100)

Since we are listing the symbols in sequential alphabetical order, we can omit the symbols themselves, listing just the number of bits and code:

(2,11), (1,0), (3,101), (3,100)

With our canonical version we have the knowledge that the symbols are in sequential alphabetical order and that a later code will always be higher in value than an earlier one. The only parts left to transmit are the bit-lengths (number of bits) for each symbol. Note that our canonical Huffman tree always has higher values for longer bit lengths and that any symbols of the same bit length (C and D) have higher code values for higher symbols:

A = 10 (code value: 2 decimal, bits: 2)

B = 0 (code value: 0 decimal, bits: 1)

C = 110 (code value: 6 decimal, bits: 3)

D = 111 (code value: 7 decimal, bits: 3)

Since two-thirds of the constraints are known, only the number of bits for each symbol need be transmitted:

2, 1, 3, 3

With knowledge of the canonical Huffman algorithm, it is then possible to recreate the entire table (symbol and code values) from just the bit-lengths. Unused symbols are normally transmitted as having zero bit length.

Pseudo code

Pseudo code for construction of a canonical Huffman table could look something like the following:

code = 0

while more symbols:

print symbol, code

code = code + (1 << (current bit length - 1))

if next bit length > current bit length:

code = code << (next bit length - current bit length)