I decided to dabble with my culinary skills today. I made the north Indian delicacy, Cholae (garbanzo beans). I took my job pretty seriously, adding the thousand five hundred (kidding) ingredients at the right time, and in right proportions. So, when the stuff came to a boil, it was time to taste it to confirm that everything was OK. I had to do the tasting twice before convincing myself everything was ok. However, the whole process threw open a few questions which people might experience in their professional lives. The cooking part can be related to the “development” of a product, and the tasting part can be related to the “verification” of the product. Take the semiconductor industry for example. This industry is consumed by the need for verification. The time it takes to verify a product far exceeds the time to develop the product in the first place. Every second year, a new standard emerges. While, development has mostly been limited to Verilog language, verification has gone from C++ to systemVerilog to VMM to OVM to you name it.

So, how much verification is too much verification? In the kitchen parlance, when should I stop tasting the food? If I search for eternal quality, I might continue tasting the food until I have either consumed all of the food, or it is well past dinner time. On the other hand, I could do it just once, make some changes to my preparation and call it done. The former approach will ensure nobody gets food. The latter approach will ensure everyone gets bad food. The end result in both cases is the same: hungry and angry people. Similarly, over-verification delays the product’s time to market, making it essentially useless. Under verification causes production stops, which again hits the company’s schedule, and its reputation in the industry takes a nose dive.

The key to successful products is to find the right balance to ensure that the end product is excellent, but not perfect. The quest for perfection is like the 80-20 rule. It is relatively easy to get the product to 80% quality, but the last twenty percent becomes progressively harder. So, a 95% product quality may be acceptable to most customers, and achievable in reasonable time. Depending on the type of product, spending time over the last 5% may not be cost efficient. On the other hand, enough effort must be spent to get the product from 80 to 95%. If this is not done, the product may not be usable.

In kitchen parlance, a lot depends on what I do with my first tasting. Depending on how well I analyze the taste, I can make a significant progress between the first and the second tasting. A dumb me would just add salt, only to realize later that I added too much salt. Then I would add something else to neutralize the salt and end up running in circles. The smart me would analyze the amount of salt required, and also realize that certain ingredients are missing. I would add them in the right quantity, and by the time I taste again, my dish would have improved significantly.

Similarly, a verification engineer can choose to be dumb or smart. A dumb engineer usually would come back with a one line statement that reads “code crashed on line 1293”. The developer would go back, fix the problem and send the code back to the verification guy. His second report would read “code crashed in line 1324”. Now, when the code at 1394 is fixed, it would crash on line 1293!!! The code would be ping-ponged between the developer and the verification engineer, until the developer, verification engineer and the manager are fired for not releasing the product on time. The smart verification engineer will read the architecture specification and will have full knowledge of the product. He will understand the root cause of the problem, and provide as much details as possible to the developer. The developer will then fix many problems in a single iteration, thereby reducing his workload, as well as that of the verification engineer. I wish life were so easy!!!

For more great posts like this, visit Srini’s blog at: cyplayer.com

Many design teams have in fact given up on proprietary interfaces and moved to increase use of IP offered by an external supplier that relies on standardized interfaces— such as AHB, AXI, and OCP to name a few. But even when standard interfaces are chosen, you still have to deal with multiple interface protocols. For example, a given IP core may only support a particular standard interface (e.g. AHB) while another IP core needed in the design supports a different standard (e.g. AXI). So even with the best of intentions and planning, the SoC design team still must deal with communications among multiple protocols.

SoCs are intricate and complex devices and are becoming even more so over time. Interfaces such as the AMBA® (APB, AHB, AXI) protocols have been used for several years now. APB was the first simple interface defined by ARM. As complexity increased, ARM introduced AHB, and then later AXI, and now AXI4. With each new definition, design teams that used AMBA interfaces were forced to learn a new interface to support the next iteration of a more complex SoC. The AMBA ecosystem today is widely available and heavily proliferated, and for that reason, SoC organizations now opt for AMBA interfaces by default for their designs.

Integrating multiple IP cores with different interfaces is no small feat, and is a costly consideration for any design project. The design team is expected to not only understand its own proprietary interfaces (if used), but also the industry standard interfaces just mentioned. Teams can continue what they’re doing today and learn each new interface to design a custom on-chip communications network. However, this approach has the disadvantage of limiting the amount of reuse from chip-to-chip, and with increasing SoC complexities, the design time and expertise are also a big factor.

To ease the design effort, I recommend that SoC teams consider choosing a configurable on-chip communications interface that is universal in its protocol support while agnostic to the majority of industry interfaces. This greatly decreases the integration effort while dramatically improving overall time-to-market. Two of the commonly used interfaces today are AXI and OCP.

Although a standard protocol, AXI for example, runs into limitations with the width of the signals and thus designers are forced to breach the specification. Having universal connectivity support in the on-chip network can deal with these breaches of the AMBA specification. In the case of an OCP interface, protocol breaches can be avoided because the OCP specification promotes the idea of configurable interfaces making it very flexible. OCP however, does not have a widely proliferated ecosystem similar to AMBA. The configurable nature of OCP is an advantage, however this flexibility adds ramp-up costs because it takes time to understand and use the interface efficiently. At Sonics, our goal is to minimize both of these concerns for design teams by providing an on-chip communications network that provides a universal “socket” that will isolate your interface protocol from the on-chip communications network—significantly simplifying the overall design.

As design teams struggle with ever-growing SoC complexity, saving time and money are critical concerns. The choice (or lack thereof) of specific cores with a given interface will have a direct impact on both. Future chip design considerations are also part of the mix. Ask yourself whether it’s better to select an on-chip network that is scalable and highly configurable across the SoC, or a custom interface that has to be re-designed for each chip and contend with standard, semi-standard and custom protocols? Keep these design decisions in mind before you start your next SoC project so you are carefully weighing all critical options and can make the most informed choice for your specific design and application.

Ravi Venugopalan
Verification Manager

What do Design & Reuses’ IP-SoC conferences have in common with an Icelandic volcano? While several analogies come to mind, suffice it to say the folks at D&R are like evangelists spreading the IP message, much like molten lava, over the widest terrain possible. I participated in the latest in a series of conferences by Design & Reuse – IP SoC Days hosted by SemIsrael in Tel Aviv, April 15th, during the eruption of Iceland’s now infamous volcano.

With the growing need for SoC developers to license IP, the goal of Design & Reuse is to expand the worldwide footprint of conferences and market the clear advantages of IP around the globe, despite unforeseen acts of nature.

There are now more than 450 IP companies and these seminars are helping to match buyer and seller by making information available and to demonstrate the needs of the industry from both the consumer and supplier perspective.

I was busy with the seminar and not paying attention to world news. If I had, I would have taken more notice of all the emerging travel challenges the volcano eruption was causing. Friday morning I entered Tel Aviv airport at 2:30 a.m. for my 5 a.m. flight to SFO via Frankfurt, planning to see my wife and family by noon the same day (CA time). Despite all the travel difficulties (and with the help of a great travel agent), I turned out to be one of the lucky ones, being stranded for only one day compared to several days for many of the other show attendees. I got on a direct flight from Tel Aviv to Newark and spent the night in Newark (home in the USA at least). The best part of the trip was that I had an opportunity to play with the new iPad courtesy of one of the flight attendants.

It turns out, Israel was an excellent location for this event, given all the SoC design activity in the region. The design community in Israel is a small but loyal and tightly linked group that supports the progression of SoC design. The seminar had a solid turn out, more than 70 attendees. Shuka Zernovizky and Tal Oren the creators of the SemIsrael portal were gracious hosts, so check-out their website when you have a moment.

Conference highlights – information for IP Seekers
Cadence, one of Sonics’ key partners, presented an overview of the ChipEstimate tool that helps guide users navigate through the plethora of IP choices. The company also shared its verification IP solutions that are critical for customers to meet their time-to-market needs.

My presentation focused on the direction of the IP industry, including the necessity for more abstraction. In the face of growing SoC complexity, more abstraction is necessary to counter increasing design costs along with design strategies that dramatically increase design reuse. As software costs continue to rise, now estimated to be greater than 50 percent of the SoC design cost, this has accelerated subsystems that reuse both hardware and software from prior designs.

We’re seeing SoC designs bifurcate into either value designs or high-performance designs. Value designs focus on leveraging mature process nodes and pushing to meet design cycle times. High-performance designs are leaning into the advanced process nodes working to reach the right level of platform functionality to meet some of the most demanding design opportunities faced by semiconductor companies and OEMs. Sonics’ broad portfolio offers a wide array of solutions to meet the needs for the on-chip network that connects the on-chip IP, while providing the desired level of data- flow services (e.g. QoS, power management, security, firewalls).

Joao Vital, of Synopsys, another key Sonics partner, was up next and discussed the challenges of analog IP along with the range of solutions that Synopsys offers for analog design. He also gave a nice overview showing the top line advantages in basic analog functions and the ways Synopsys builds a large library of sophisticated analog subsystems.

We’re Back….Sonics is back in Israel again this week, as Grant Pierce, our CEO and co-founder, participates in Sol Goodman’s second annual ChipEx conference and exhibition, and attends the GSA Israel Executive forum Tuesday, May 4. Best wishes and shalom!

Jack Browne
Sr. VP of Sales & Marketing at Sonics, Inc.
twitter.com/Jackb650

For those who may not be aware, Constellations is a marketing and sales effort of many different semiconductor IP companies joining together to get their messages to the market and generate customer interest.

These companies, representing a broad range of differentiated IP, presented the audience with information about their IP products. Panels on business and technical issues followed.

The business panel, chaired by IPextreme’s Warren Savage, highlighted the importance for customers and IP providers, to have straightforward conversations about key business issues with the goal of getting a contract defined and in place.

While I don’t ever imagine having a one-size-fits-all contract, being able to present business issues candidly and quickly, during the negotiation process, can result in a faster deal that is agreeable to both the customer and IP provider. As IP becomes more complex, we, as leaders in this industry, should continually strive to simplify business deals for everyone’s benefit.

The technical panel, chaired by Ron Wilson of EDN Magazine, focused on differing perspectives and assumptions about how to use IP within complex SoC systems. Reuse, integration, and standardization were all discussed. Of course, these are issues that we at Sonics support and have become part of our marketing mantra.

For me, the key take-away of the day was the discussion about the importance of making the customer successful. Early in my career, I learned that taking care of customers and ensuring they were successful was the answer to any repeat business. That is certainly the case for IP and managing a long-term relationship between IP supplier and customer.

Another highlight of the seminar was IPextreme’s demonstration of how quickly and easily it is to combine IP using SNAP in a simple SoC configuration using an Altera Cyclone III FPGA system. The simple demonstration included a Coldfire V1 processor and five peripheral blocks that were connected using SNAP (Sonic Network for AMBA Protocol) product to build the interconnect. The entire design was less than 65K gates. I was pleased to hear about the excellent experience of the IPextreme engineers. SNAP enable a fast design cycle as it only took three days from the start of the evaluation to a working FPGA for demonstration at the seminar. SNAP reduced to days what would have taken the engineers several months using their existing technology. AND, the gate count with SNAP was actually 10 percent smaller than that of their internal technology. So, for simple to complex SoC designs, it is in the best interest of SoC teams to look at the latest IP technology to reduce both execution time and cost.

All in all, the conference was a great chance to get together with folks in the industry, share stories, and talk about how to enable customers to win in these tough times. My presentation from the conference is embedded below so take a look. Comments? Questions? Just let me know.

Now off to Israel for this weeks Design and Reuse IP SOC conference in Tel Aviv.

Jack Browne
VP of Sales & Marketing at Sonics, Inc.
twitter.com/Jackb650

The recent IP-SoC Days, hosted by Design & Reuse, provided an excellent opportunity for IP providers (intellectual property) and IP customers to exchange ideas and requirements and to review the state of the IP industry.  Here’s my take on the conference:

“Getting no respect”
One of the conference presenters called IP the “Rodney Dangerfield” of the semiconductor industry since it’s a $1.3B industry today compared to the $255B semiconductor industry. Yet if you look at the content of SoCs, 50% or more could be 3^rd party licensed IP. And the licensed IP content will continue to rise given that system and semiconductor manufacturers are being asked to do more with less.  In fact, an engineering VP from a fabless semiconductor company said,  ‘We’re being asked to execute faster with less.’

Many companies struggle to launch new SoC programs because designers haven’t completed ongoing ones.  To compound the problem, SoC speed and complexity continues to grow—making it impossible for any one company to develop all the IP needed to successfully execute on schedule.  Clearly, having the ability to license value-added, high-quality IP is critical to the overall success and progression of the SoC industry.

“IP industry in the cat bird seat?”
Semiconductor manufacturers have no choice today but to license some of their IP.  Even the largest companies license “star IP” like processors, along with commodity IP components.  Even so, much of the discussion boils down to the question of “make vs. buy.”   However, the real dilemma for many companies is where to draw the line between the IP they need to develop for their unique value-add (differentiation) vs. purchasing IP.  Given these inherent challenges, it is critical for the success of the IP industry to make these decisions easier to answer and more obvious by providing complete products, including verification IP, software and support.

Jack Browne of Sonics, Inc. and D&R CEO, Gabriele Saucier, at Design and Reuse IP-SoC Days 2010 - Santa Clara - March 23, 2010

I also noticed that several speakers mentioned the growing use and importance of 3^rd party bus IP.  This is certainly good to hear from our perspective, but not a surprise.  With the growing number of cores in an SoC, “rolling your own” bus is becoming a more complicated endeavor.  Another factor is that the bus IP touches every other core in the system.  It serves as the glue or center of the SoC, and ensures that everything comes together properly.  Since Sonics’ IP must “play” with all other IP, it is critical for us to maintain our value by being able to connect to anyone’s IP at anytime.  This is evident in Sonics’ recent announcement as one of the first supporters of the AMBA® 4 specification well ahead of the commercial release of cores with this interface.

Jack Browne of Sonics, Inc. presenting at Design and Reuse IP-SoC Days 2010 - Santa Clara - March 23, 2010

Future Direction of IP – The rise of software?
As the industry continues to evolve, the significance and role of software proves to be an interesting discussion.  Software resources are clearly dominating SoC design teams. Some at the conference even speculated that we will see the emergence of software IP companies.  Many IP companies today are providing software support, stacks, drivers and services, so I expect this will be an even larger part of the IP portfolio in the future.  In any case, the IP industry will ultimately gain the “respect” it deserves as the SoC industry becomes increasingly aware of the critical role that 3^rd party IP plays in its longevity and success.

Frank Ferro
Director of Marketing
Sonics, Inc.
www.sonicsinc.com
www.twitter.com/sonicsinc

At Sonics, we believe it’s clear that SoC design teams are spending more time and engineering resources dealing with on-chip connectivity challenges as chip complexity continues to increase.  What was once a simple task of connecting a few cores has now grown into a complex network of connections with many heterogeneous cores.  If you’re faced with the nagging issues of: protocol conversions for new and legacy cores; latency sensitive cores; memory efficiency and memory bottlenecks, or preserving your existing multi-layer AHB designs, then I suggest that you tune in to our webinar.

Senior architect, Steve Hamilton, will discuss some of the existing multi-layer AHB design challenges for embedded SoCs, along with solutions to these challenges.  He’ll also show how SoC designers can effectively solve inherent AHB bandwidth limitations and how to convert multi-layer designs into concurrent designs.  Steve’s presentation will also focus on ‘heterogeneity’ – dealing with different data widths, protocols and clock frequencies.  And he’ll outline the most cost effective approach for combining new and legacy cores, simplifying on-chip bus designs, and optimizing the performance of AMBA-based SoCs for wireless, consumer, home networking and automotive applications.

Cracking the Multi-layer Design Code: How to Cost-effectively Simplify and Optimize AMBA-based designs

So remember to mark your calendar for a webinar, jammed-packed with information you can use TODAY to solve some of your most critical SoC design issues.  To learn more about the conference and to register please visit, http://eetimes.com/arm.

I’ll be tuning in, I hope you will too!

Frank Ferro
Director of Marketing
Sonics, Inc.
www.sonicsinc.com
www.twitter.com/sonicsinc

I wanted to share some recent Sonics milestones with you— that continue to demonstrate Sonics’ vision and leadership, as well as the pivotal role IP is playing in system performance and the SoC design process. With the company’s increased customer traction, Sonics recently announced it surpassed the 750 million unit mark with total licensee shipments, and is now on track to reach one billion units by year-end. Our customers’ design innovations have helped Sonics grow to become the world’s number one supplier of silicon-proven IP for on-chip networks and the only IP company that allows designers to integrate any IP from anywhere, anytime to deliver an SoC with the right features into the market at the right time. We look forward to sharing our plans with you as we invest in technology, expand our global presence even further this year and continue to maintain a world-class engineering organization that is larger than any of our competitors.

From netbooks and Wi-Fi routers to mobile internet devices and HDTVs, Sonics has long been a leader in digital, home and mobile entertainment, with tremendous growth being fueled by many of today’s hottest consumer markets. Following one of our strongest product cycles in years, Sonics continues to address customer demand at every level of the market, and recently unveiled SNAP, a low-cost platform to simplify on-chip bus designs for complex embedded SoCs.

As a pioneer in network-on-chip (NoC) technology, Sonics has been helping semiconductor companies tackle their most challenging memory, bandwidth and on-chip connectivity issues for more than 13 years. Sonics’ mission is to help companies achieve their SoC integration and time-to-market goals, and to cost-effectively solve today’s most critical hardware, software, performance and power challenges on-chip. We help semiconductor companies choose from the most advanced on-chip network technologies to deliver the performance necessary to build quality, value-added SoCs, and keep pace with the rapidly moving consumer electronics markets.

Here’s to your success in 2010! We look forward to seeing you at these industry events in your area.

Grant Pierce
President & CEO
Sonics, Inc.
www.sonicsinc.com
www.twitter.com/sonicsinc

Sonics' SNAP Cature Tool - GUI Screenshot

SNAP is Sonics’ brand new, client-based solution for designing on-chip buses for any complex SoC. With SNAP, you can capture, test, and analyze your designs quickly and easily. Earlier this year, we announced SNAP as a cost-effective, turn-key solution for SoC designers. Now it’s available for everyone!  SNAP’s unique IP delivery system allows you to quickly and easily download the SNAP design capture tool from the Sonics Website, install and go. No need to worry about complicated licenses and key files inherent in other conventional tools. SNAP allows you to explore various chip bus architectures via an intuitive GUI, delivering valuable insight into performance, gate count and power early in the design stage—while seamlessly creating a rapid and reliable SoC design environment.

SNAP helps to simplify on-chip bus design for complex embedded SoCs by turning multilayer bus designs into an IP block. The product is well-suited for embedded wireless, home networking and automotive applications, including 3G/4G baseband and WiMAX baseband, gateways and wireless routers, and automotive control and telematics. As a complete platform solution, SNAP lowers development costs by reducing engineering costs for multi-layer designs. For example, all arbitration, clocks, data width and protocol conversions are done automatically.

So, how do you know if SNAP is right for you? Are you experiencing any of the following?

• You have an increasing number of cores with new and legacy interfaces
• You’re reaching the limits of AHB bus performance
• You’re using an ever increasing amount of engineering resources due to the shortcomings of your existing bus design tools and methodology
• You’re evolving designs to incorporate faster processors like ARM (AXI) or MIPS (OCP)
• You’re re-architecting a design to optimize for low power
• You’re hitting the memory bottleneck with your current solution

If so, then SNAP may be just what you’re looking for: A simple to use, low-cost alternative to your current SoC design tools and methodology.

SNAP - Sonics Network for AMBA Protocol - Download Now!

Go to http://www.sonicsinc.com/snap.htm and download your free copy today. We’d love to hear your thoughts. And make sure to stay tuned for upcoming customer and partner feedback and how these companies are simplifying their on-chip bus designs with SNAP.

Stephen Tomasello at Sonics, Inc.
http://twitter.com/S_Tomasello

EI – 688 – Sonics