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Method for manufacturing semiconductor device

Patent Number: RE44236
Publication Date: 2013-05-21
Inventors: ; ; ;

A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed ...

Patterning of antistiction films for electromechanical systems devices

Patent Number: 8445390
Publication Date: 2013-05-21
Inventor:

A laser absorption layer is first selectively formed in a seal pattern region surrounding an array of electromechanical systems elements, followed by depositing an antistiction layer as a blanket layer over the substrate and the laser absorption layer. The antistiction layer is then selectively removed from the seal pattern using a laser. An epoxy sealing material is provided in the seal pattern where the antistiction layer was removed and a backplate is sealed to the substrate using ...

Etchant treatment processes for substrate surfaces and chamber surfaces

Patent Number: 8445389
Publication Date: 2013-05-21
Inventors: ;

Embodiments of the invention generally relate to methods for treating a silicon-containing material on a substrate surface and performing a chamber clean process. In one embodiment, a method includes positioning a substrate containing a silicon material having a contaminant thereon within a process chamber and exposing the substrate to an etching gas containing chlorine gas and a silicon source gas while removing the contaminant and maintaining a temperature of the substrate within a range ...

Methods of forming semiconductor devices and devices formed using such methods

Patent Number: 8445388
Publication Date: 2013-05-21
Inventors: ;

Single source precursors are subjected to carbon dioxide to form particles of material. The carbon dioxide may be in a supercritical state. Single source precursors also may be subjected to supercritical fluids other than supercritical carbon dioxide to form particles of material. The methods may be used to form nanoparticles. In some embodiments, the methods are used to form chalcopyrite materials. Devices such as, for example, semiconductor devices may be fabricated that include such ...

Epitaxial silicon growth

Patent Number: 8445387
Publication Date: 2013-05-21
Inventors: ;

Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the ...

Smoothing method for semiconductor material and wafers produced by same

Patent Number: 8445386
Publication Date: 2013-05-21
Inventor:

A smoothing method for semiconductor material and semiconductor wafers produced by the method are disclosed. Semiconductor wafers with reduced atomic steps, as well with reduced scratches and subsurface defects can be produced. Such wafers feature an improved growth surface that can provide for the growth of an epilayer with reduced macroscopic defects and defect densities. A method of smoothing the surface of a wafer according to example embodiments of the invention includes planarizing ...

Methods for etching carbon nano-tube films for use in non-volatile memories

Patent Number: 8445385
Publication Date: 2013-05-21
Inventors: ; ; ;

Memory cells, and methods of forming such memory cells are provided that include a steering element coupled to a carbon-based reversible resistivity-switching material. In particular embodiments, methods in accordance with this invention etch a carbon nano-tube (“CNT”) film formed over a substrate, the methods including coating the substrate with a masking layer, patterning the masking layer, and etching the CNT film through the patterned masking layer using a non-oxygen based ...

High density six transistor FinFET SRAM cell layout

Patent Number: 8445384
Publication Date: 2013-05-21
Inventor:

Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs ...

Transparent nanocrystalline diamond contacts to wide bandgap semiconductor devices

Patent Number: 8445383
Publication Date: 2013-05-21
Inventors: ; ; ; ; ; ; ;

A heterojunction between thin films of NCD and 4H—SiC was developed. Undoped and B-doped NCDs were deposited on both n− and p− SiC epilayers. I-V measurements on p+ NCD/n− SiC indicated Schottky rectifying behavior with a turn-on voltage of around 0.2 V. The current increased over eight orders of magnitude with an ideality factor of 1.17 at 30° C. Ideal energy-band diagrams suggested a possible conduction mechanism for electron transport from the SiC conduction band to either the ...

Side wall pore sealing for low-k dielectrics

Patent Number: 8445382
Publication Date: 2013-05-21
Inventor:

A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the ...

Oxide-nitride stack gate dielectric

Patent Number: 8445381
Publication Date: 2013-05-21
Inventors: ;

A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 ...

Semiconductor having a high aspect ratio via

Patent Number: 8445380
Publication Date: 2013-05-21
Inventors: ; ; ; ;

The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed ...

Method of manufacturing semiconductor device

Patent Number: 8445379
Publication Date: 2013-05-21
Inventors: ; ;

A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the ...

Method of manufacturing a CMOS device including molecular storage elements in a via level

Patent Number: 8445378
Publication Date: 2013-05-21
Inventor:

Memory cells in integrated circuit devices may be formed on the basis of functional molecules which may be positioned within via openings on the basis of appropriate patterning techniques, which may also be used for forming semiconductor-based integrated circuits. Consequently, memory cells may be formed on a “molecular” level without requiring extremely sophisticated patterning regimes, such as electron beam lithography and the ...

Mechanically robust metal/low-k interconnects

Patent Number: 8445377
Publication Date: 2013-05-21
Inventors: ; ; ;

A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated ...

Post-etching treatment process for copper interconnecting wires

Patent Number: 8445376
Publication Date: 2013-05-21
Inventor:

A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top ...

Method for manufacturing a semiconductor component

Patent Number: 8445375
Publication Date: 2013-05-21
Inventors: ;

A semiconductor component and methods for manufacturing the semiconductor component that includes a double exposure of a layer of photoresist or the use of multiple layers of photoresist. A metallization structure is formed on a layer of electrically conductive material that is disposed on a substrate and a layer of photoresist is formed on the metallization structure. The layer of photoresist is exposed to light and developed to remove a portion of the photoresist layer, thereby forming an ...

Soft error rate mitigation by interconnect structure

Patent Number: 8445374
Publication Date: 2013-05-21
Inventors: ; ;

A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large ...

Method of enhancing the conductive and optical properties of deposited indium tin oxide (ITO) thin films

Patent Number: 8445373
Publication Date: 2013-05-21
Inventors: ;

Certain example embodiments of this invention relate to a method of activating an indium tin oxide (ITO) thin film deposited, directly or indirectly, on a substrate. The ITO thin film is baked in a low oxygen environment at a temperature of at least 450 degrees C. for at least 10 minutes so as to provide for (1) a post-baked resistivity of the ITO thin film that is below a resistivity of a corresponding air-baked ITO thin film, (2) a post-baked visible spectrum absorption and transmission ...

Selective silicide formation using resist etch back

Patent Number: 8445372
Publication Date: 2013-05-21
Inventors: ; ; ;

Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of ...

Self-aligned contacts

Patent Number: 8445371
Publication Date: 2013-05-21
Inventors: ; ;

A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial ...

Trench junction barrier controlled Schottky

Patent Number: 8445370
Publication Date: 2013-05-21
Inventors: ;

A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal ...

Method for fabricating semiconductor device

Patent Number: 8445369
Publication Date: 2013-05-21
Inventor:

A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern ...

Semiconductor device and method for manufacturing same

Patent Number: 8445368
Publication Date: 2013-05-21
Inventors: ;

A semiconductor device includes a trench MOS barrier Schottky diode having an integrated PN diode and a method is for manufacturing ...

Methods of manufacturing semiconductor devices

Patent Number: 8445367
Publication Date: 2013-05-21
Inventors: ; ; ;

In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a ...

Electron beam annealing apparatus and annealing methods using the same

Patent Number: 8445366
Publication Date: 2013-05-21
Inventors: ;

Electron beam annealing apparatuses for annealing a thin layer on a substrate and annealing methods using the apparatuses are provided. The electron beam annealing apparatuses may include an electron beam scanning unit that may scan a pulsed electron beam onto a ...

Single scan irradiation for crystallization of thin films

Patent Number: 8445365
Publication Date: 2013-05-21
Inventor:

A method of processing a polycrystalline film on a substrate includes generating laser pulses, directing the laser pulses through a mask to generate patterned laser beams, each having a length l′, a width w′, and a spacing between adjacent beams d′; irradiating a region of the film with the patterned beams, said beams having an intensity sufficient to melt and to induce crystallization of the irradiated portion of the film, wherein the film region is irradiated n times; and after ...

Methods of treating semiconducting materials including melting and cooling

Patent Number: 8445364
Publication Date: 2013-05-21
Inventors: ; ; ;

A method for treating semiconducting materials includes providing a semiconducting material having a crystalline structure, pre-heating a portion of the semiconducting material to a temperature less than the melting temperature of the semiconducting material, and then cooling the semiconducting material prior to exposing at least the portion of the semiconducting material to a heat source to create a melt pool, and cooling the semiconducting ...

Method of fabricating an epitaxial layer

Patent Number: 8445363
Publication Date: 2013-05-21
Inventors: ; ; ;

A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° ...

Apparatus and method for programming an electronically programmable semiconductor fuse

Patent Number: 8445362
Publication Date: 2013-05-21
Inventors: ; ; ; ; ;

An apparatus and method for programming an electronically programmable semiconductor fuse applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pulses provides a level of programming current sufficiently high to ensure reliable and effective electromigration while avoiding exceeding temperature limits of the fuse ...

Method of dividing a semiconductor wafer having semiconductor and metal layers into separate devices

Patent Number: 8445361
Publication Date: 2013-05-21
Inventor:

A method of dividing a semiconductor wafer having a metal layer includes removing all or substantially all of the semiconductor material in scribe streets while the wafer is supported by a support, turning over the wafer and while using a second support to support the wafer, introducing a heat energy flux into the metal layer to remove metal of the metal layer from the scribe ...

Method for manufacturing semiconductor device

Patent Number: 8445360
Publication Date: 2013-05-21
Inventors: ; ;

A method for manufacturing a semiconductor device makes it possible to efficiently polish with a polishing tape a peripheral portion of a silicon substrate under polishing conditions particularly suited for a deposited film and for silicon underlying the deposited film. The method includes pressing a first polishing tape against a peripheral portion of a device substrate having a deposited film on a silicon surface while rotating the device substrate at a first rotational speed, thereby ...

Manufacturing method and manufacturing apparatus of semiconductor device

Patent Number: 8445359
Publication Date: 2013-05-21
Inventors: ;

To provide a manufacturing method of a semiconductor device using an SOI substrate, by which mobility can be improved. A plurality of semiconductor films formed using a plurality of bond substrates (semiconductor substrates) are bonded to one base substrate (support substrate). At least one of the plurality of bond substrates has a crystal plane orientation different from that of the other bond substrates. Accordingly, at least one of the plurality of semiconductor films formed over one ...

Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device

Patent Number: 8445358
Publication Date: 2013-05-21
Inventor:

An object of the present invention is to reduce the influence of a foreign substance adhering to a single crystalline semiconductor substrate and manufacture a semiconductor substrate with a high yield. Another object of the present invention is to manufacture, with a high yield, a semiconductor device which has stable characteristics. In the process of manufacturing a semiconductor substrate, when an embrittled region is to be formed in a single crystalline semiconductor substrate, the ...

Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device fabricated using the method

Patent Number: 8445357
Publication Date: 2013-05-21
Inventors: ;

Provided are a method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated using the method. The method includes: forming a mask film, which exposes a portion of a substrate, on the substrate; forming a first buried impurity layer, which contains impurities of a first conductivity type and of a first concentration, in a surface of the exposed portion of the substrate by using the mask film; removing the mask film; forming a second ...

Integrated circuit having back gating, improved isolation and reduced well resistance and method to fabricate same

Patent Number: 8445356
Publication Date: 2013-05-21
Inventors: ; ; ;

Disclosed is a method of forming a structure and a resulting structure. The method includes providing a semiconductor substrate; forming a first opening to a first depth in the semiconductor substrate; amorphizing semiconductor sidewalls of an upper portion of the first opening leaving unamorphized semiconductor sidewalls in a lower portion of the first opening; enlarging only the lower portion of the first opening using an etch process that is selective to the unamorphized semiconductor ...

Metal-insulator-metal capacitors with high capacitance density

Patent Number: 8445355
Publication Date: 2013-05-21
Inventors: ; ;

Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor ...

Methods for manufacturing a phase-change memory device

Patent Number: 8445354
Publication Date: 2013-05-21
Inventor:

A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material ...

Method for integrating MIM capacitor and thin film resistor in modular two layer metal process and corresponding device

Patent Number: 8445353
Publication Date: 2013-05-21
Inventors: ; ;

A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer ...

Manufacturing method of semiconductor device

Patent Number: 8445352
Publication Date: 2013-05-21
Inventors: ;

A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on ...

Floating-gate nonvolatile semiconductor memory device and method of making

Patent Number: 8445351
Publication Date: 2013-05-21
Inventors: ;

The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region ...

Semiconductor device and method of manufacturing the same

Patent Number: 8445350
Publication Date: 2013-05-21
Inventor:

According to an embodiment of a semiconductor device and a method of manufacturing the same, buried gates are formed in a semiconductor substrate including a cell region and a peripheral region, with the cell region and the peripheral region formed to have a step therebetween. Next, a spacer is formed in a region between the cell region and the peripheral region to block an oxidation path between a gate oxide layer and another insulating layer. Embodiments may reduce damage to active ...

Method of manufacturing nonvolatile semiconductor memory device

Patent Number: 8445349
Publication Date: 2013-05-21
Inventor:

In one embodiment, a method of manufacturing a nonvolatile semiconductor memory includes forming a plurality of memory cell transistors and a plurality of selection transistors on a substrate. The method further includes burying first and second insulators successively between memory cell transistors and between a memory cell transistor and a selection transistor, and forming the first and second insulators successively on side surfaces of selection transistors, the side surfaces facing a ...

Manufacturing method of a semiconductor component with a nanowire channel

Patent Number: 8445348
Publication Date: 2013-05-21
Inventors: ; ;

The present invention discloses a manufacturing method of a semiconductor component with a nanowire channel. The method comprises the following steps. The step of forming a stack structure on a substrate is performed. A semiconductor layer is formed on the substrate and the stack structure and further filled into the fillister. The semiconductor layer is patterned to form a source area and a drain area, and the channel region is located between the source area and the drain area. The ...

3D vertical NAND and method of making thereof by front and back side processing

Patent Number: 8445347
Publication Date: 2013-05-21
Inventor:

Monolithic three dimensional NAND strings and methods of making. The method includes both front side and back side processing. Using the combination of front side and back side processing, a NAND string can be formed that includes an air gap between the floating gates in the NAND string. The NAND string may be formed with a single vertical channel. Alternatively, the NAND string may have a U shape with two vertical channels connected with a horizontal ...

Method of reducing wordline shorting

Patent Number: 8445346
Publication Date: 2013-05-21
Inventors: ; ;

A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer ...

CMOS structure having multiple threshold voltage devices

Patent Number: 8445345
Publication Date: 2013-05-21
Inventors: ; ; ;

A method of forming a complementary metal oxide semiconductor (CMOS) structure having multiple threshold voltage devices includes forming a first transistor device and a second transistor device on a semiconductor substrate. The first transistor device and second transistor device initially have sacrificial dummy gate structures. The sacrificial dummy gate structures are removed and a set of vertical oxide spacers are selectively formed for the first transistor device. The set of vertical ...

Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning

Patent Number: 8445344
Publication Date: 2013-05-21
Inventor:

Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and ...

Methods of fabricating semiconductor devices including semiconductor layers formed in stacked insulating layers

Patent Number: 8445343
Publication Date: 2013-05-21
Inventors: ;

Methods of fabricating a semiconductor device include alternatingly and repeatedly stacking sacrificial layers and first insulating layers on a substrate, forming an opening penetrating the sacrificial layers and the first insulating layers, and forming a spacer on a sidewall of the opening, wherein a bottom surface of the opening is free of the spacer. A semiconductor layer is formed in the opening. Related devices are also ...

Short channel semiconductor devices with reduced halo diffusion

Patent Number: 8445342
Publication Date: 2013-05-21
Inventors: ;

A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and ...