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Stackable ball grid array package

Patent Number: RE43112
Publication Date: 2012-01-17
Inventors: Moden, Walter L.; Corisis, David J.; Brooks, Jerry M.

A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted ...

Methods and systems of transferring a substrate to minimize heat loss

Patent Number: 8110511
Publication Date: 2012-02-07
Inventors: Lei, Lawrence Chung-Lai; Liu, Rex; Wu, Tzy-Chung Terry; Mak, Alfred; Park, Kon; Wang, Xiaoming; Zhu, Simon; Shin, Gene

A method of transferring one or more substrates between process modules or load lock stations while minimizing heat loss is provided. In some embodiments the method comprising the steps of: identifying a destination location D1 for a substrate S1 present at an initial processing location P1; if the destination location D1 is occupied with a substrate S2, maintaining the substrate S1 at the initial processing location P1; and if the destination ...

Low temperature synthesis of nanowires in solution

Patent Number: 8110510
Publication Date: 2012-02-07
Inventors: Korgel, Brian A.; Fanfair, Dayne D.

Methods synthesizing nanowires in solution at low temperatures (e.g., about 400° C. or lower) are provided. In the present methods, the nanowires are synthesized by exposing nanowire precursors to metal nanocrystals in a nanowire growth solution comprising a solvent. The metal nanocrystals serve as seed particles that catalyze the growth of the semiconductor nanowires. The metal nanocrystals may be formed in situ in the growth solution from metal nanocrystal precursors. Alternatively, the ...

Method of fabricating light emitting devices

Patent Number: 8110509
Publication Date: 2012-02-07
Inventors: Murakami, Masakazu; Yamazaki, Shunpei

A manufacturing apparatus is provided, which can improve a utilization efficiency of an evaporation material, reduce manufacturing costs of a light emitting device having an organic light emitting element, and shorten manufacturing time necessary to manufacture a light emitting device. According to the present invention, a multi-chamber manufacturing apparatus having plural film forming chambers includes a first film forming chamber for subjecting a first substrate to evaporation and a ...

Method of forming a bump structure using an etching composition for an under bump metallurgy layer

Patent Number: 8110508
Publication Date: 2012-02-07
Inventors: Kim, Young-Nam; Kang, Dong-Min; Kang, Bo-Ram; Lim, Young-Sam

In an etching composition for an under-bump metallurgy (UBM) layer and a method of forming a bump structure, the etching composition includes about 40% by weight to about 90% by weight of hydrogen peroxide (H₂O₂), about 1% by weight to about 20% by weight of an aqueous basic solution including ammonium hydroxide (NH₄OH) or tetraalkylammonium hydroxide, about 0.01% by weight to about 10% by weight of an alcohol compound, and about 2% by weight to 30% by ...

Method for patterning an active region in a semiconductor device using a space patterning process

Patent Number: 8110507
Publication Date: 2012-02-07
Inventor: Park, Chan Ha

Disclosed here in is a method for patterning an active region in a semiconductor device using a space patterning process that includes forming a partition pattern having partition pattern elements arranged in a square shape on a semiconductor substrate; forming a spacer on side walls of the partition pattern; removing the partition pattern; separating the spacer into first and second spacer portions to expose a portion of the semiconductor substrate; and etching the exposed portion of the ...

Methods of forming fine patterns in semiconductor devices

Patent Number: 8110506
Publication Date: 2012-02-07
Inventors: Kim, Dong-chan; Kim, Myeong-cheol; Kim, Bum-Soo; Min, Jae-Ho; Kwon, O-Ik

Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different ...

Lead frame manufactured from low-priced material and not requiring strict process control, semiconductor package including the same, and method of manufacturing the lead frame and the semiconductor package

Patent Number: 8110505
Publication Date: 2012-02-07
Inventors: Kang, Sung-il; Shim, Chang-han

Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both ...

Method of manufacturing semiconductor device

Patent Number: 8110504
Publication Date: 2012-02-07
Inventors: Kageyama, Satoshi; Nakao, Yuichi

The method of manufacturing a semiconductor device according to the present invention includes: an insulating layer forming step of forming an insulating layer made of an insulating material containing Si and O; a groove forming step of forming a groove in the insulating layer; a metal film applying step of covering the inner surface of the groove with a metal film made of MnO_x(x: a number greater than zero) by sputtering; and a wire forming step of forming a Cu wire made of a ...

Surface preparation for thin film growth by enhanced nucleation

Patent Number: 8110503
Publication Date: 2012-02-07
Inventors: Girolami, Gregory S.; Abelson, John R.; Kumar, Navneet; Yanguas-Gil, Angel

Various processes and related systems are provided for making structures on substrate surfaces. Disclosed are methods of making a structure supported by a substrate by providing a substrate having a receiving surface and exposing at least a portion of the receiving surface to output from a remote plasma of an inert gas. The remote plasma has an energy low enough to substantially avoid etching or sputtering of the receiving surface but sufficient to generate a treated receiving surface. The ...

Method of improving adhesion strength of low dielectric constant layers

Patent Number: 8110502
Publication Date: 2012-02-07
Inventor: Ang, Ting Cheong

A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma ...

Method of fabricating landing plug with varied doping concentration in semiconductor device

Patent Number: 8110501
Publication Date: 2012-02-07
Inventor: Rouh, Kyoung Bong

A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is ...

Mitigation of plating stub resonance by controlling surface roughness

Patent Number: 8110500
Publication Date: 2012-02-07
Inventors: Kim, Tae Hong; Cases, Moises; Mutnury, Bhyrav M.; Na, Nanju

Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including ...

Method of forming a contact structure

Patent Number: 8110499
Publication Date: 2012-02-07
Inventors: Hong, Chang-Ki; Kim, Young-Hoo; Lee, Jae-Dong; Lee, Kun-Tack; Kang, Dae-Hyuk; Han, Jeong-Nam; Eom, Dae-Hong

An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A ...

Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device

Patent Number: 8110498
Publication Date: 2012-02-07
Inventors: Fischer, Daniel; Leppack, Susanne; Schaller, Matthias

When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by exposing the surface to a vapor of a passivation agent. Due to the corresponding interaction with the metal surface, enhanced integrity may be accomplished, while at the same time damage of exposed dielectric surface portions may be significantly reduced compared to conventional aggressive wet chemical cleaning processes that are typically ...

Method for manufacturing semiconductor device

Patent Number: 8110497
Publication Date: 2012-02-07
Inventors: Hasunuma, Masahiko; Sakata, Atsuko; Toyoda, Hiroshi; Yamashita, Soichi; Sonoda, Yasuyuki

An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection ...

Method for performing chemical shrink process over BARC (bottom anti-reflective coating)

Patent Number: 8110496
Publication Date: 2012-02-07
Inventors: Bailey, Todd Christopher; Gabor, Allen H.; Brodsky, Colin J.

A structure and a method for forming the same. The method comprises providing a structure including (a) a hole layer, (b) a BARC (bottom antireflective coating) layer on the top of the hole layer, and (c) a patterned photoresist layer on top of the BARC layer and having a photoresist hole; etching the BARC layer through the photoresist hole to extend the photoresist hole to the hole layer; performing the chemical shrinking process to shrink the extended photoresist hole; and etching the ...

Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation

Patent Number: 8110495
Publication Date: 2012-02-07
Inventors: Masuda, Hiroshi; Domae, Shinichi; Kato, Yoshiaki; Yano, Kousaku

A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring ...

Systems and methods for maximizing breakdown voltage in semiconductor devices

Patent Number: 8110494
Publication Date: 2012-02-07
Inventors: Stewart, Eric Jonathan; McCoy, Megan Jean; McNutt, Ty Richard; Veliadis, John V.; Chen, Li-shu

Systems and methods for maximizing the breakdown voltage of a semiconductor device are described. In a multiple floating guard ring design, the spacing between two consecutive sets of floating guard rings may increase with their distance from the main junction while maintaining depletion region overlap, thereby alleviating crowding and optimally spreading the electric field leading to a breakdown voltage that is close to the intrinsic material limit. In another exemplary embodiment, ...

Pulsed PECVD method for modulating hydrogen content in hard mask

Patent Number: 8110493
Publication Date: 2012-02-07
Inventors: Fang, Zhiyuan; Subramonium, Pramod; Henri, Jon

A method for forming a PECVD deposited amorphous carbon or ashable hard mask (AHM) in a trench or a via with less than 30% H content at a process temperature below 500° C., e.g., about 400° C. produces low H content hard masks with high selectivity and little or no hard mask on the sidewalls. The deposition method utilizes a pulsed precursor delivery with a plasma etch while the precursor flow is ...

Method for connecting a die attach pad to a lead frame and product thereof

Patent Number: 8110492
Publication Date: 2012-02-07
Inventors: Calo, Paul Armand; Almagro, Erwin Ian V.; Granada, Jr., Honorio T.

Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits different styles of die attach pads and lead frames to be interchanged, thus reducing production ...

Method of manufacturing semiconductor device and substrate processing apparatus

Patent Number: 8110491
Publication Date: 2012-02-07
Inventor: Harada, Kazuhiro

A manufacturing method of a semiconductor device of the present invention includes the step of forming an insulating film on a substrate, and the step of forming a high dielectric constant insulating film on the insulating film, and the step of forming a titanium aluminum nitride film on the high dielectric constant insulating film, wherein in the step of forming the titanium aluminum nitride film, formation of an aluminum nitride film and formation of a titanium nitride film are ...

Gate oxide leakage reduction

Patent Number: 8110490
Publication Date: 2012-02-07
Inventors: Tao, Hun-Jan; Lee, Da-Yuan; Chen, Chi-Chun; Yeh, Matt

A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the ...

Process for forming cobalt-containing materials

Patent Number: 8110489
Publication Date: 2012-02-07
Inventors: Moraes, Kevin; Ganguli, Seshadri; Chu, Schubert S.; Chang, Mei; Yu, Sang-Ho; Phan, See-Eng

Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic ...

Method for increasing etch rate during deep silicon dry etch

Patent Number: 8110488
Publication Date: 2012-02-07
Inventors: Kirby, Kyle; Borthakur, Swarnal

A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks ...

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

Patent Number: 8110487
Publication Date: 2012-02-07
Inventors: Schwan, Christoph; Frohberg, Kai; Griebenow, Uwe; Ruttloff, Kerstin

By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the ...

Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer

Patent Number: 8110486
Publication Date: 2012-02-07
Inventors: Matsumoto, Koji; Hora, Tomoyuki; Ninomiya, Masaharu; Endo, Akihiko; Morita, Etsurou

A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing ...

Nanocrystal silicon layer structures formed using plasma deposition technique, methods of forming the same, nonvolatile memory devices having the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices

Patent Number: 8110485
Publication Date: 2012-02-07
Inventors: Jung, Sung wook; Choi, Byoung deog; Yi, Jun sin; Jang, Kyung soo; Cho, Jae hyun

Provided are nanocrystal silicon layer structures formed using a plasma deposition technique, methods of forming the same, nonvolatile memory devices including the nanocrystal silicon layer structures, and methods of fabricating the nonvolatile memory devices. A method of forming a nanocrystal silicon layer structure includes forming a buffer layer on a substrate and forming a nanocrystal silicon layer on the buffer layer by a plasma deposition technique using silicon (Si)-containing gas ...

Conductive nitride semiconductor substrate and method for producing the same

Patent Number: 8110484
Publication Date: 2012-02-07
Inventors: Kiyama, Makoto; Nakahata, Seiji; Sato, Fumitaka

A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 μm and arranged at a spacing of 250 to 10,000 μm; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and ...

Forming an extremely thin semiconductor-on-insulator (ETSOI) layer

Patent Number: 8110483
Publication Date: 2012-02-07
Inventors: Chatty, Kiran V.; Cummings, Jason E.; Robison, Robert R.; ; Abadeer, Wagdi W.; Tonti, William R.; Furukawa, Toshiharu; Gauthier, Robert J.; Rankin, Jr., Jed H.

Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the ...

Miscut semipolar optoelectronic device

Patent Number: 8110482
Publication Date: 2012-02-07
Inventors: Kaeding, John F.; Iza, Michael; Sato, Hitoshi; Baker, Troy J.; Lee, Dong-Seon; Haskell, Benjamin A.; Nakamura, Shuji; DenBaars, Steven P.; Speck, James S.

A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In_xGa_1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the In_xGa_1-xN ...

Method of segmenting semiconductor wafer

Patent Number: 8110481
Publication Date: 2012-02-07
Inventors: Harikai, Atsushi; Arita, Kiyoshi

To provide a method of segmenting a semiconductor wafer, which is capable of preventing chippings.

A semiconductor wafer 1 is partitioned into a circumferential ring-shaped region 1a and a segmentation region placed in the inner side of the ring-shaped region 1a. The semiconductor wafer 1 included in the segmentation region is cut into the form of a lattice along a plurality of perpendicular cutting lines 4 and is segmented into a ...

Method and structure for fabricating solar cells using a thick layer transfer process

Patent Number: 8110480
Publication Date: 2012-02-07
Inventor: Henley, Francois J.

A photovoltaic cell device, e.g., solar cell, solar panel, and method of manufacture. The device has an optically transparent substrate comprises a first surface and a second surface. A first thickness of material (e.g., semiconductor material, single crystal material) having a first surface region and a second surface region is included. In a preferred embodiment, the surface region is overlying the first surface of the optically transparent substrate. The device has an optical coupling ...

Manufacturing method of SOI substrate provided with barrier layer

Patent Number: 8110479
Publication Date: 2012-02-07
Inventor: Yamazaki, Shunpei

To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be ...

Method for manufacturing semiconductor substrate, display panel, and display device

Patent Number: 8110478
Publication Date: 2012-02-07
Inventors: Koyama, Jun; Ohnuma, Hideto; Yamazaki, Shunpei

If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single ...

Semiconductor device and method of forming high-frequency circuit structure and method thereof

Patent Number: 8110477
Publication Date: 2012-02-07
Inventors: Cao, Haijing; Chen, Kang; Fang, Jianmin; Lin, Yaojian

A semiconductor device is made by providing an integrated passive device (IPD). Through-silicon vias (TSVs) are formed in the IPD. A capacitor is formed over a surface of the IPD by depositing a first metal layer over the IPD, depositing a resistive layer over the first metal layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the resistive and dielectric layers. The first metal layer and the resistive layer are electrically connected to ...

Memory cell that includes a carbon-based memory element and methods of forming the same

Patent Number: 8110476
Publication Date: 2012-02-07
Inventors: Ilkbahar, Alper; Scheuerlein, Roy E.; Shricker, April D.

In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of ...

Method for forming a memory device with C-shaped deep trench capacitors

Patent Number: 8110475
Publication Date: 2012-02-07
Inventor: Chou, Hou-Hong

The invention is related to a memory device, including a substrate, a capacitor which is substantially C-shaped in a cross section parallel to the substrate surface and a word line coupling the capacitor. In an embodiment, the C-shaped capacitor is a deep trench capacitor, and in alternative embodiment, the C-shaped capacitor is a stack capacitor. Both inner edge and outer edge of the C-shaped capacitor can be used for providing ...

Method of making micromodules including integrated thin film inductors

Patent Number: 8110474
Publication Date: 2012-02-07
Inventors: Carobolante, Francesco; Hawks, Douglas Alan

Micromodules and methods of making them are disclosed. An exemplary micromodule includes a substrate having a thin film inductor, and a bumped die mounted on the substrate and over the thin film ...

Semiconductor device comprising multilayer dielectric film and related method

Patent Number: 8110473
Publication Date: 2012-02-07
Inventors: Choi, Hoon-sang; Kang, Sang-yeol; Chung, Eun-ae; Lee, Jong-cheol; Lim, Ki-vin

A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance ...

High power and high temperature semiconductor power devices protected by non-uniform ballasted sources

Patent Number: 8110472
Publication Date: 2012-02-07
Inventors: Hébert, François; Bhalla, Anup

A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond ...

Semiconductor device having a round-shaped nano-wire transistor channel and method of manufacturing same

Patent Number: 8110471
Publication Date: 2012-02-07
Inventors: Lee, Sungyoung; Shin, Dongsuk

A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular ...

Asymmetrical transistor device and method of fabrication

Patent Number: 8110470
Publication Date: 2012-02-07
Inventors: Chu, Sanford; Tan, Chung Foong; Toh, Eng Huat; Lee, Jae Gon

Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating ...

Graded dielectric layers

Patent Number: 8110469
Publication Date: 2012-02-07
Inventors: Srividya, Cancheepuram V.; Gealy, Dan; Bhat, Vishwanath; Rocklein, M. Noel

Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer ...

DMOS-transistor having improved dielectric strength of drain and source voltages

Patent Number: 8110468
Publication Date: 2012-02-07
Inventor: Roth, Andreas

A DMOS-transistor having enhanced dielectric strength includes a first well region. A highly doped source region is located in the first well region and is complementarily doped thereto. A highly doped bulk connection region is located in the first well region and has the same type of doping as the first well region. A gate electrode and a gate insulation layer for forming a transistor channel are included on a surface of the first well region. The DMOS-transistor further comprises an ...

Multiple Vt field-effect transistor devices

Patent Number: 8110467
Publication Date: 2012-02-07
Inventors: Chang, Leland; Mo, Renee T.; Narayanan, Vijay; Chang, Josephine B.; Sleight, Jeffrey W.

Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the ...

Cross OD FinFET patterning

Patent Number: 8110466
Publication Date: 2012-02-07
Inventors: Shieh, Ming-Feng; Lee, Tsung-Lin; Chang, Chang-Yun

A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality ...

Field effect transistor having an asymmetric gate electrode

Patent Number: 8110465
Publication Date: 2012-02-07
Inventors: Liang, Qingqing; Zhu, Huilong

The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short ...

SOI protection for buried plate implant and DT bottle ETCH

Patent Number: 8110464
Publication Date: 2012-02-07
Inventors: Ho, Herbert L.; Dyer, Thomas W.; Todi, Ravi M.

An SOI layer has an initial trench extending therethrough, prior to deep trench etch. An oxidation step, such as thermal oxidation is performed to form a band of oxide on an inner periphery of the SOI layer to protect it during a subsequent RIE step for forming a deep trench. The initial trench may stop on BOX underlying the SOI. The band of oxide may also protect the SOI during buried plate implant or gas phase ...

Method of fabricating semiconductor device

Patent Number: 8110463
Publication Date: 2012-02-07
Inventors: Shimada, Satoru; Otake, Seiji; Takeda, Yasuhiro

A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in ...