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Variable gain amplifier circuit and filter circuit

Patent Number: 8111096
Publication Date: 2012-02-07
Inventor: Oishi, Kazuaki

This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between ...

Temperature compensation for internal inductor resistance

Patent Number: 8111095
Publication Date: 2012-02-07
Inventors: Carr, Frank; Bult, Klaas; Vorenkamp, Pieter

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed ...

Analog multiplexer circuits and methods

Patent Number: 8111094
Publication Date: 2012-02-07
Inventor: Fischer, Jonathan H.

A sample and hold circuit is disclosed that provides longer hold times. An analog multiplexer circuit is also disclosed that exhibits low switch leakage. The analog multiplexer circuit comprises a shared node, a plurality of input circuits, a control input for selecting one or more of the plurality of input circuits, and an amplifier coupled to the shared node. Each input circuit comprises an input node, a primary input switch for selectively coupling an input to the input node, and a ...

Power supply noise rejection in PLL or DLL circuits

Patent Number: 8111093
Publication Date: 2012-02-07
Inventors: Poulton, John Wood; Greer, III, Thomas H.

A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency ...

Register with process, supply voltage and temperature variation independent propagation delay path

Patent Number: 8111092
Publication Date: 2012-02-07
Inventors: Rombach, Gerd; Tambouris, Sotirios

A digital data register is disclosed that provides setup and hold timing on the pre-register side, clock centering on the post-register side, and constant propagation delay time over variations in process, supply voltage and temperature (PVT) using a novel means to generate and distribute the clock signal. These features allow the register to be used in applications operating at clock frequencies in excess of 800 ...

High speed track and hold circuit

Patent Number: 8111091
Publication Date: 2012-02-07
Inventor: Glass, Kevin William

Examples of systems and methods are provided for tracking-and-holding an input signal. The system may produce a pair of differential voltage outputs responsive to a pair of differential voltage inputs. The system may couple, in response to a clock signal, an input amplifier circuit to an output circuit or decouple the input amplifier circuit from the output circuit. The system may couple the input amplifier to an electrical ground. The system may track values of a pair of differential ...

Voltage comparator having improved kickback and jitter characteristics

Patent Number: 8111090
Publication Date: 2012-02-07
Inventors: Gebara, Fadi H.; Schaub, Jeremy D.

A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and ...

Curvature compensated bandgap voltage reference

Patent Number: 8106707
Publication Date: 2012-01-31
Inventors: Rutherford, Mark; Katyal, Vipul

Embodiments of the present invention include systems and methods for generating a curvature compensated bandgap voltage reference. In an embodiment, a curvature compensated bandgap reference voltage is achieved by injecting a temperature dependent current at different points in the bandgap reference voltage circuit. In an embodiment, the temperature dependent current is injected in the proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) current ...

DC biasing circuit for a metal oxide semiconductor transistor

Patent Number: 8106706
Publication Date: 2012-01-31
Inventors: Mathur, Sumeet; Easwaran, Prakash; Bhowmik, Prasenjit

A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. ...

Control circuit for PVT conditions of a module

Patent Number: 8106705
Publication Date: 2012-01-31
Inventor: Negoi, Andy C.

The electronic circuit comprises a functional module (10), a condition signaling module (20), a reference module (30) and a control circuit (40). The condition signaling module (20) generates an indication signal (Imeas) indicative for PVT conditions local to the functional module. The PVT conditions comprise a set of conditions relevant for a module comprising at least one of a voltage supplied to said module, a temperature within an area occupied by said ...

Apparatus and method for preventing excessive increase in pumping voltage when generating pumping voltage

Patent Number: 8106704
Publication Date: 2012-01-31
Inventor: Kim, Myung Jin

A device for generating a pumping voltage and preventing an excessive increase in the pumping voltage includes a pumping voltage output unit that outputs a pumping voltage and adjusts the level of the pumping voltage in order to maintain a target voltage. The level of the pumping voltage is adjusted in response to a change in the level of the pumping unit. A release unit is included to detect an excessive pumping voltage. The release unit adjusts the level of the pumping voltage when the ...

Booster circuit

Patent Number: 8106703
Publication Date: 2012-01-31
Inventors: Amanai, Masakazu; Kashimura, Masahiko; Nagai, Yoshihiro; Honda, Norihiro; Yamanaka, Kazushi; Taki, Masato

Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or ...

Dynamic enabling pump for power control

Patent Number: 8106702
Publication Date: 2012-01-31
Inventor: Jurasek, Ryan Andrew

A voltage generation system that can dynamically calibrate a time period for enabling the system includes: a voltage generation circuit, for providing an output voltage; an oscillator, coupled to the voltage generation circuit, for driving the voltage generation circuit to generate the output voltage at a specific frequency according to an enable signal; a limiter, coupled to the oscillator and the output voltage fed back from the voltage generation circuit, for generating the enable signal ...

Level shifter with shoot-through current isolation

Patent Number: 8106701
Publication Date: 2012-01-31
Inventors: Pan, Feng; Pham, Trung; Nguyen, Qui Vi; Huynh, Jonathan Hoang

A level shifter circuit suitable for high voltage applications with shoot-through current isolation is presented. The level shifter receives a first enable signal and receives an input voltage at a first node and supplies an output voltage at a second node. The circuit provides the output voltage from the input voltage in response to the first enable signal being asserted and sets the output node to a low voltage value when the first enable signal is de-asserted. The level shifting circuit ...

Wideband voltage translators

Patent Number: 8106700
Publication Date: 2012-01-31
Inventors: Lloyd, Jennifer; Tam, Kimo Y. F.

In embodiments of the present invention, the problems of poor low-frequency response, slow speed, high cost and high power consumption in conventional voltage translators are addressed by processing high frequency and low frequency components of an input signal separately in two parallel stages without the use of large passive components or slow devices. At the output, the processed high frequency and low frequency components are seamlessly merged at a combining stage that maintains the ...

High signal level compliant input/output circuits

Patent Number: 8106699
Publication Date: 2012-01-31
Inventors: Shankar, Vijay; Srinivas, Vaishnav; Gupta, Abheek; Mohan, Vivek

A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level ...

Pulse-based flip-flop having scan input signal

Patent Number: 8106698
Publication Date: 2012-01-31
Inventor: Kim, Min-Su

A flip-flop for transmitting a scan input and data for scan-testing a semiconductor circuit is provided. The flip-flop includes a first pulse signal generator which generates a first pulse signal in response to a scan enable signal and an inversed scan input signal. A second pulse signal generator generates a second pulse signal in response to the scan enable signal and a scan input signal. A signal transmitter receives a data signal and transmits the data signal to a first node in response ...

Circuit and method for providing a corrected duty cycle

Patent Number: 8106697
Publication Date: 2012-01-31
Inventors: Chang, Chien Yi; Huang, Ming Chien

A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit ...

Duty ratio correction circuit and duty ratio correction method

Patent Number: 8106696
Publication Date: 2012-01-31
Inventor: Kikuchi, Kazutaka

A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock signal, a data input buffer that receives a first data signal, a data duty adjuster that adjusts a duty ratio of a second data signal output from the data input buffer based on the correction signal and generates a third data ...

Semiconductor device

Patent Number: 8106695
Publication Date: 2012-01-31
Inventor: Miyano, Kazutaka

A semiconductor device which has a duty detection circuit that detects a duty error in an internal clock synchronized with an external clock and is capable of performing accurate duty measurement. A first capacitor is coupled to a first node and a first current source coupled to a second node. A first switch is coupled between the first and second nodes. A second switch is coupled between a voltage line and the first node and a third switch is coupled between the voltage line and the second ...

DLL circuit

Patent Number: 8106694
Publication Date: 2012-01-31
Inventor: Kim, Tae Kyun

A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the ...

Delay locked loop circuit and operation method thereof

Patent Number: 8106693
Publication Date: 2012-01-31
Inventor: Lee, Hye-Young

A delay locked loop circuit includes a delay replica model unit for reflecting a delay time of an actual output path to a source clock and outputting the reflected source clock as a delay replica clock, a detector for detecting a remaining time after subtracting a time corresponding to a multiple of a clock cycle of the source clock from a time corresponding to a phase difference between the delay replica clock and the source clock, and a delay locking unit for delaying the source clock for ...

Method for tracking delay locked loop clock

Patent Number: 8106692
Publication Date: 2012-01-31
Inventor: Chen, Chung-Zen

A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay ...

Phase adjustment circuit

Patent Number: 8106691
Publication Date: 2012-01-31
Inventors: Kinoshita, Masayoshi; Yamada, Yuji; Sogawa, Kazuaki

In a phase adjustment circuit that divides the frequency of a double-frequency clock to obtain a 50% duty-cycle clock, a first ½ frequency division circuit having a phase inversion function generates an intermediate reference clock apart in phase from both a phase reference clock and a phase-adjusted clock. A first phase control circuit controls the phase of the intermediate reference clock to be in a desired phase state with respect to the phase reference clock. A second phase control ...

Semiconductor integrated circuit device

Patent Number: 8106690
Publication Date: 2012-01-31
Inventors: Sakaguchi, Jiro; Ota, Moriyoshi

To generate a highly accurate SSC while reducing the circuit area of a clock generation circuit that generates a normal clock and an SSC. A clock signal output from a voltage controlled oscillator is frequency-divided by a frequency divider, and is output as a first frequency-divided clock to a selector. The frequency divider outputs a plurality of second frequency-divided clocks each shifted in phase by 1/m of a period based on a control signal of a control circuit. The selector selects ...

Circuit for generating power-up signal of semiconductor memory apparatus

Patent Number: 8106689
Publication Date: 2012-01-31
Inventor: Rho, Kwang-Myoung

A power-up signal generating circuit of a semiconductor memory apparatus includes a current source unit configured to supply a current to a first node; a current sink unit configured to be turned on when the level of a divided voltage dividing an external voltage is equal to or higher than a predetermined level to allow the current to flow from a first node to a second node; a control unit configured to control the turn-on timing of the current sink unit by controlling a voltage level of ...

Power-on-reset circuit with brown-out reset for multiple power supplies

Patent Number: 8106688
Publication Date: 2012-01-31
Inventors: Huang, Haitao; Zhang, Min; Yin, Liding

A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source ...

Spread spectrum clock system and spread spectrum clock generator

Patent Number: 8106687
Publication Date: 2012-01-31
Inventor: Chang, Keng-Yu

A spread spectrum clock generator includes a triangular wave generator, a digital wave modulator, a sigma delta modulator, and a selector. The triangular wave generator transforms one of the input clock signals into an original triangular wave signal, in which the input clock signals have the same frequency and phases different from each other. The digital wave modulator adjusts the waveform of the original triangular wave signal to generate an adjusted triangular wave signal and a first ...

Integrated circuit

Patent Number: 8106686
Publication Date: 2012-01-31
Inventors: Schneider, Helmut; Roth, Harald

An integrated circuit includes an input terminal for applying an input signal, a further input terminal for applying a further input signal having a level differing from the level of the initial input signal, an output terminal for providing an output signal, a switching unit having a controllable switch, which is arranged between the input terminal and the output terminal, and a further switching unit, which is arranged between the further input terminal and the output terminal. The ...

Signal receiver and voltage compensation method

Patent Number: 8106685
Publication Date: 2012-01-31
Inventor: Cheng, Wen-Chang

A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the ...

High-speed low-voltage differential signaling system

Patent Number: 8106684
Publication Date: 2012-01-31
Inventors: Takeuchi, Hiroshi; Yokoshima, Hideki; Kondo, Yuya

A system and a method for communicating data at a rate exceeding about a gigabit per second is described. The system may include circuitry and a current-sourcing module. The circuitry may include an output couplable to a load. The circuitry may output from the output a low voltage differential signal having a first current that drives the load from a first voltage at a first time to a second voltage at a second time. The current-sourcing module may apply a second current to the output at a ...

Reference circuit and method for providing a reference

Patent Number: 8102201
Publication Date: 2012-01-24
Inventor: Marinca, Stefan

A reference circuit configured to provide a reference value. The circuit includes a first circuit unit which is configured to provide a first electrical representation that varies linearly with temperature and has a crossover point where its polarity relative to zero changes from a negative value to a positive value. A second circuit unit is configured to provide a second electrical representation that varies linearly with temperature. The first and second circuit units are operable for ...

Current control circuit

Patent Number: 8102200
Publication Date: 2012-01-24
Inventor: Araki, Norihiko

A current control circuit in accordance an exemplary aspect of the present invention includes a first transistor that controls a current flowing to a load, a first resistor through which a current flows according to a current flowing through the first transistor, a control signal generation circuit that generates a control signal used to control the first transistor based on a comparison voltage and a predetermined reference voltage, the comparison voltage being determined based on a ...

Ultra-low voltage level shifting circuit

Patent Number: 8102199
Publication Date: 2012-01-24
Inventors: Chen, Yen-Huei; Wu, Jui-Jen; Chou, Shao-Yu

A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a first blocking device coupled between the drain of the first ...

Relay circuit, information processing apparatus, and relay method

Patent Number: 8102198
Publication Date: 2012-01-24
Inventor: Ogura, Yoshinari

A relay circuit for relaying signal transmission between a first circuit driven by a first voltage and a second circuit driven by a second voltage different from the first voltage, the relay circuit includes: a waveform shaping circuit that obtains a shaped voltage by shaping a waveform of the second voltage in order to make a change of the second voltage steeper; and a buffer circuit that is driven by the first voltage and interrupts a signal transmission by the buffer circuit if the ...

Digital phase locked loop

Patent Number: 8102197
Publication Date: 2012-01-24
Inventors: Chao, Chieh-Yuan; Yu, Shu-Sun; Zhang, Weicheng; Shi, Ming; Zou, Wei-Hua

An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO ...

Programmable dual phase-locked loop clock signal generator and conditioner

Patent Number: 8102196
Publication Date: 2012-01-24
Inventor: Zhang, Benyong

A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module and an on-chip VCO with intra-PLL frequency doubling to provide a clock signal with reduced in-band phase noise and RMS jitter. As desired, synchronization between the input and output clocks can also be ...

Digital phase-locked loop circuit including a phase delay quantizer and method of use

Patent Number: 8102195
Publication Date: 2012-01-24
Inventor: Wu, I-chang

A phase locked loop circuit in accordance with an embodiment implements a digital phase delay quantizer to replace the analog charge-pump and phase frequency detector in an analog PLL circuit. Therefore, the built-in loop filter can be a compact-sized, high order, high bandwidth, and high attenuation digital filter as well. The digital PLL circuit takes advantage of the deep sub-micron process technology which features high speed, high resolution, compact size, and low ...

Dual frequency divider having phase-shifted inputs and outputs

Patent Number: 8102194
Publication Date: 2012-01-24
Inventors: Gebara, Fadi H.; Mathews, Abraham; Kuang, Jente B.

A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two ...

Current sensing circuit

Patent Number: 8102193
Publication Date: 2012-01-24
Inventors: Jang, Jung-Ah; Ha, Chang-Woo

A current sensing circuit includes a power transistor, a sensing transistor configured to copy a current flowing through the power transistor at a predetermined ratio, a current sensing resistor configured to detect a voltage from the current copied by the sensing transistor, an input resistor configured to convert an input voltage to a current, a cross self-biasing cascade block configured to adjust currents at both ends of the input resistor, and a common gate transistor and a reference ...

DC brushed motor drive with circuit to reduce di/dt and EMI, for MOSFET Vth detection, voltage source detection, and overpower protection

Patent Number: 8102192
Publication Date: 2012-01-24
Inventors: Thevenet, Kevin; Mourrier, Andre

A gate driver for performing gate shaping on a first transistor of having gate, source, and drain terminals, the first transistor being selected from a switching stage of a power switching circuit having high- and low-side transistors series connected at a switching node for driving a load. The gate driver includes the following steps: upon receipt of an ON pulse pre-charging the gate terminal until gate to source terminal voltage equals Vth, controlling the di/dt(ON) flowing in the first ...

Window comparator circuit for limiting input voltage applied to object circuit

Patent Number: 8102191
Publication Date: 2012-01-24
Inventors: Miki, Takeshi; Satake, Hiroyuki

Plurality of current mirror circuits CM1 to CM5 at which the same amount of current I1 flows in the circuits. Transistors Qa4/Qb5 are ON state when it is in the steady state. Transistors Qa5/Qb7 turn ON and transistors Qb6/Qa6 turn OFF when a voltage generation circuit 3 applies a voltage more than predetermined value V12 to node N3. Therefore node N3 becomes fixed voltage V12. On the other ...

Open-drain output buffer for single-voltage-supply CMOS

Patent Number: 8098090
Publication Date: 2012-01-17
Inventor: Le, Hung Pham

An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching ...

Voltage booster

Patent Number: 8098089
Publication Date: 2012-01-17
Inventors: Bitonti, Davide; Castaldo, Andrea; Foschini, Angela

A voltage booster for generating a boosted voltage, including a charge pump adapted to generate the boosted voltage starting from a supply voltage by a transfer of electric charge controlled by at least one oscillating signal having an oscillation frequency; an oscillator for providing the oscillating signal; and a regulation circuit arranged to receive and perform a comparison of a voltage related to the boosted voltage and a reference voltage, and adapted to provide at least one ...

High-voltage switch using three FETS

Patent Number: 8098088
Publication Date: 2012-01-17
Inventors: Sutandi, Agustinus; Wong, Yanyi L.

Switch circuits are disclosed, for providing a single-ended and a differentially switched high-voltage output signals by switching a high supply voltage in response to at least one logic-level control signal. The switch that provides the single-ended switched high-voltage output signal includes a chain of at least three serially coupled field effect transistors (FETs). The chain receives the high supply voltage and switches it to output the high-voltage output signal. The switch that ...

Method and apparatus for standby voltage offset cancellation

Patent Number: 8098087
Publication Date: 2012-01-17
Inventors: Zaliznyak, Arch; Lai, Tin H.; Wong, Wilson; Lee, Chong H.; Shumarayev, Sergey; Lam, John Dung-Ngoc

A method and apparatus is provided for standby voltage offset cancellation at inputs to a comparator within a receiver channel. Each of a first comparator input and second comparator input is isolated from an input signal such that each of the first and second comparator inputs attains a respective standby voltage level. A voltage level on one of the first and second comparator inputs is incrementally changed, while the output signal of the comparator is monitored. Upon detecting a state ...

Integrated circuit and programmable delay

Patent Number: 8098086
Publication Date: 2012-01-17
Inventor: Szczypinski, Kazimierz

Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be ...

Time-to-digital converter (TDC) with improved resolution

Patent Number: 8098085
Publication Date: 2012-01-17
Inventors: Wang, Kevin H.; Bossu, Frederic; Palakurty, Saru

A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to ...