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		    <title>PatentStorm -&gt; Patents -&gt; Miscellaneous active electrical nonlinear devices, circuits, and systems</title>
		    <link>http://www.patentstorm.us/rss/class/patents/rss-327.xml</link>
		    <description>Recent patents filings in USPTO Class 327 Miscellaneous active electrical nonlinear devices, circuits, and systems.</description>
		    <pubDate>Tue, 21 May 2013 16:08:46</pubDate>
		    <managingEditor>patents@patentstorm.us</managingEditor>
		    <language>en</language><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="self" type="application/rss+xml" href="http://feeds.feedburner.com/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems" /><feedburner:info uri="patentstorm-patents-miscellaneousactiveelectricalnonlineardevicescircuitsandsystems" /><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="hub" href="http://pubsubhubbub.appspot.com/" /><item>
			         <title><![CDATA[Constant voltage circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/6ULyK7dNTX4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446215&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A constant voltage circuit is disclosed that includes an output control transistor and an overcurrent protection circuit. The overcurrent protection circuit includes a proportional current generation circuit part, a current division circuit part, a division ratio control circuit part, a current-voltage conversion circuit part, and an output current control circuit part. When the output voltage of the current-voltage conversion circuit part reaches a predetermined voltage, the output current ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/6ULyK7dNTX4" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Semiconductor device and method of controlling the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/jXaTOMGsnDA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446214&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V&lt;sub&gt;2 &lt;/sub&gt;from a first voltage V&lt;sub&gt;1&lt;/sub&gt;; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/jXaTOMGsnDA" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Charge pump circuit, control method thereof, and semiconductor integrated circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/Y7DoXVCrMzc/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446213&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;There is provided a charge pump circuit suited for reducing the power consumption. A capacitor &lt;b&gt;201&lt;/b&gt;&lt;i&gt;a&lt;/i&gt;, a capacitor &lt;b&gt;201&lt;/b&gt;&lt;i&gt;b&lt;/i&gt;, a capacitor &lt;b&gt;201&lt;/b&gt;&lt;i&gt;c&lt;/i&gt;, and switching elements &lt;b&gt;202&lt;/b&gt;&lt;i&gt;a &lt;/i&gt;to &lt;b&gt;202&lt;/b&gt;&lt;i&gt;k&lt;/i&gt;, for electrically connecting or separating capacitors &lt;b&gt;201&lt;/b&gt;&lt;i&gt;a&lt;/i&gt;&lt;b&gt;, 201&lt;/b&gt;&lt;i&gt;b&lt;/i&gt;, and &lt;b&gt;201&lt;/b&gt;&lt;i&gt;c&lt;/i&gt;, repeats: a first state where charge supplied from an input power-supply voltage V&lt;sub&gt;DD &lt;/sub&gt;is accumulated in the capacitors ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/Y7DoXVCrMzc" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Pulse generator having an efficient fractional voltage converter and method of use]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/AN2g4VslVy4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446212&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Disclosed are systems and methods which provide voltage conversion in increments less than integer multiples of a power supply (e.g., battery) voltage. A representative embodiment provides power supply voltage multipliers in a binary ladder distribution to provide a desired number of output voltage steps using a relatively uncomplicated circuit design. By using different sources in various combinations and/or by “stacking” different sources in various ways, the voltage multiplier ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/AN2g4VslVy4" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Internal voltage generation circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/sIQaVu4p-HM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446211&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An internal voltage generation circuit includes a first detection unit, a second detection unit, a control unit, and a voltage pumping unit. The first detection unit compares an internal voltage with a first reference voltage to generate a first detection signal when the first detection unit is activated in response to a first enable signal. The second detection unit compares the internal voltage with a second reference voltage to generate a second detection signal. The control unit ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/sIQaVu4p-HM" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Electronic fuse system]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/lX6rDXkEnJM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446210&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used for receiving a reference voltage. The electronic fuse circuit is used for changing a voltage level when a current signal passes. The first switch circuit is coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit to be disabled or enabled according to a switch control signal. The control circuit, coupled to the first ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/lX6rDXkEnJM" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Semiconductor device and method of forming same for temperature compensating active resistance]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/kPvYYBjvpeM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446209&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;In an embodiment a circuit provides an active resistance that is adjusted with temperature, the active resistance has a magnitude and temperature coefficient that is selected by the values of external resistors. The active resistance is controlled by an active resistance controller that uses a temperature dependent source and a temperature stable source to control adjustment of a first adjustable resistance to maintain correspondence between a temperature dependent parameter and a ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/kPvYYBjvpeM" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Circuit arrangement with temperature compensation]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/Meb1Exphl7s/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446208&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A circuit arrangement having at least one analog switch, which is operated by a supply voltage and which comprises a switching signal contact and a pair of switch contacts, whereby applied to the switching signal contact is an electrical switching signal depending on which an electrical connection can be switched between the switch contacts whose internal on-resistance is temperature dependent, whereby the circuit arrangement has in the vicinity of the at least one analog switch at least ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/Meb1Exphl7s" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446208/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Load driving circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/plDK3cQKoMM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446207&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A load driving circuit in which the off-time Toff and the fall time Tf can be improved in turn-off operation of the N-channel type MOSFET used as a high side switch. The load driving circuit uses an N-channel type power MOSFET as a high side switch connected between a power supply and a load, including a comparator circuit for comparing a gate voltage of the power MOSFET with a power-supply voltage; and a shut-off circuit for discharging the gate terminal of the power MOSFET in turn-off ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/plDK3cQKoMM" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446207/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Current balancing of parallel connected semiconductor components]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/iPUc-OpX3O4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446206&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A method and an arrangement are provided for balancing the switching transient behavior of parallel connected power semiconductor components. The method includes providing a switch signal to the parallel connected power semiconductor components for changing the state of the components, forming control signals for each of the parallel connected components from the switch signal, and determining, during the change of state of the power semiconductor component, the voltage induced to an ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/iPUc-OpX3O4" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446206/description.html</feedburner:origLink></item>
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			         <title><![CDATA[Mixer circuit and method for adjusting common voltage of mixer circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/R4rJyBvQaKc/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446205&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A mixer circuit includes: a mixer circuit including a first transistor pair to output a first differential input signal and a second transistor pair to output a second differential input signal by inversing the first differential signal; a local signal supply circuit to supply a pair of local signals to gates of the first transistor pair and the second transistor pair; an operational amplifier including an input pair coupled to an output pair of the mixer circuit and an output pair coupled ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/R4rJyBvQaKc" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[High voltage tolerant receiver]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/VY_utNKrs1I/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446204&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/VY_utNKrs1I" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Current controlled fast low-side clamp]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/q8FpnnrIL7M/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446203&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A low side clamp circuit has a control portion, a sense portion, and a clamp portion. When the sense portion detects that the input voltage of an output stage of a buffer has gone below a threshold voltage, it triggers the control portion to quickly turn on a clamp transistor (in the clamp portion) to clamp the output voltage to the clamp voltage. The control portion and sense portion have cross-coupled transistors that create increased speed and a sharp response with little or no voltage ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/q8FpnnrIL7M" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Power limiting circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/imcaO682owA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446202&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A power limiting circuit includes: a maximum value prediction filter section (MVPFS) interpolating data of one branched digital input signal; a maximum value detection section detecting maximum value of an output of the MVPFS and a time detection position thereof every constant period; a threshold subtraction section subtracting a threshold from detected maximum value and outputting a peak signal (zero when the subtraction result is negative); a coefficient selection section weighting the ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/imcaO682owA" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[High speed rail to rail phase splitter for providing a symmetrical differential output signal having low skew]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/PyRRyCrCVLs/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446201&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A novel high-speed phase splitter circuit (&lt;b&gt;100&lt;/b&gt;) and method of operation are disclosed. This high-speed phase splitter (&lt;b&gt;100&lt;/b&gt;) creates a differential rail-to-rail output signal from a single ended input signal, with an inherent low skew and symmetrical output. The circuit (&lt;b&gt;100&lt;/b&gt;) uses a phase splitting input stage (&lt;b&gt;110, 130&lt;/b&gt;) followed by several amplification stages (&lt;b&gt;150, 170&lt;/b&gt;) that are symmetrical and balanced in ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/PyRRyCrCVLs" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Systems and methods for a continuous, linear, 360-degree analog phase shifter]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/gj2YWwK5OsY/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446200&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Embodiments of the invention may be directed to a continuous analog phase shifter for radio frequency (RF) signals, which can be integrated on a CMOS process or another compatible process where inherent process-dependent passive components such as inductors and capacitors may have low quality factors. Insertion loss degradation for a given amount of phase shift may be compensated by using an active compensation circuit/device that smartly controls negative resistance generated from the ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/gj2YWwK5OsY" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Duty cycle correction circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/_KNw-eN6xeg/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446199&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/_KNw-eN6xeg" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446199/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Phase interpolator and a delay circuit for the phase interpolator]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/0SYBu2yCRAk/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446198&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/0SYBu2yCRAk" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446198</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446198/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Delay locked loop and method for driving the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/k1y6jFysou4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446197&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A delay locked loop includes a delay pulse generation unit, a coding unit, and a delay line. The delay pulse generation unit is configured to generate a delay pulse having a certain width. The coding unit is configured to code the delay pulse and output a code value. The delay line is configured to delay an input clock by the code value, and generate a delayed locked clock. The delay pulse has a logic high level state during a third period equivalent to a difference between a first period, ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/k1y6jFysou4" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446197</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446197/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Input interface circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/Y6KEKnCFZiY/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446196&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/Y6KEKnCFZiY" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446196</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446196/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Strobe signal management to clock data into a system]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/Vtnh9Z76_bE/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446195&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the source synchronous device. Pulses in the strobe signal can be counted. Responsive to detecting a last pulse of the expected number of pulses of the strobe signal, the strobe signal can be replaced with a reference signal that is ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/Vtnh9Z76_bE" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446195</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446195/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Spread spectrum clock generating circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/7OMb9m6aTE8/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446194&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Provided is a spread spectrum clock generating circuit. The spread spectrum clock generating circuit includes: a phase detector receiving a reference frequency signal from the external and detecting a phase difference between the reference frequency signal and a frequency-divided signal; a voltage controlled oscillator outputting an oscillation signal corresponding to a detection result of the phase detector; a main divider generating the frequency-divided signal by dividing a frequency of ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/7OMb9m6aTE8" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446194</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446194/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Apparatus and method to hold PLL output frequency when input clock is lost]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/7S1xbD5nilM/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446193&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/7S1xbD5nilM" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446193</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446193/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[PLL circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/RFkEMPe1afQ/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446192&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuit &lt;b&gt;3&lt;/b&gt; provides a frequency division ratio table &lt;b&gt;32&lt;/b&gt; where frequency division ratios to improve spurious output characteristics in the output of a VCO for each channel number at temperatures are stored, and the control circuit reads, from ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/RFkEMPe1afQ" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446192</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446192/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Phase locked loop with digital compensation for analog integration]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/ERhQKCMem-U/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446191&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A phase locked loop (PLL) device includes a digital differentiator configured to differentiate a digital loop signal to at least partially compensate for the integration of an analog current signal by an analog integrator. A digital to analog converter (DAC) includes a current source output stage that generates the analog current signal based on an digital input signal. The analog integrator integrates the analog current signal to generate a voltage control signal for controlling a voltage ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/ERhQKCMem-U" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446191</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446191/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Frequency divider, frequency synthesizer and application circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/e0YxNcrxBbA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446190&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/e0YxNcrxBbA" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446190</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446190/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Power-on reset circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/uQK7_rm_wAo/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446189&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/uQK7_rm_wAo" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446189</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446189/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Systems and methods for producing a predetermined output in a sequential circuit during power on]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/hqIxAXhBZWA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446188&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/hqIxAXhBZWA" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446188/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Apparatus and method for power-on reset circuit with current comparison]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/5nvQInvGc98/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446187&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A power-on reset (POR) circuit is provided. The POR circuit includes a first current source, a second current source, and a current comparator. The first current source is arranged to provide a relatively supply-independent circuit. The second current source is arranged to provide a supply-dependent current. The current comparator is arranged to compare the relatively supply-independent circuit with the relatively supply-dependent current to provide a POR ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/5nvQInvGc98" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446187/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Time-shared latency locked loop circuit for driving a buffer circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/PBQf7_bO1WA/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446186&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/PBQf7_bO1WA" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446186</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446186/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Load driving device]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/MaQ5dHBG4e8/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446185&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A load driving device includes a power supply terminal, a ground terminal, an output terminal coupled to a load, an output transistor coupled between the power supply and output terminals, a driver circuit supplying a first control signal to turn on the output transistor and a second control signal to turn off the output transistor, a discharge circuit coupled between the control terminal of the output transistor and the output terminal, a compensation circuit that turns on when a potential ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/MaQ5dHBG4e8" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446185/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Mode dependent driving of the center tap in ethernet communications]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/w0D3EBasLBc/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446184&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An output stage comprising a current mode line driver, a voltage mode line driver, and a center-tapped transformer for coupling data provided by the line drivers to a transmission line is provided herein. The output stage is configured to operate in a backwards compatible Ethernet communication device. For example, the Ethernet communication device is configured to support 10G Ethernet and legacy Ethernet modes of 10BASE-T, 100BASE-T, and 1000BASE-T. The current mode line driver can be ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/w0D3EBasLBc" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446184/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[High current emitter drive unit cell]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/Njn4BWQSEwY/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446183&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A unit cell for a Read-In Integrated Circuit employs a signal sampling circuit with a voltage input controlled by a first switch, a capacitor charged by the voltage input and a linear amplifier connected to the capacitor. An output through a second switch samples the capacitor as the input signal for a transistor cascade for emitter current supply incorporating a first transistor receiving the input signal and a second transistor serially connected to the first transistor with a parallel ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/Njn4BWQSEwY" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446183</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446183/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[TX output combining method between different bands]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/MYRLUE7DrqQ/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446182&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/MYRLUE7DrqQ" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8446182</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8446182/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Sampling circuit and image signal amplifying circuit each including feedback clamp block and image sensor including the image signal amplifying circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/EFC1Zf1su-s/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446181&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A sampling circuit samples an input signal by using at least one switch, at least one capacitor, an amplifier, and a clamp block connected between an output terminal and a negative input terminal of the amplifier. The clamp block prevents a difference between a voltage level of the output terminal of the amplifier and a voltage level of the negative input terminal of the amplifier during sampling from exceeding a maximum voltage ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/EFC1Zf1su-s" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Semiconductor device]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/PCI36Zm0oQc/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446180&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A disclosed semiconductor device includes an input terminal, a power line, a pnp-bipolar transistor connected to the power line, a first resistor connecting an emitter of the transistor to the input terminal, a second resistor connecting a collector of the transistor to ground, an operation circuit operable when the input voltage is a predetermined voltage or higher, the predetermined voltage being set within a first voltage region in which the input voltage cannot turn on the transistor, a ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/PCI36Zm0oQc" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446180/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Start signal detector circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/Mjo-QQyKtuU/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446179&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A non-linear effect of a rectifier element is enhanced, an input amplitude is increased by further taking advantage of a resonance circuit, and a rectification efficiency of a rectifier circuit for detection is improved, so that the gain of an amplifier circuit at a latter stage can be set low. RF input terminals &lt;b&gt;101, 102&lt;/b&gt; are applied with signals at phases opposite to each other. A signal at terminal &lt;b&gt;102&lt;/b&gt; is applied to a gate of transistor M&lt;b&gt;1&lt;/b&gt; through capacitor C&lt;b&gt;3&lt;/b&gt;, ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/Mjo-QQyKtuU" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8446179/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Comparator and analog-to-digital]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/kx1UUSH_g5s/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8446178&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-21&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A comparator includes: a pre-amplification module, configured to generate two amplified differential signal reference currents according to an input voltage and a reference voltage; and a differential signal obtaining module, configured to obtain a differential signal according to the two amplified differential signal reference currents. The pre-amplification module includes a differential unit, an offset unit, and an amplification unit, where the differential unit is configured to generate ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/kx1UUSH_g5s" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Configurable clock network for programmable logic device]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/B6qBtYl7DqI/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441314&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/B6qBtYl7DqI" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8441314</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8441314/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Current-mode analog baseband apparatus]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/R_SOB9k9ffE/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441313&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; ; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/R_SOB9k9ffE" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8441313</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8441313/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Reference current generating circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/UvxFHnCyHyQ/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441312&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A reference current generating circuit has: first and second current mirror circuits and first and second output terminals. The first current mirror circuit has: a first transistor of a first polarity being an input-side transistor; and a first resistor connected between a gate of the first transistor and a power supply terminal. The second current mirror circuit has a second transistor of a second polarity being an input-side transistor. An output node of the first current mirror circuit ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/UvxFHnCyHyQ" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Voltage regulation circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/0G0g9UbPKoI/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441311&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A voltage regulation circuit includes: a first voltage divider that divides a regulation voltage with a predetermined division ratio to generate a division voltage; a first current driving force control unit configured to compare a reference voltage with the division voltage and generate a first control signal; a current driving unit configured to generate a driving current with a variable driving force based on the first control signal and a second control signal, and generate the ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/0G0g9UbPKoI" height="1" width="1"/&gt;</description>
			         
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			      <feedburner:origLink>http://www.patentstorm.us/patents/8441311/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Power control based on dual loop with multiple process detection circuits]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/bQAEJsUqyXI/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441310&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;According to an example embodiment, an apparatus for controlling a power supply voltage for an integrated circuit may be provided, which may include a plurality of different types of process region detection circuits, each process region detection circuit configured to identify a respective process region of a plurality of process regions. The apparatus may also include a voltage selection circuit configured to determine a highest voltage among the voltages associated with the identified ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/bQAEJsUqyXI" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8441310</guid>
			
			      <feedburner:origLink>http://www.patentstorm.us/patents/8441310/description.html</feedburner:origLink></item>
<item>
			         <title><![CDATA[Temperature independent reference circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/eui_Y8zK7B4/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441309&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R&lt;b&gt;1&lt;/b&gt; and R&lt;b&gt;2,&lt;/b&gt; and third and second temperature coefficients, TC&lt;b&gt;3&lt;/b&gt; and TC&lt;b&gt;2,&lt;/b&gt; respectively. The resistance values being such that a temperature coefficient of a ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/eui_Y8zK7B4" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Bias current generator]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/FNTBzmFPHU0/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441308&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;An electronic device generates a current with a predetermined temperature coefficient. The circuit comprises a temperature coefficient (TC) component receiving a bias current, a differential amplifier providing a buffered output voltage based on the voltage across the TC component and a resistor receiving an TC current based on the differential amplifier output voltage. The differential amplifier has a predetermined input related offset which decreases the voltage drop across the resistor. ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/FNTBzmFPHU0" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Methods and circuits for a low input voltage charge pump]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/5siTPrfzKCo/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441307&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A charge pump circuit comprises a plurality of subcircuits, where the subcircuits are connected to each other in a single or a dual array having a repeating pattern. Each of the subcircuits comprises one or more of the following: an X-channel device having an X-gate terminal, an X-source terminal and an X-drain terminal, a Y-channel device having a Y-gate terminal, a Y-source terminal and a Y-drain terminal, and a capacitor; wherein a first end of the capacitor, the X-drain terminal, and ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/5siTPrfzKCo" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Poly fuse burning system]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/SNHiO6yUa9Y/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441306&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventors:&lt;/strong&gt; &amp;nbsp;; &lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;This invention provides a poly fuse burning system comprising a poly fuse, a controllable power source supplying power for burning the poly fuse, and a monitor circuit monitoring the burning state of the poly fuse, wherein when a targeted burning state is reached, a control signal is output to shut down the controllable power source to stop the ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/SNHiO6yUa9Y" height="1" width="1"/&gt;</description>
			         
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<item>
			         <title><![CDATA[Low-leakage diodes and methods of forming the same]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/MZVFpqxqb1g/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441305&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;Low leakage diodes and methods of forming the same are disclosed. In one embodiment an apparatus includes a designed or parasitic bipolar transistor having an emitter, a base and a collector. The bipolar transistor is configured to operate as a diode, the diode having reverse-biased and forward-biased modes of operation. The emitter and base operate as first and second terminals of the diode, respectively. The collector is configured to receive a collector bias voltage, which is controlled ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/MZVFpqxqb1g" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[High-frequency switch circuit]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/NoNmBh-reVo/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441304&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A high-frequency switch circuit according to the present invention includes at least a first switch connected between a common terminal and a first terminal, and a second switch connected between the common terminal and a second terminal. Each of the first and second switches includes a plurality of field-effect transistors connected in series and each having a body, a source, a drain, and a gate. A compensation capacitance that compensates a parasitic capacitance generated when the first ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/NoNmBh-reVo" height="1" width="1"/&gt;</description>
			         
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			         <title><![CDATA[Analog switching system for low cross-talk]]></title>
			         <link>http://feedproxy.google.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~3/4WFQSzPM3to/description.html</link>
			         <description>&lt;ul&gt;&lt;li&gt;&lt;strong&gt;Patent Number:&lt;/strong&gt; &amp;nbsp;8441303&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Publication Date:&lt;/strong&gt; &amp;nbsp;2013-05-14&lt;/li&gt;&lt;li&gt;&lt;strong&gt;Inventor:&lt;/strong&gt; &amp;nbsp;&lt;/li&gt;&lt;/ul&gt;
&lt;p&gt;A system includes a voltage pump to generate a first pump voltage from an analog voltage signal. The system further includes switching pad to receive an analog signal from an external source and route the analog signal to analog processing circuitry over one or more analog signal busses based on the first pump voltage and the analog voltage ...&lt;br /&gt;&lt;img src="http://feeds.feedburner.com/~r/Patentstorm-Patents-MiscellaneousActiveElectricalNonlinearDevicesCircuitsAndSystems/~4/4WFQSzPM3to" height="1" width="1"/&gt;</description>
			         
			         <guid isPermaLink="false">8441303</guid>
			
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