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Lossy compression technique for video encoder bandwidth reduction using compression error data

Patent Number: 8443275
Publication Date: 2013-05-14
Inventor:

A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error ...

Test circuit for testing execution of a handshake protocol and method for testing execution of handshake protocol

Patent Number: 8443274
Publication Date: 2013-05-14
Inventor:

The present invention relates to a checker circuit for a handshake protocol. The checker circuit detects common errors that occur when two communication unit on execute the handshake protocol. The checker circuit is characterized by a compact circuit design that is associated with reduced susceptibility to circuit errors and a significantly reduced spatial requirement. The invention also relates to a method for checking the execution of the handshake ...

Data dependent NPML detection and systems thereof

Patent Number: 8443273
Publication Date: 2013-05-14
Inventors: ; ;

According to one embodiment, a data detection system includes a coefficient-and-variance engine for selecting which infinite impulse response (IIR) filter and prediction error variance to process and store at any time, and a maximum-likelihood sequence detector. The coefficient-and-variance engine comprises a filter bank storing a plurality of IIR filters that represent a plurality of data-dependent noise whitening or noise prediction filters; a least-mean square (LMS) engine for adapting ...

Methods, algorithms, software, circuits, receivers and systems for decoding convolutional code

Patent Number: 8443272
Publication Date: 2013-05-14
Inventors: ; ;

Methods, software, circuits and systems involving a low complexity, tailbiting decoder. In various embodiments, the method relates to concatenating an initial and/or terminal subblock of the serial data block and outputting decoded data from an internal block of the modified data block. The circuitry generally includes a buffer, logic configured to concatenate an initial and/or terminal subblock to the serial data block, and a decoder configured to decode the data block, estimate starting ...

Systems and methods for dual process data decoding

Patent Number: 8443271
Publication Date: 2013-05-14
Inventors: ; ; ;

Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding system. The data decoding system includes a data decoder circuit and a simplified maximum likelihood value modification circuit. The data decoder circuit is operable to apply a data decode algorithm to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded ...

Multiple input hardware reuse using LDPC codes

Patent Number: 8443270
Publication Date: 2013-05-14
Inventor:

A network controller receives data substantially simultaneously from multiple client nodes. The network controller assigns to each client node one or more sub-carriers of an orthogonal frequency-division multiplexing access frequency spectrum. The client nodes transmit substantially simultaneously M LDPC codewords that are encoded in a parity check matrix so that the number of rows m′ depend on the code rate and are mapped on its assigned sub-carriers. The network controller computes a ...

System and method for handling forward error correction code blocks in a receiver

Patent Number: 8443269
Publication Date: 2013-05-14
Inventor:

A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be ...

Method of performing interleaving and data transmission apparatus

Patent Number: 8443268
Publication Date: 2013-05-14
Inventors: ;

A method of performing interleaving and a data transmission apparatus are disclosed, in which interleaving is performed for input data streams using bit reverse ordering (BRO) operation. A method of performing interleaving for input data streams comprises writing respective bits of the input data stream in a row direction of a memory matrix in accordance with the input order, performing row permutation for index of each row of the memory matrix using an R-bit (R is an integer) bit reverse ...

Systems and methods for hard decision assisted decoding

Patent Number: 8443267
Publication Date: 2013-05-14
Inventors: ; ; ;

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a processing loop circuit having a data detector and a soft decision decoder. The data detector provides a detected output, and the soft decision decoder applies a soft decoding algorithm to a derivative of the detected output to yield a soft decision output and a first hard decision output. The systems further include a queuing ...

Data processing method and data processor

Patent Number: 8443266
Publication Date: 2013-05-14
Inventor:

A data processing method includes checking an error on a first header, and determining whether or not to correct the error on the first header based on an error correction count for an first error correction processing block including the first ...

Method and apparatus for map decoding and turbo decoder using the same

Patent Number: 8443265
Publication Date: 2013-05-14
Inventor:

A Maximum A Posteriori (MAP) decoder and a MAP decoding method are provided. The MAP decoder includes a first metric operation unit, a first bit-width control unit, a second metric operation unit, a Log Likelihood Ratio (LLR) operation unit, and a second bit-width control unit. The first metric operation unit outputs a first metric data using an input data. The first bit-width control unit controls a bit-width of the first metric data according to a modulation scheme of the input data. The ...

Disk array apparatus, a disk array apparatus control method and a program for a disk array apparatus

Patent Number: 8443264
Publication Date: 2013-05-14
Inventor:

A disk array apparatus includes a plurality of magnetic disks, and a RAID controller that generates redundancy data for host data received from a host apparatus by a primitive polynomial of Galois extension field, generates a redundancy code for the host data and the redundancy data, the redundancy code is a cyclic code calculated by a generating polynomial identical to the primitive polynomial, and writes the host data and the redundancy data to the plurality of magnetic ...

Method and controller for performing a copy-back operation

Patent Number: 8443263
Publication Date: 2013-05-14
Inventors: ;

The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program ...

Adaptive memory scrub rate

Patent Number: 8443262
Publication Date: 2013-05-14
Inventor:

In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at ...

Transparent recovery from hardware memory errors

Patent Number: 8443261
Publication Date: 2013-05-14
Inventors: ; ; ;

A method is provided for recovering from an uncorrected memory error located at a memory address as identified by a memory device. A stored hash value for a memory page corresponding to the identified memory address is used to determine the correct data. Because the memory device specifies the location of the corrupted data, and the size of the window where the corruption occurred, the stored hash can be used to verify memory page reconstruction. With the known good part of the data in ...

Error correction in copy back memory operations

Patent Number: 8443260
Publication Date: 2013-05-14
Inventors: ; ;

A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, ...

Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storage

Patent Number: 8443259
Publication Date: 2013-05-14
Inventors: ; ; ; ; ;

An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data ...

Memory device including memory controller

Patent Number: 8443258
Publication Date: 2013-05-14
Inventor:

A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, ...

Rate-scalable, multistage quasi-cyclic LDPC coding

Patent Number: 8443257
Publication Date: 2013-05-14
Inventors: ; ;

Encoding is performed by dividing a quasi-cyclic low-density parity-check (QC-LDPC) parity check matrix into a first sub-matrix and a second sub-matrix. The first sub-matrix includes a plurality of circulant vectors and the plurality of circulant vectors is associated with a circulant size. Input data is received having a length which is a product of an integer multiplier and the circulant size. A first stage of multi-stage LDPC encoding is performed using the input data and a subset of the ...

Method and apparatus for determining a cyclic redundancy check (CRC) for a data message

Patent Number: 8443256
Publication Date: 2013-05-14
Inventors: ;

A method of creatine a CRC (Cyclic Redundancy Check) code for a data message in a data communications system includes sequentially placing portions of the data message on a bus of width W bits consisting of an integral number N of segments of width S. An initial portion of the message fills n complete segments, where n

Parity check matrix optimization and selection for iterative decoding

Patent Number: 8443255
Publication Date: 2013-05-14
Inventors: ;

A method of generating a parity check matrix for iterative decoding of a linear block code includes: determining a set of parity check vectors for the linear block code; ordering according to Hamming weight non-zero parity check vectors of the set; selecting a criterion for generating the parity check matrix; and building the parity check matrix by incrementally selecting according to the criterion a parity check vector for each consecutive row of the parity check matrix, wherein the parity ...

Method of generating a parity check matrix for LDPC encoding and decoding

Patent Number: 8443254
Publication Date: 2013-05-14
Inventor:

A method of encoding input data using a low density parity check (LDPC) code or decoding the encoded data is disclosed. Each index of a model matrix is expanded to an index matrix which includes two or more indexes. Each index included in the index matrix indicates a specific sub-matrix, and can be replaced with a corresponding sub-matrix to generate a parity check ...

Turbo decoding device and communication device

Patent Number: 8443253
Publication Date: 2013-05-14
Inventors: ;

A turbo decoding device includes a memory unit that stores data in an interleaving process performed in a process of decoding a coded signal encoded with a turbo code and an access unit that accesses the memory unit to read and write the data. The memory unit includes memory circuits and is formed as one memory space by coupling the memory circuits. Furthermore, the memory circuit functions as a first bank configuration by which a first capacity is assigned to each bank or a second bank ...

Method and system of relaying data

Patent Number: 8443252
Publication Date: 2013-05-14
Inventors: ;

A method and system of relaying data are provided. The data is encoded into a turbo codeword by using a convolutional turbo code encoder, and the turbo codeword is transmitted from a source to a relay and a destination after puncturing by a first puncturing operation. The first punctured turbo codeword which is received in the relay is de-punctured and regenerated in a decoding operation and the regenerated turbo codeword is transmitted from the relay to the destination in punctured form ...

Systems and methods for out of order processing in a data retry

Patent Number: 8443251
Publication Date: 2013-05-14
Inventors: ; ;

Various embodiments of the present invention provide systems and methods for data processing that includes selectively reporting results out of order or in ...

Systems and methods for error correction using irregular low density parity check codes

Patent Number: 8443250
Publication Date: 2013-05-14
Inventors: ;

Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix ...

Systems and methods for low density parity check data encoding

Patent Number: 8443249
Publication Date: 2013-05-14
Inventors: ;

Various embodiments of the present invention provide systems and methods for encoding data. As an example, a data encoding circuit is disclosed that includes a first stage data encoder circuit and a second stage data encoder circuit. The first stage data encoder circuit is operable to provide a first stage output. The first stage data encoder circuit includes a first vector multiplier circuit operable to receive a data input and to multiply the data input by a first sparse matrix to yield a ...

Method for decoding data packets in a wireless communication system

Patent Number: 8443248
Publication Date: 2013-05-14
Inventor:

A method is provided for decoding data packets in wireless communication schemes that use a Hybrid Automatic Repeat Request technique, and a receiver for wireless communication that performs such a method. The HARQ memory incorporated in a receiver for wireless communication is minimized to a size which only reserves memory for an average number of erroneous sub-packets. Following decoding, an error check is performed on a per sub-packet basis, and only the softbits of those sub-packets for ...

Methods and systems using window start update for wireless communication HARQ connection

Patent Number: 8443247
Publication Date: 2013-05-14
Inventor:

Embodiments of the present disclosure allow a HARQ transmitter to provide a receiver an indication of the protocol data units (PDUs) that should not be expected because they are part of a data burst that has been retransmitted a maximum allowable number of times. The indication message may contain a maximum serial number contained in the data burst that has reached the maximum number of retransmissions, or the serial number of a first PDU in the next data ...

Control of clock gate cells during scan testing

Patent Number: 8443246
Publication Date: 2013-05-14
Inventor:

A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be ...

Test system having a sub-system to sub-system bridge

Patent Number: 8443245
Publication Date: 2013-05-14
Inventors: ; ; ; ; ;

A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and time efficient. The method analyzes performance data acquired by a first component for one or more circuits, and sends that performance data to a second test ...

Blind and decision directed multi-level channel estimation

Patent Number: 8443244
Publication Date: 2013-05-14
Inventors: ;

A read value that is read from a multi-level storage device is received, as are a set of bins having bin ranges. A set of amounts corresponding to the set of bins is received where each amount in the set indicates an amount of read values which fall into the corresponding bin. One or more of the bin ranges is adjusted, including by: in the event there is a first bin range that is less than the received read value, increasing at least the first bin range and in the event there is a second ...

Semiconductor integrated circuit device and method for evaluating an eye-opening margin

Patent Number: 8443243
Publication Date: 2013-05-14
Inventors: ; ; ;

An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit ...

Systems and methods for multiple coding rates in flash devices

Patent Number: 8443242
Publication Date: 2013-05-14
Inventors: ;

A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading ...

Runtime dynamic performance skew elimination

Patent Number: 8443241
Publication Date: 2013-05-14
Inventors: ; ;

For runtime dynamic performance skew elimination in a computer environment, an exemplary computer environment is configured for calculating a rank heats by utilizing a plurality of fine-grained statistics collected at an extent granularity, including considering bandwidth (BW) and input/outputs per second (IOPS) metrics. An adaptive data placement plan is generated to relocate the data. The data is placed among data storage ranks. The data storage ranks are balanced according to the ...

Method in a gaming machine for providing data recovery

Patent Number: 8443240
Publication Date: 2013-05-14
Inventor:

Disclosed is a gaming machine capable of data ...

High resiliency network infrastructure

Patent Number: 8443239
Publication Date: 2013-05-14
Inventor:

The invention provides a highly resilient network infrastructure that provides connectivity between a main network such as the Internet and a subnetwork such as a server-based (e.g., web server) local area network. In accordance with the invention, a network interface incorporated into a server hosting center provides a resilient architecture that achieves redundancy in each of three different layers of the Open System Interconnect (OSI) stack protocol (i.e., physical interface, data link, ...

System and method for testing hard disk ports

Patent Number: 8443238
Publication Date: 2013-05-14
Inventors: ;

A method tests hard disk ports located on a motherboard of a computing device. Each of the hard disk ports connects to a respective serial port of a test fixture. The test fixture includes a group of serial ports, a multiplexer and a storage device. Each of the hard disk ports is selected to be tested during the process of hard disk ports test. A data transmission path is formed by building a connection between the storage device and a channel of the multiplexer corresponding to the hard ...

Storage apparatus and method for controlling the same using loopback diagnosis to detect failure

Patent Number: 8443237
Publication Date: 2013-05-14
Inventors: ;

An objective is to allow a storage apparatus to accurately locate a failure site upon occurrence of a failure. Provided is a storage apparatus 10 including: a controller 11 that performs data input and data output into and from a storage drive 171 in response to a data input/output request sent from an external device 2; and expanders 112, 121 each having a switch circuit 1122 provided with a physical port (Phy 1121). In this storage ...

Test apparatus for testing an information processing apparatus

Patent Number: 8443236
Publication Date: 2013-05-14
Inventor:

A test apparatus for testing an information processing apparatus includes a control unit connected to the control signal line through the connector unit to receive command information from the processing unit to execute the program, and a switching unit connected to the control unit to connect the second communication signal line and the fourth communication signal line under the control of the control ...

Storage system and known problem information management method

Patent Number: 8443235
Publication Date: 2013-05-14
Inventors: ;

Proposed are a highly reliable storage system capable of inhibiting the problematic operation or change of state in the storage system, and a known problem information management method capable of improving the reliability of the storage system. The storage system is provided with a storage apparatus including a storage medium for storing data, and a management apparatus for managing the storage apparatus. The management apparatus includes an apparatus-side known problem information storage ...

Bios refresh device and method using the same

Patent Number: 8443234
Publication Date: 2013-05-14
Inventor:

A BIOS refresh device includes a first socket, a second socket, and a jumper. The first socket includes a first elastic contact, a first voltage contact, and a first ground contact. The second socket includes a second elastic contact, a second voltage contact, and a second ground contact. The jumper includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is electronically connected with the second elastic contact. The second pin is electronically connected with the ...

Methods and systems for failure isolation and data recovery in a configuration of series-connected semiconductor devices

Patent Number: 8443233
Publication Date: 2013-05-14
Inventor:

A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected ...

Automatic clusterwide fail-back

Patent Number: 8443232
Publication Date: 2013-05-14
Inventors: ;

Systems and procedures may be used to coordinate the fail-back of multiple hosts in environments where the hosts share one or more data-storage resources. In one implementation, a procedure for coordinating fail-backs includes monitoring a failed data path to detect a restoration of the data path, polling remaining nodes in response to the restoration, and allowing the first node to resume communications if access has been restored to the remaining ...

Updating a list of quorum disks

Patent Number: 8443231
Publication Date: 2013-05-14
Inventors: ; ; ;

A node in a server cluster is designated as a quorum disk. The node stores a list of other nodes in the server cluster also designated as quorum disks. The node can replace the first list with a second and more recent list of quorum disks only if the second list is updated on at least a simple majority of quorum disks on the first ...

Methods and systems with transaction-level lockstep

Patent Number: 8443230
Publication Date: 2013-05-14
Inventors: ; ; ; ;

Methods and systems for redundant operation of a first and second processor are provided. A set of instructions is executed in parallel on the first and second processors. In response to a first access transaction for a peripheral device being issued from execution of an instruction by the first processor, the first processor suspends operation. In response to the first access transaction being a write transaction, the write transaction is not issued to the peripheral device until the ...

Transitional replacement of operations performed by a central hub

Patent Number: 8443228
Publication Date: 2013-05-14
Inventors: ;

A central hub is coupled to a plurality of computational devices. The central hub stores a data structure that grants locks for accessing common data stored at the central hub, wherein the common data is shared by the plurality of computational devices. Each computational device maintains locally those locks that are held by the computational device in the data structure stored at the central hub. In response to a failure of the data structure stored at the central hub, a selected ...

Processor and method for workaround trigger activated exceptions

Patent Number: 8443227
Publication Date: 2013-05-14
Inventors: ; ; ;

A processor includes a microarchitecture for working around a processing flaw, the microarchitecture including: at least one detector adapted for detecting a predetermined state associated with the processing flaw; and at least one mechanism to modify default processor processing behavior; and upon modification of processing behavior, the processing of an instruction involving the processing flaw can be completed by avoiding the processing ...

Systems and methods for diagnosing and fixing electronic devices

Patent Number: 8443226
Publication Date: 2013-05-14
Inventors: ; ;

Systems and methods for reducing the cost and time required for diagnosing and fixing electronic devices are provided. A host electronic device may be configured to generate a log of events that it experiences. A help component may access the generated log and analyze the log to detect if the host device has experienced a problem. Data may then be exchanged between the help component and the host device in order to fix the detected ...

Distributed transaction management using two-phase commit optimization

Patent Number: 8442962
Publication Date: 2013-05-14
Inventors: ;

A computer-implemented method, a computer-readable medium and a system are provided. A transaction master for each of a plurality of transactions of a database is provided. Each transaction master is configured to communicate with at least one transaction slave to manage execution of a transaction in the plurality of transactions. Each transaction master configured to perform generating a transaction token to specify data to be visible for a transaction on the database, the transaction ...