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Systems and methods for non-periodic pulse sequential lateral solidification

Patent Number: 8440581
Publication Date: 2013-05-14
Inventors: ; ;

The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser ...

Method of fabricating silicon nitride gap-filling layer

Patent Number: 8440580
Publication Date: 2013-05-14
Inventors: ; ;

A method for fabricating a silicon nitride gap-filling layer is provided. A pre-multi-step formation process is performed to form a stacked layer constituting as a dense film on a substrate. Then, a post-single step deposition process is conducted to form a cap layer constituting as a sparse film on the stacked layer, wherein the cap layer has a thickness of at least 10% of the total film ...

Re-establishing surface characteristics of sensitive low-k dielectrics in microstructure device by using an in situ surface modification

Patent Number: 8440579
Publication Date: 2013-05-14
Inventors: ;

Patterning-induced damage of sensitive low-k dielectric materials in semiconductors devices may be restored to a certain degree on the basis of a surface treatment that is performed prior to exposing the device to ambient atmosphere. To this end, the dangling silicon bonds of the silicon oxide-based low-k dielectric material may be saturated in a confined process environment, thereby providing superior surface conditions for the subsequent application of an appropriate repair ...

GCIB process for reducing interfacial roughness following pre-amorphization

Patent Number: 8440578
Publication Date: 2013-05-14
Inventor:

A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a ...

Method for reducing metal, multilayer interconnection structure and manufacturing method for the same, and semiconductor device and manufacturing method for the same

Patent Number: 8440577
Publication Date: 2013-05-14
Inventor:

To provide a reliable, efficient method for reducing oxidized metals used upon manufacturing of the multilayer interconnection structure, semiconductor device, etc. With this method vapor containing at least a carboxylic acid ester is hydrolyzed by water vapor to reduce oxidized metal. The multilayer interconnection manufacturing method of the present invention includes at least film formation step, interconnection formation step, and reduction step using the metal reduction method of the ...

Method for pitch reduction in integrated circuit fabrication

Patent Number: 8440576
Publication Date: 2013-05-14
Inventor:

A method for patterning a material is provided. The method includes patterning a second material over a first material over a substrate. A surface portion of the patterned second material is converted to form a third material and a remaining patterned second material, wherein the third material is around the remaining patterned second material. One of the remaining patterned second material and the third material is removed to form a mask. The first material is patterned by using the ...

Method of fabricating semiconductor device

Patent Number: 8440575
Publication Date: 2013-05-14
Inventor:

A method includes: forming an device isolation region in a substrate to divide the device isolation region into first and second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist ...

Post chromium alloy plasma etch ashing process

Patent Number: 8440574
Publication Date: 2013-05-14
Inventor:

A method for ashing hardened resist from a photoresist patterned chromium alloy post etch using a plasma ashing chemistry which contains no gaseous source of hydrogen and contains a gaseous source of oxygen and a gaseous source of nitrogen with an oxygen to nitrogen atomic ratio of at least ...

Method and apparatus for pattern collapse free wet processing of semiconductor devices

Patent Number: 8440573
Publication Date: 2013-05-14
Inventors: ; ; ;

A method is provided for processing a wafer used in fabricating semiconductor devices. The method can comprise forming high-aspect ratio features on the wafer, which is followed by wet processing and drying. During drying, pattern collapse can occur. This pattern collapse can be repaired to allow for additional processing of the wafer. In some instance, pattern collapse can be repaired via etching where the etching breaks bonds that can have formed during pattern ...

Si etching method

Patent Number: 8440572
Publication Date: 2013-05-14
Inventor:

A Si etching method includes: arranging a silicon substrate or a substrate having a silicon layer in a processing chamber; generating a plasma of an etching gas in the processing chamber; and etching the silicon substrate by the plasma. The etching gas is a gaseous mixture including a Br₂gas and one of a Cl₂gas and a chloride gas. The chloride gas has a mass that is higher than that of the Cl_{2 ...}

Methods for deposition of silicon carbide and silicon carbonitride films

Patent Number: 8440571
Publication Date: 2013-05-14
Inventors: ;

Methods for deposition of silicon carbide films on a substrate surface are provided. The methods include the use of vapor phase carbosilane precursors and may employ plasma enhanced atomic layer deposition processes. The methods may be carried out at temperatures less than 600° C., for example between about 23° C. and about 200° C. or at about 100° C. This silicon carbide layer may then be densified to remove hydrogen content. Additionally, the silicon carbide layer may be exposed to a ...

Method for manufacturing semiconductor device

Patent Number: 8440570
Publication Date: 2013-05-14
Inventor:

The invention defines a pillar pattern or an island pattern by forming a contact hole and filling the contact hole with a hard mask material by using a spacer formation process, so that the mask pattern formation process margin for island (e.g., pillar) pattern formation is increased. Accordingly, the yield and reliability of the formation process of a semiconductor device are ...

Method of eliminating a lithography operation

Patent Number: 8440569
Publication Date: 2013-05-14
Inventors: ;

Methods of semiconductor device fabrication are disclosed. An exemplary method includes processes of depositing a first pattern on a semiconductor substrate, wherein the first pattern defines wide and narrow spaces; depositing spacer material over the first pattern on the substrate; etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of a wide space defined by the first ...

Substrate etching method and system

Patent Number: 8440568
Publication Date: 2013-05-14
Inventor:

The etching method includes etching the silicon oxide film by supplying a halogen-containing gas and a basic gas to the substrate so that the silicon oxide film is chemically reacted with the halogen-containing gas and the basic gas to generate a condensation layer; etching silicon by supplying a silicon etching gas, which includes at least one selected from the group consisting of an F₂gas, an XeF₂gas, and a ClF₃gas, to the substrate; and after the ...

Semiconductor processing methods

Patent Number: 8440567
Publication Date: 2013-05-14
Inventors: ; ;

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the ...

Method for forming an aluminum nitride thin film

Patent Number: 8440566
Publication Date: 2013-05-14
Inventor:

The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin ...

Semiconductor apparatus manufacturing method and semiconductor apparatus

Patent Number: 8440565
Publication Date: 2013-05-14
Inventor:

There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; ...

Schemes for forming barrier layers for copper in interconnect structures

Patent Number: 8440564
Publication Date: 2013-05-14
Inventors: ;

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and ...

Film forming method and processing system

Patent Number: 8440563
Publication Date: 2013-05-14
Inventor:

Provided is a film-forming method for performing a film-forming process on a surface of a target substrate to be processed in an evacuable processing chamber, a recessed portion being formed on the surface of the target substrate. The method includes a transition metal-containing film processing process in which a transition metal-containing film is formed by a heat treatment by using a source gas containing a transition metal; and a metal film forming process in which a metal film ...

Germanium-containing dielectric barrier for low-K process

Patent Number: 8440562
Publication Date: 2013-05-14
Inventors: ;

A semiconductor structure and methods of forming the same are provided. The semiconductor structure includes a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive wiring in the first dielectric layer; and a copper germanide nitride layer over the conductive ...

Three-dimensional semiconductor device comprising an inter-die connection on the basis of functional molecules

Patent Number: 8440561
Publication Date: 2013-05-14
Inventor:

In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor ...

Method for fabricating tungsten line and method for fabricating gate of semiconductor device using the same

Patent Number: 8440560
Publication Date: 2013-05-14
Inventor:

A method for fabricating a tungsten (W) line includes forming a silicon-containing layer, forming a diffusion barrier layer over the silicon-containing layer, forming a tungsten layer over the diffusion barrier layer, and performing a thermal treatment process on the tungsten layer to increase a grain size of the tungsten ...

Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer

Patent Number: 8440559
Publication Date: 2013-05-14
Inventor:

Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The ...

Semiconductor device and method of fabricating the same

Patent Number: 8440558
Publication Date: 2013-05-14
Inventor:

There is provided a semiconductor device and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, wherein the transistor structure comprises a gate region and a source/drain region, and the gate region comprises a gate dielectric layer provided on the semiconductor substrate and a sacrificial gate formed on the gate dielectric layer; depositing a first interlayer dielectric layer, and ...

Method for fabricating a semiconductor device by considering the extinction coefficient during etching of an interlayer insulating film

Patent Number: 8440557
Publication Date: 2013-05-14
Inventor:

The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction ...

Forming conformal metallic platinum zinc films for semiconductor devices

Patent Number: 8440556
Publication Date: 2013-05-14
Inventors: ;

Forming conformal platinum-zinc films for semiconductor devices is described. In one example, a conformal film is formed by heating a substrate in a reaction chamber, exposing a desired region of the substrate to a precursor that contains platinum, purging excess precursor from the chamber, exposing the desired region of the substrate to a co-reactant containing zinc to cause a reaction between the precursor and the co-reactant to form a platinum zinc film on the desired region, and purging ...

Method for analyzing electrolytic copper plating solution

Patent Number: 8440555
Publication Date: 2013-05-14
Inventor:

Effective fillability and the uniformity electrodeposition of a copper electroplating solution is judged by determining the time-dependent potential change thereof at a cathode current density of 0.1-20 A/dm². The potential change is determined at a working electrode rotation of 100-7500 rpm, and the fillability with the solution is judged from the curve profile. In an embodiment of the present invention, the fillability is judged by obtaining the potential change speed in the ...

Through via connected backside embedded circuit features structure and method

Patent Number: 8440554
Publication Date: 2013-05-14
Inventors: ;

A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array ...

Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate and in a semiconductor device

Patent Number: 8440553
Publication Date: 2013-05-14
Inventors: ;

Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing (100) platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing (102) platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming (104) a ...

Method to form low series resistance transistor devices on silicon on insulator layer

Patent Number: 8440552
Publication Date: 2013-05-14
Inventors: ; ; ; ;

A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of ...

Plasma doping method and manufacturing method of semiconductor device

Patent Number: 8440551
Publication Date: 2013-05-14
Inventor:

A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon ...

Method for forming strained layer with high Ge content on substrate and semiconductor structure

Patent Number: 8440550
Publication Date: 2013-05-14
Inventor:

A semiconductor structure and a method for forming the same are provided. The semiconductor structure may comprise a substrate (110); an insulation layer (120) formed on the substrate (110); a strained layer (130) formed on the insulation layer (120); a strained layer (140) with high Ge content formed on the strained layer (130); and a gate stack (160) formed on the strained layer (140) with high Ge ...

Compound semiconductor device including aln layer of controlled skewness

Patent Number: 8440549
Publication Date: 2013-05-14
Inventors: ; ;

A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AlN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is ...

Manufacturing method of microcrystalline silicon film and manufacturing method of thin film transistor

Patent Number: 8440548
Publication Date: 2013-05-14
Inventors: ;

An object is to provide a manufacturing method of a microcrystalline silicon film with improved adhesion between an insulating film and the microcrystalline silicon film. The microcrystalline silicon film is formed in the following manner. Over an insulating film, a microcrystalline silicon grain having a height that allows the microcrystalline silicon grain to be completely oxidized by later plasma oxidation (e.g., a height greater than 0 nm and less than or equal to 5 nm), or a ...

Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering

Patent Number: 8440547
Publication Date: 2013-05-14
Inventors: ; ;

Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent ...

Methods and devices for fabricating and assembling printable semiconductor elements

Patent Number: 8440546
Publication Date: 2013-05-14
Inventors: ; ; ; ;

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices ...

Method of manufacturing semiconductor device with spraying fluid

Patent Number: 8440545
Publication Date: 2013-05-14
Inventor:

A method of manufacturing a semiconductor device includes spraying fluid onto a surface of a treatment target substrate including a semiconductor substrate; forming a protection layer on the surface of the treatment target substrate after spraying the fluid; selectively removing the protection layer and a part of the treatment target substrate by an energy beam; and conducting removal processing on an area of the treatment target substrate from which the protection layer and the part of the ...

CMOS structure and method of manufacture

Patent Number: 8440544
Publication Date: 2013-05-14
Inventors: ; ;

CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding ...

Hybrid circuit structure and partial backfill method for improving thermal cycling reliability of same

Patent Number: 8440543
Publication Date: 2013-05-14
Inventors: ;

A method of improving thermal cycling reliability for a hybrid circuit structure requires providing at least two circuit layers, aligning two of the circuit layers vertically such that their respective circuit elements have a precise and well-defined spatial relationship, and providing an adhesive material which wicks into a portion of the space between the aligned layers so as to mitigate damage to the structure and/or interconnections that might otherwise occur due to thermal contraction ...

Semiconductor device and structure

Patent Number: 8440542
Publication Date: 2013-05-14
Inventor:

A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first ...

Methods for reducing the width of the unbonded region in SOI structures

Patent Number: 8440541
Publication Date: 2013-05-14
Inventors: ; ;

The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also ...

Method for doping a selected portion of a device

Patent Number: 8440540
Publication Date: 2013-05-14
Inventors: ; ;

A method includes forming a protective layer with an opening over a substrate, thereafter implanting a dopant into a substrate region through the opening, the protective layer protecting a different substrate region, and reducing thickness of the protective layer. A different aspect includes etching a substrate to form a recess therein, thereafter implanting a dopant into a substrate region within the recess and through an opening in a protective layer provided over the substrate, and ...

Isolation trench processing for strain control

Patent Number: 8440539
Publication Date: 2013-05-14
Inventor:

A semiconductor fabrication process includes forming a hard mask, e.g., silicon nitride, over an active layer of a silicon on insulator (SOI) wafer, removing a portion of the hard mask and the active layer to form a trench, and forming an isolation dielectric in the trench where the dielectric exerts compressive strain on a channel region of the active layer. Forming the dielectric may include performing a thermal oxidation. Before performing the thermal oxidation, semiconductor structures ...

Method of manufacturing airbridge

Patent Number: 8440538
Publication Date: 2013-05-14
Inventor:

In making an airbridge structure, a second resist layer is applied over a first resist layer. The resist layers are exposed and developed to have a predetermined width W₂. A third resist layer is applied. The third resist layer is also exposed and developed to have a predetermined width W₃. An airbridge-forming material layer is applied to the layer stack structure consisting of the first, second, and third resist layers, forming an airbridge. The resist layers are ...

Adsorption site blocking method for co-doping ALD films

Patent Number: 8440537
Publication Date: 2013-05-14
Inventors: ; ;

A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the ...

Mask layout and method for forming vertical channel transistor in semiconductor device using the same

Patent Number: 8440536
Publication Date: 2013-05-14
Inventor:

A method for forming a vertical channel transistor in a semiconductor memory device includes: forming a plurality of pillars over a substrate so that the plurality of pillars are arranged in a first direction and a second direction crossing the first direction, and so that each of the pillars has a hard mask pattern thereon; forming an insulation layer to fill a regions between the pillars; forming a mask pattern over a resultant structure including the insulation layer, wherein the mask ...

Forming a phase change memory with an ovonic threshold switch

Patent Number: 8440535
Publication Date: 2013-05-14
Inventor:

A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage ...

Threshold adjustment for MOS devices by adapting a spacer width prior to implantation

Patent Number: 8440534
Publication Date: 2013-05-14
Inventors: ; ; ; ; ;

Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing ...

Self-aligned contact for replacement metal gate and silicide last processes

Patent Number: 8440533
Publication Date: 2013-05-14
Inventor:

A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the ...

Structure and method for making metal semiconductor field effect transistor (MOSFET) with isolation last process

Patent Number: 8440532
Publication Date: 2013-05-14
Inventors: ; ;

In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the ...