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Four logic state voltage to two output decompressor IC

Patent Number: 8441286
Publication Date: 2013-05-14
Inventor:

Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit ...

Latching control buffer between functional logic and tri-state output buffer

Patent Number: 8441285
Publication Date: 2013-05-14
Inventor:

An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer ...

Flexible updating of multi-bit registers

Patent Number: 8441284
Publication Date: 2013-05-14
Inventors: ; ;

Various techniques are provided to flexibly update data fields stored in multi-bit registers. In one example, a method of updating a control register within an integrated circuit includes storing a plurality of initial bit values in the control register within the integrated circuit. The method also includes receiving a data set comprising one or more corrective bit values and one or more non-corrective bit values. The method also includes performing a logic operation on the received data ...

Integrated circuit

Patent Number: 8441283
Publication Date: 2013-05-14
Inventor:

An integrated circuit includes: an on-die-termination (ODT) circuit configured to drive an input signal with drivability adjusted according to an impedance calibration code and a reference voltage; and an input buffer configured to buffer the input signal in response to the reference voltage and generate an output ...

Impedance calibration circuit and impedance calibration method

Patent Number: 8441282
Publication Date: 2013-05-14
Inventor:

An integrated circuit includes a first ODT (On Die Termination) unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code and calibrate a resistance value for impedance matching of a first line transferring data. The input buffer is configured to buffer the data in response to a reference voltage level and drive input data. Herein, the driving of the input data is controlled in response to the pull-up code and the ...

Current-mode logic buffer with enhanced output swing

Patent Number: 8441281
Publication Date: 2013-05-14
Inventors: ; ;

A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias ...

Safety component in a programmable components chain

Patent Number: 8441280
Publication Date: 2013-05-14
Inventor:

An electronic circuit includes a plurality of programmable components connected in an electronic chain. An interface is adapted to connect the programmable components to an external controller wherein the controller is adapted to program the programmable components. A component isolation element is connected to the interface at an input end and to the electronic chain of the programmable components at an output end wherein the isolation element is adapted to isolate one component of the ...

Scan flip-flop circuits and scan test circuits including the same

Patent Number: 8441279
Publication Date: 2013-05-14
Inventors: ;

A scan flip-flop circuit includes an input unit and an output unit. The input unit selects one of a data input signal and a scan input signal depending on an operation mode and generates an intermediate signal based on the selected signal. The output unit generates an output signal based on the intermediate signal and selects one of a data output terminal and a scan output terminal depending on the operation mode to provide the output signal through the selected output terminal. A voltage ...

Apparatus for designing semiconductor integrated circuit, method of designing semiconductor integrated circuit, and program for designing semiconductor integrated circuit

Patent Number: 8438518
Publication Date: 2013-05-07
Inventor:

A device comprises a analysis section for detecting hold errors according to data including the values of the input and output nodes of the FF circuit, and identifying the node in which a hold error has occurred, a determining section for determining insertion of the trailing edge FF or the buffer into hold error sections on the basis of the results of the analysis by the analysis section, a FF insertion section for inserting the FF into a hold error section subjected to position ...

Method and apparatus for signaling characteristics of a transmitted signal

Patent Number: 8436658
Publication Date: 2013-05-07
Inventor:

A method and apparatus are provided that allow exploitation of the common mode characteristics of a differential transmission network to provide an additional data signal. Signal represents either a binary signal or a multi-valued signal to allow signaling of one or more bits of information. The signaling occurs through the variation of the common mode voltage in transmitters and is detected using differential receiver. One embodiment is presented that achieves signaling of an extended run ...

Semiconductor device having output driver

Patent Number: 8436657
Publication Date: 2013-05-07
Inventor:

To provide an output driver that outputs read data to outside and a mode register that sets a swing capability of the output driver. A transition start timing of the read data driven by the output driver is made relatively earlier when a swing capability of the output driver set by the mode register is set to be relatively large, and the transition start timing is relatively delayed when the swing capability of the output driver set by the mode register is set to be relatively small. With ...

Method and apparatus for saving power in an integrated circuit

Patent Number: 8436656
Publication Date: 2013-05-07
Inventors: ; ; ;

Some embodiments provide an integrated circuit (‘IC’) that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing ...

Voltage level shift circuit and semiconductor device

Patent Number: 8436655
Publication Date: 2013-05-07
Inventor:

A voltage level shift circuit in which a difference in response characteristic depending on the signal level of an input signal is suppressed. The voltage level shift circuit generates an output signal VOUT having a voltage amplitude different from that of the input signal. An inverter INV2 generates a voltage V1 in the range of VSS to VDDI according to the input signal. An inverter INV3 generates a voltage V2 in the range of VSS to VPERI according to the input ...

Level converter circuit for use in CMOS circuit device provided for converting signal level of digital signal to higher level

Patent Number: 8436654
Publication Date: 2013-05-07
Inventors: ;

A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current ...

Low power multi-level signaling

Patent Number: 8436653
Publication Date: 2013-05-07
Inventor:

Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second ...

Dual-edge register and the monitoring thereof on the basis of a clock

Patent Number: 8436652
Publication Date: 2013-05-07
Inventor:

Sequential electronic circuit (10) reacting on a rising edge and a falling edge of a clock signal (CK), comprising a first (1) and a second (2) D-type flip-flop, a main multiplexer (3) coupled at input to the flip-flops (1 and 2), the circuit (10) comprising a first input receiving the clock signal (CK) and a second input receiving a control signal (TE) so as to control the circuit (10) according to a normal operating mode and a test ...

Command control circuit for semiconductor integrated device

Patent Number: 8436651
Publication Date: 2013-05-07
Inventor:

A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of ...

Programmable logic device

Patent Number: 8436650
Publication Date: 2013-05-07
Inventors: ;

A programmable logic device includes a plurality of logic blocks and a plurality of routing networks. One of the plurality of routing networks includes a first selection circuit, a second selection circuit, and an auxiliary power connector circuit. The first selection circuit is connected to the second selection circuit via a signal line. The signal line is connected to a power supply line via the auxiliary power connector ...

Semiconductor device, information processing apparatus, and method for configuring circuits of semiconductor device

Patent Number: 8436649
Publication Date: 2013-05-07
Inventor:

Disclosed is a semiconductor device including a circuit information supply unit that supplies circuit information acquired from an outside of the semiconductor device; circuit configuration units that configure respective circuits based on the circuit information supplied from the circuit information supply unit; a specification unit that specifies whether to execute circuit configuration with respect to the circuit configuration unit; and a signal fixation unit that fixes values of signals ...

Voltage sequence output circuit

Patent Number: 8436648
Publication Date: 2013-05-07
Inventor:

A sequential voltage output circuit is connected between a power supply and a number of loads. The voltage sequence output circuit includes a complex programmable logic device (CPLD) and a number of switching circuits. When the CPLD receives a power on signal, the CPLD outputs a number of control signals sequentially through a number of outputs. When a switching circuit receives a control signal from the CPLD, the switching circuit allows the power supply to supply power to a corresponding ...

Pipeline power gating for gates with multiple destinations

Patent Number: 8436647
Publication Date: 2013-05-07
Inventor:

A first and second plurality of gates are coupled respectively between first and second source storage elements and first and second destination storage elements. The first and second plurality of gates are slept to reduce leakage current in the plurality of gates under certain conditions by turning off respective one or more transistors between the first and second plurality of gates and power supplies. A third plurality of gates are maintained in a reduced leakage current state (sleep ...

Reconfigurable logic block with user RAM

Patent Number: 8436646
Publication Date: 2013-05-07
Inventors: ; ; ;

A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. If the mode flag indicates a design state, the configuration logic associated with the logic block is included in data verification and correction processes. ...

Information generating apparatus and operation method thereof

Patent Number: 8436645
Publication Date: 2013-05-07
Inventor:

An information generating apparatus and an operation method thereof are provided. The information generating apparatus includes a first logic contact, a second logic contact, an information output contact and a plurality of switches SW_(i,j), wherein SW_(i,j)represents a j^thswitch in an i^thlayer, 1≦i≦L, and 1≦j≦2⁽ⁱ⁻¹⁾. The switch SW_(i,j)has a first input terminal, a second input terminal and an output terminal, ...

Configuration method and FPGA circuit re-executing configuration based on adjusted configuration data

Patent Number: 8436644
Publication Date: 2013-05-07
Inventor:

A configuration method performs a configuration of a FPGA circuit by setting configuration data from a configuration circuit to the FPGA circuit. The method counts, within the FPGA circuit, a number of times a configuration of the FPGA circuit fails. The method adjusts, within the FPGA circuit, the configuration data at a time when the configuration failed if the counted number exceeds an upper limit value, and re-executes the configuration based on the adjusted configuration data. The ...

High frequency solid state switching for impedance matching

Patent Number: 8436643
Publication Date: 2013-05-07
Inventor:

In accordance with this invention the above and other problems are solved by a switching apparatus and method that uses a switching circuit having a pair of parallel solid-state diodes (e.g., PN diodes), one of which is connected to a transistor (e.g., power MOSFET or IGBT), to switch a capacitor in or out of a variable capacitance element of an impedance matching network. Charging a body capacitance of the transistor reverse biases one of the two diodes so as to isolate the transistor from ...

Control of termination capacitance for maximum transmitter bandwidth extension

Patent Number: 8436642
Publication Date: 2013-05-07
Inventors: ;

An integrated circuit device includes an input/output (IO) pad, and a programmable termination capacitance circuit coupled to the IO pad, the programmable termination capacitance circuit comprising at least one compensation bank, wherein each of the at least one compensation bank includes a compensation capacitor coupled to a reference voltage through a compensation pass ...

Circuit and method for generating on-die termination signal and semiconductor apparatus using the same

Patent Number: 8436641
Publication Date: 2013-05-07
Inventor:

Various embodiments of an on-die termination (ODT) signal generating circuit are disclosed. In one exemplary embodiment, the ODT signal generating circuit includes a latency unit and an ODT control signal generating unit. The latency unit is configured to receive a clock signal and an ODT signal. The latency unit is configured to delay the ODT signal by a predetermined time to generate a first ODT signal. The latency unit is also configured to delay the ODT signal by less than the ...

Area optimized output impedance controlled driver

Patent Number: 8436640
Publication Date: 2013-05-07
Inventors: ; ;

The present invention significantly reduces the chip size of a metal-oxide-semiconductor (MOS) field-effect transistor, which serves as a driver for output impedance drivers, such as, but not limited to, double data rate (DDR2) synchronous dynamic random access memory (SDRAM). In an embodiment of the invention, a voltage drop across the driver is a decreased ratio of the supply voltage, e.g., three-tenths of the supply voltage, lower than half of the supply voltage. A smaller voltage drop ...

Circuits and methods for testing through-silicon vias

Patent Number: 8436639
Publication Date: 2013-05-07
Inventor:

A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during ...

Switch to perform non-destructive and secure disablement of IC functionality utilizing MEMS and method thereof

Patent Number: 8436638
Publication Date: 2013-05-07
Inventors: ; ; ;

Structures and methods are provided for performing non-destructive and secure disablement of integrated circuit (IC) functionality. A structure for enabling non-destructive and secure disablement and re-enablement of the IC includes a micro-electrical mechanical structure (MEMS) initially set to a chip enable state. The structure also includes an activation circuit operable to set the MEMS device to an error state based on a detected predetermined condition of the IC. The IC is disabled ...

Noise-assisted reprogrammable nanomechanical logic gate and method

Patent Number: 8436637
Publication Date: 2013-05-07
Inventors: ; ; ; ;

A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the ...

Semiconductor device with reduced power consumption

Patent Number: 8432190
Publication Date: 2013-04-30
Inventor:

A semiconductor device includes a reduced-power-consumption circuit block which includes first and second power lines, and a first circuit cell. The first circuit cell includes a first functional-element-free region. The first functional-element-free region includes a first driver circuit configured to connect and disconnect the first power line and the second power ...

Digital voltage level shifter

Patent Number: 8432189
Publication Date: 2013-04-30
Inventors: ; ;

A dual supply bidirectional level shifter performs voltage level shifting in two directions, low to high and high to low. A feedback control branch and a control stage inverter are provided that reduce leakage power and allow for low delay time while also allowing for a small circuit ...

Latch circuit, flip-flop having the same and data latching method

Patent Number: 8432188
Publication Date: 2013-04-30
Inventors: ;

A latch circuit includes a first tri-state inverter configured to invert an input voltage in response to a pulse and to output the inverted voltage to a first node, a second tri-state inverter connected between the first node and a second node and to invert a voltage of the second node in response to an inverted pulse being an inverted version of the pulse, and a variable inversion unit connected between the first node and the second node. The variable inversion unit adjusts a logical ...

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

Patent Number: 8432187
Publication Date: 2013-04-30
Inventor:

To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion configured to hold data of the latch portion. In the data holding portion, a transistor ...

Programmable logic switch

Patent Number: 8432186
Publication Date: 2013-04-30
Inventors: ; ;

One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected ...

Receiver circuits for differential and single-ended signals

Patent Number: 8432185
Publication Date: 2013-04-30
Inventors: ;

Receiver circuits for differential and single-ended signals are disclosed. A receiver may include a differential amplifier configured to receive a first signal of a differential pair at a first input and a second signal of the differential pair at a second input when operating in differential mode, and a single-ended signal at the first input and a reference signal at a third input when operating in single-ended mode. The receiver may also include an inverter coupled to the differential ...

Termination device and system and method for termination for an alarm system peripheral device

Patent Number: 8432184
Publication Date: 2013-04-30
Inventor:

A termination device and a system and a method terminate a peripheral device of an alarm system. The termination device connects to wiring extending from the peripheral device. The termination device may have a resistor, a diode and/or a similar component which provides electrical resistance. The termination device may have a potentiometer which may enable a user to adjust the electrical resistance. The termination device may have a blade which cuts the ...

Element substrate and printed wiring board

Patent Number: 8432183
Publication Date: 2013-04-30
Inventor:

An element substrate includes a plurality of terminals, a first receiving circuit and a second receiving circuit each receiving a differential signal via one of the terminals included in the plurality of terminals, a driving circuit including a first input unit for inputting a first signal and a second input unit for inputting a second signal and driving a driving element based on the first signal and the second signal, and a setting circuit for setting a first connection state of ...

USB isolator with advanced control features

Patent Number: 8432182
Publication Date: 2013-04-30
Inventors: ;

A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator ...

Reconfigurable memristor-based computing logic

Patent Number: 8427203
Publication Date: 2013-04-23
Inventor:

An apparatus for reconfigurable computing logic implemented by an innovative memristor based computing architecture. The invention employs a decoder to select memristor devices whose ON/OFF impedance state will determine the reconfigurable logic output. Thus, the resulting circuit design can be electronically configured and re-configured to implement any multi-input/output Boolean logic computing functionality. Moreover, the invention retains its configured logic state without the ...

Nonvolatile logic circuit and a method for operating the same

Patent Number: 8427202
Publication Date: 2013-04-23
Inventor:

A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration ...

Local result processor

Patent Number: 8427201
Publication Date: 2013-04-23
Inventor:

A system includes a register, a first logical function portion, the first logical function portion operative to receive a first numerical value from the register, perform a first logical function with the first numerical value, and output a second numerical value, a second logical function portion, the second logical function portion operative to receive the first numerical value from the register, perform a second logical function with the first numerical value, and output a third ...

3D semiconductor device

Patent Number: 8427200
Publication Date: 2013-04-23
Inventor:

A semiconductor device includes a first mono-crystallized semiconductor layer; and a second mono-crystallized semiconductor layer; wherein said first and second mono-crystallized semiconductor layers are overlaying one on top of the other, and wherein said first mono-crystallized semiconductor layer comprise repeating memory structure with sub structures defined by ...

Magnetic logic gate

Patent Number: 8427199
Publication Date: 2013-04-23
Inventor:

This disclosure is directed to a magnetic logic device for implementing a combinational logic function. The magnetic logic device may include a network of at least two magnetoresistive devices electrically coupled in parallel. The magnetic logic device may further include a voltage source configured to apply a voltage between a first terminal and a second terminal of the network of at least two magnetoresistive devices electrically coupled in parallel. The magnetic logic device may further ...

Reduced quantization error I/O resistor calibrator

Patent Number: 8427198
Publication Date: 2013-04-23
Inventor:

Calibration circuitry 42 for an off-chip driver circuit 4 and/or an on-die termination circuit 8 is provided using a parallel network of main transistors controlled by a N-bit calibration value. During the calibration operation, the N-bit calibration value is varied until a threshold impedance value is crossed by the combination of the main transistors. A rounding transistor 52 is then used to determine which of the N-bit calibration values produces a combined ...

Configurable reference circuit for logic gates

Patent Number: 8427197
Publication Date: 2013-04-23
Inventor:

This disclosure is directed to techniques for generating a reference current based on a combinational logic function that is to be performed by a magnetic logic device. A comparator circuit may compare an amplitude of a read current that flows through the magnetic logic device and the reference current to generate a logic output value that corresponds to the logic output value when combinational logic function is applied to the input values. By selecting appropriate amplitudes for the ...

System for processing analog-type electrical signals with low noise driving device

Patent Number: 8427196
Publication Date: 2013-04-23
Inventor:

A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to ...

Digital signal generator and automatic test equipment having the same

Patent Number: 8427195
Publication Date: 2013-04-23
Inventors: ; ;

A digital signal generator includes an input unit configured to receive signal information of a target data signal, a controller configured to calculate at least two delay values and at least two data values, the at least two delay values and the at least two data values being used to generate a data signal corresponding to the signal information input through the input unit, a multi-phase clock generator configured to delay a reference clock signal based on the at least two delay values to ...

Logic system with resistance to side-channel attack by exhibiting a closed clock-data eye diagram

Patent Number: 8427194
Publication Date: 2013-04-23
Inventors: ;

An improvement in the security of a logic system by minimizing observable features such as the power supply or electromagnetic radiation, so called, “side-channel attacks”. Specifically, the present invention comprises a technique and methods for reducing the ability of an intruder to monitor the relationship between currents in the system and the data in the system through the use of a randomized clock wherein the clock eye diagram is closed and without significant reduction in maximum ...